cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: LAN_IDE_CP Date: 2-21-2019, 11:38PM Device Used: XC95288XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 243/288 ( 84%) 1180/1440 ( 82%) 603/864 ( 70%) 154/288 ( 53%) 115/117 ( 98%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 41/54 71/90 8/ 8* FB2 16/18 46/54 79/90 10/10* FB3 16/18 39/54 44/90 5/ 5* FB4 18/18* 47/54 86/90 6/ 6* FB5 15/18 50/54 83/90 7/ 8 FB6 18/18* 15/54 28/90 8/ 8* FB7 10/18 32/54 90/90* 4/ 4* FB8 15/18 41/54 83/90 5/ 5* FB9 16/18 49/54 80/90 9/ 9* FB10 11/18 31/54 87/90 10/10* FB11 18/18* 34/54 66/90 7/ 7* FB12 12/18 35/54 89/90 6/ 6* FB13 10/18 41/54 79/90 6/ 6* FB14 17/18 31/54 59/90 7/ 8 FB15 18/18* 41/54 79/90 9/ 9* FB16 16/18 30/54 77/90 8/ 8* ----- ----- ----- ----- 243/288 603/864 1180/1440 115/117 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_EXT' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 23 23 | I/O : 108 109 Output : 43 43 | GCK/IO : 2 3 Bidirectional : 48 48 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 115 115 ** Power Data ** There are 243 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<8> to allow all signals assigned to this function block to be placed. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB10, because too many function block product terms are required. Buffering output signal DQ<4> to allow all signals assigned to this function block to be placed. ************************* Summary of Mapped Logic ************************ ** 91 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D<5> 7 8 FB1_5 20 I/O I/O STD FAST D<4> 7 8 FB1_6 21 I/O I/O STD FAST IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST IDE_R 1 2 FB1_17 27 I/O O STD FAST A_LAN<4> 2 4 FB2_2 9 I/O O STD FAST A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST D<6> 7 8 FB2_10 14 I/O I/O STD FAST D<3> 7 8 FB2_12 15 I/O I/O STD FAST D<7> 7 8 FB2_14 16 I/O I/O STD FAST D<1> 7 8 FB2_15 17 I/O I/O STD FAST D<8> 7 8 FB2_17 19 I/O I/O STD FAST IDE_W 1 2 FB3_2 28 I/O O STD FAST INT2_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST ROM_B<0> 0 0 FB3_15 33 I/O O STD FAST D<0> 7 8 FB4_2 2 GTS/I/O I/O STD FAST A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST A_LAN<3> 3 5 FB4_8 5 GTS/I/O O STD FAST A_LAN<2> 2 4 FB4_12 6 GTS/I/O O STD FAST A_LAN<5> 2 4 FB4_14 7 I/O O STD FAST CP_CS 19 19 FB5_2 34 I/O O STD FAST SET ROM_OE 1 3 FB5_5 35 I/O O STD FAST D<2> 7 8 FB5_10 39 I/O I/O STD FAST D<9> 7 8 FB5_12 40 I/O I/O STD FAST D<10> 7 8 FB5_14 41 I/O I/O STD FAST D<11> 7 8 FB5_15 43 I/O I/O STD FAST D<12> 9 9 FB5_17 44 I/O I/O STD FAST LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST D<13> 9 9 FB7_3 45 I/O I/O STD FAST D<14> 9 9 FB7_5 46 I/O I/O STD FAST D<15> 9 9 FB7_12 48 I/O I/O STD FAST DQ<12> 9 11 FB8_2 130 I/O I/O STD FAST DQ<14> 9 11 FB8_3 131 I/O I/O STD FAST LAN_WRH 3 4 FB8_5 132 I/O O STD FAST LAN_CS 3 4 FB8_8 133 I/O O STD FAST LAN_RD 1 3 FB8_10 134 I/O O STD FAST A<8> 5 8 FB9_11 56 I/O I/O STD FAST RESET A<9> 5 8 FB9_14 58 I/O I/O STD FAST RESET A<10> 5 8 FB9_17 59 I/O I/O STD FAST RESET DQ<1> 10 12 FB10_2 117 I/O I/O STD FAST DQ<0> 9 11 FB10_3 118 I/O I/O STD FAST DQ<3> 9 11 FB10_5 119 I/O I/O STD FAST DQ<2> 9 11 FB10_6 120 I/O I/O STD FAST DQ<5> 9 11 FB10_8 121 I/O I/O STD FAST DQ<4> 2 2 FB10_10 124 I/O I/O STD FAST DQ<7> 9 11 FB10_11 125 I/O I/O STD FAST DQ<6> 9 11 FB10_12 126 I/O I/O STD FAST DQ<8> 2 2 FB10_14 128 I/O I/O STD FAST DQ<10> 10 12 FB10_17 129 I/O I/O STD FAST A<11> 5 8 FB11_3 60 I/O I/O STD FAST RESET A<12> 5 8 FB11_5 61 I/O I/O STD FAST RESET A<13> 5 8 FB11_10 64 I/O I/O STD FAST RESET A<14> 5 8 FB11_11 66 I/O I/O STD FAST RESET INT6_OUT 1 1 FB11_12 68 I/O O STD FAST ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST CP_WE 1 3 FB11_17 70 I/O O STD FAST LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST DQ<15> 9 11 FB12_5 112 I/O I/O STD FAST DQ<13> 9 11 FB12_8 113 I/O I/O STD FAST DQ<11> 10 12 FB12_10 115 I/O I/O STD FAST DQ<9> 10 12 FB12_12 116 I/O I/O STD FAST CP_RD 1 2 FB13_2 71 I/O O STD FAST A<15> 5 8 FB13_8 74 I/O I/O STD FAST RESET LAN_WRL 3 4 FB13_14 76 I/O O STD FAST OVR 1 2 FB14_3 100 I/O O STD FAST CFOUT 1 3 FB14_11 105 I/O O STD FAST SLAVE 4 6 FB14_14 106 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State OWN 0 0 FB14_15 107 I/O O STD FAST DTACK 1 2 FB15_12 85 I/O O STD FAST A<23> 5 8 FB15_14 86 I/O I/O STD FAST RESET A<22> 5 8 FB15_15 87 I/O I/O STD FAST RESET A<21> 5 8 FB15_17 88 I/O I/O STD FAST RESET A<20> 5 8 FB16_2 91 I/O I/O STD FAST RESET A<19> 5 8 FB16_3 92 I/O I/O STD FAST RESET A<18> 5 8 FB16_6 94 I/O I/O STD FAST RESET A<17> 5 8 FB16_8 95 I/O I/O STD FAST RESET MTACK 0 0 FB16_10 96 I/O O STD FAST A<16> 5 8 FB16_11 97 I/O I/O STD FAST RESET ** 152 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State LAN_BASEADR<5> 6 16 FB1_1 STD RESET LAN_BASEADR<9> 6 16 FB1_2 STD RESET D_10_IOBUFE/D_10_IOBUFE_TRST 3 6 FB1_3 STD LAN_BASEADR<7> 6 16 FB1_4 STD RESET LAN_BASEADR<2> 6 16 FB1_9 STD RESET LAN_BASEADR<1> 6 16 FB1_11 STD RESET LAN_BASEADR<15> 6 16 FB1_13 STD RESET LAN_BASEADR<13> 6 16 FB1_16 STD RESET LAN_BASEADR<10> 6 16 FB1_18 STD RESET DQ<8>_BUFR 9 11 FB2_1 STD IDE_BASEADR<3> 6 18 FB2_4 STD RESET IDE_BASEADR<2> 6 18 FB2_7 STD RESET IDE_BASEADR<1> 6 18 FB2_9 STD RESET IDE_BASEADR<0> 6 18 FB2_13 STD RESET DQ_4_IOBUFE/DQ_4_IOBUFE_TRST 6 10 FB2_16 STD LAN_IRQ_OUT 3 4 FB3_1 STD RESET LAN_A_INIT<3> 1 1 FB3_4 STD SET SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 2 2 FB3_5 STD Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D 2 2 FB3_6 STD LAN_RST_SM_FSM_FFd7 2 2 FB3_7 STD RESET LAN_IRQ_D0 2 2 FB3_8 STD RESET CP_WE_QUIRK 2 2 FB3_9 STD RESET $OpTx$FX_DC$84 2 2 FB3_10 STD $OpTx$FX_DC$83 2 2 FB3_11 STD Z3_ADR<9> 3 3 FB3_12 STD RESET Z3_ADR<8> 3 3 FB3_13 STD RESET $OpTx$INV$62 4 4 FB3_16 STD $OpTx$INV$61 14 14 FB3_17 STD SHUT_UP_Z2<2> 4 17 FB4_1 STD SET IDE_BASEADR<7> 6 18 FB4_3 STD RESET IDE_BASEADR<6> 6 18 FB4_4 STD RESET IDE_BASEADR<5> 6 18 FB4_7 STD RESET IDE_BASEADR<4> 6 18 FB4_9 STD RESET CP_BASEADR<7> 6 17 FB4_10 STD RESET CP_BASEADR<6> 6 17 FB4_11 STD RESET CP_BASEADR<5> 6 17 FB4_13 STD RESET CP_BASEADR<4> 6 17 FB4_15 STD RESET CP_BASEADR<2> 6 17 FB4_16 STD RESET CP_BASEADR<1> 6 17 FB4_17 STD RESET CP_BASEADR<0> 6 17 FB4_18 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State AUTOCONFIG_Z2_ACCESS 5 14 FB5_1 STD RESET AUTO_CONFIG_Z2_DONE<2> 4 5 FB5_6 STD RESET AUTO_CONFIG_Z2_DONE_CYCLE<2> 4 16 FB5_7 STD RESET Z3_ADR<2> 3 3 FB5_8 STD RESET Z3_ADR<3> 3 3 FB5_9 STD RESET Z3_ADR<4> 3 3 FB5_11 STD RESET Z3_ADR_1 3 3 FB5_13 STD RESET $OpTx$$OpTx$FX_DC$87_INV$1549 1 2 FB5_16 STD LAN_WR_RST 2 3 FB6_1 STD RESET LAN_RST_SM_FSM_FFd6 2 2 FB6_4 STD RESET LAN_RST_SM_FSM_FFd5 2 2 FB6_7 STD RESET LAN_RST_SM_FSM_FFd4 2 2 FB6_9 STD RESET LAN_RST_SM_FSM_FFd3 2 2 FB6_11 STD RESET LAN_RST_SM_FSM_FFd2 2 2 FB6_12 STD RESET LAN_RST_SM_FSM_FFd1 2 3 FB6_13 STD RESET LAN_D_INIT<8> 2 5 FB6_15 STD RESET LAN_D_INIT<1> 2 5 FB6_16 STD RESET LAN_CS_RST 2 3 FB6_17 STD RESET LAN_A_INIT<6> 2 5 FB6_18 STD SET SHUT_UP_Z2<0> 4 15 FB7_1 STD SET CP_RD_S 3 6 FB7_2 STD RESET AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 15 FB7_4 STD RESET D_Z2_OUT<0> 15 14 FB7_8 STD SET AUTO_CONFIG_Z2_DONE_CYCLE<0> 4 14 FB7_10 STD RESET D_Z2_OUT<1> 17 15 FB7_14 STD SET D_Z2_OUT<2> 16 14 FB7_17 STD SET LAN_BASEADR<8> 6 16 FB8_6 STD RESET LAN_BASEADR<6> 6 16 FB8_7 STD RESET LAN_BASEADR<4> 6 16 FB8_9 STD RESET LAN_BASEADR<3> 6 16 FB8_11 STD RESET LAN_BASEADR<14> 6 16 FB8_12 STD RESET LAN_BASEADR<12> 6 16 FB8_13 STD RESET LAN_BASEADR<11> 6 16 FB8_14 STD RESET LAN_BASEADR<0> 6 16 FB8_15 STD RESET CP_BASEADR<3> 6 17 FB8_16 STD RESET SHUT_UP_Z2<1> 4 16 FB8_18 STD SET LAN_ACCESS 17 17 FB9_2 STD RESET LAN_SM_FSM_FFd1 2 3 FB9_3 STD RESET Z3_ADR<11> 3 3 FB9_4 STD RESET $OpTx$FX_DC$81 2 2 FB9_5 STD Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$INV$63 15 15 FB9_6 STD Z3_ADR<12> 3 3 FB9_8 STD RESET LAN_SM_FSM_FFd13 1 1 FB9_9 STD SET IDE_ENABLE 3 5 FB9_10 STD RESET DQ_SWAP 10 17 FB9_12 STD RESET LAN_SM_FSM_FFd2 2 2 FB9_13 STD RESET IDE_W_S 3 5 FB9_15 STD RESET $OpTx$FX_DC$82 2 2 FB9_16 STD LAN_SM_FSM_FFd4 2 2 FB9_18 STD RESET DQ<4>_BUFR 9 11 FB10_1 STD $OpTx$FX_DC$1248 1 11 FB11_1 STD Z3_DATA<30> 4 5 FB11_2 STD RESET Z3_DATA<29> 4 5 FB11_4 STD RESET Z3_DATA<28> 4 5 FB11_6 STD RESET Z3_DATA<27> 4 5 FB11_7 STD RESET Z3_DATA<22> 4 5 FB11_8 STD RESET Z3_DATA<21> 4 5 FB11_9 STD RESET Z3_DATA<20> 4 5 FB11_13 STD RESET Z3_DATA<19> 4 5 FB11_15 STD RESET LAN_READY 4 10 FB11_16 STD RESET Z3_A_LOW 7 12 FB11_18 STD RESET DQ_DATA<11> 10 12 FB12_1 STD RESET LAN_SM_FSM_FFd8 4 9 FB12_3 STD RESET LAN_SM_FSM_FFd10 3 7 FB12_4 STD RESET LAN_SM_RST 4 8 FB12_6 STD RESET DQ_DATA<5> 10 12 FB12_14 STD RESET DQ_DATA<3> 10 12 FB12_16 STD RESET DQ_DATA<13> 10 12 FB12_18 STD RESET DQ_DATA<10> 10 12 FB13_1 STD RESET DQ_DATA<6> 10 12 FB13_5 STD RESET DQ_DATA<4> 10 12 FB13_7 STD RESET DQ_DATA<2> 10 12 FB13_10 STD RESET DQ_DATA<15> 10 12 FB13_13 STD RESET DQ_DATA<14> 10 12 FB13_16 STD RESET DQ_DATA<12> 10 12 FB13_18 STD RESET D_Z2_OUT<3> 14 14 FB14_2 STD SET AUTO_CONFIG_Z2_DONE<1> 4 5 FB14_4 STD RESET IDE_ACCESS 4 5 FB14_5 STD RESET CP_WE_S 3 6 FB14_6 STD RESET IDE_R_S 3 6 FB14_7 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State ROM_OE_S 3 6 FB14_8 STD RESET Z3_ADR<10> 3 3 FB14_9 STD RESET Z3_ADR<13> 3 3 FB14_10 STD RESET Z3_ADR<5> 3 3 FB14_12 STD RESET Z3_ADR<6> 3 3 FB14_13 STD RESET Z3_ADR<7> 3 3 FB14_16 STD RESET Z3_ADR_0 3 3 FB14_17 STD RESET AUTO_CONFIG_Z2_DONE<0> 4 5 FB14_18 STD RESET DQ_DATA<1> 10 12 FB15_1 STD RESET LAN_SM_FSM_FFd12 2 4 FB15_2 STD RESET LAN_WRL_S 3 5 FB15_3 STD RESET LAN_WRH_S 3 5 FB15_4 STD RESET LAN_SM_FSM_FFd7 3 5 FB15_5 STD RESET LAN_SM_FSM_FFd3 3 5 FB15_6 STD RESET LAN_SM_FSM_FFd9 3 6 FB15_7 STD RESET LAN_SM_FSM_FFd11 3 6 FB15_8 STD RESET LAN_RD_S 4 7 FB15_9 STD RESET DQ_DATA<9> 10 12 FB15_10 STD RESET LAN_SM_FSM_FFd6 3 4 FB15_11 STD RESET DQ_DATA<7> 10 12 FB15_13 STD RESET LAN_INT_ENABLE 4 8 FB15_16 STD RESET LAN_SM_FSM_FFd5 2 3 FB15_18 STD RESET DQ_DATA<0> 10 12 FB16_1 STD RESET DQ_DATA<8> 10 12 FB16_5 STD RESET Z3_DATA<17> 4 5 FB16_7 STD RESET Z3_DATA<18> 4 5 FB16_9 STD RESET Z3_DATA<23> 4 5 FB16_12 STD RESET Z3_DATA<24> 4 5 FB16_13 STD RESET Z3_DATA<25> 4 5 FB16_14 STD RESET Z3_DATA<26> 4 5 FB16_15 STD RESET Z3_DATA<31> 4 5 FB16_16 STD RESET Z3_DATA<16> 4 5 FB16_17 STD RESET ** 24 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_EXT FB3_10 30 GCK/I/O GCK CP_IRQ FB3_12 31 I/O I RESET FB6_15 143 GSR/I/O I A<5> FB7_15 49 I/O I A<4> FB9_2 50 I/O I A<6> FB9_3 51 I/O I A<3> FB9_5 52 I/O I A<7> FB9_6 53 I/O I A<2> FB9_8 54 I/O I A<1> FB9_12 57 I/O I LAN_INT FB12_3 111 I/O I AUTOBOOT_OFF FB13_11 75 I/O I FCS FB13_15 77 I/O I DS1 FB13_17 78 I/O I C3 FB14_6 102 I/O I C1 FB14_8 103 I/O I CFIN FB14_10 104 I/O I Z3 FB15_2 79 I/O I AS FB15_3 80 I/O I UDS FB15_8 81 I/O I LDS FB15_10 82 I/O I RW FB15_11 83 I/O I DS0 FB16_5 93 I/O I BERR FB16_12 98 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_BASEADR<5> 6 1<- 0 0 FB1_1 (b) (b) LAN_BASEADR<9> 6 1<- 0 0 FB1_2 (b) (b) D_10_IOBUFE/D_10_IOBUFE_TRST 3 0 /\1 1 FB1_3 (b) (b) LAN_BASEADR<7> 6 1<- 0 0 FB1_4 (b) (b) D<5> 7 3<- /\1 0 FB1_5 20 I/O I/O D<4> 7 5<- /\3 0 FB1_6 21 I/O I/O (unused) 0 0 /\5 0 FB1_7 (b) (b) IDE_CS<0> 1 0 0 4 FB1_8 22 I/O O LAN_BASEADR<2> 6 1<- 0 0 FB1_9 (b) (b) IDE_CS<1> 1 0 /\1 3 FB1_10 23 I/O O LAN_BASEADR<1> 6 1<- 0 0 FB1_11 (b) (b) IDE_A<0> 1 0 /\1 3 FB1_12 24 I/O O LAN_BASEADR<15> 6 1<- 0 0 FB1_13 (b) (b) IDE_A<2> 1 0 /\1 3 FB1_14 25 I/O O IDE_A<1> 1 0 \/1 3 FB1_15 26 I/O O LAN_BASEADR<13> 6 1<- 0 0 FB1_16 (b) (b) IDE_R 1 0 \/2 2 FB1_17 27 I/O O LAN_BASEADR<10> 6 2<- \/1 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: AS 15: A<10>.PIN 29: DQ<5>.PIN 2: AUTOCONFIG_Z2_ACCESS 16: A<11>.PIN 30: DQ<4>.PIN 3: AUTO_CONFIG_Z2_DONE<0> 17: IDE_R_S 31: A<13>.PIN 4: AUTO_CONFIG_Z2_DONE<1> 18: LAN_ACCESS 32: D<15>.PIN 5: A<1> 19: LAN_BASEADR<10> 33: D<13>.PIN 6: A<2> 20: LAN_BASEADR<13> 34: D<10>.PIN 7: A<3> 21: LAN_BASEADR<15> 35: D<9>.PIN 8: A<4> 22: LAN_BASEADR<1> 36: RESET 9: A<5> 23: LAN_BASEADR<2> 37: RW 10: A<6> 24: LAN_BASEADR<5> 38: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 11: CP_CS 25: LAN_BASEADR<7> 39: UDS 12: D_10_IOBUFE/D_10_IOBUFE_TRST 26: LAN_BASEADR<9> 40: Z3_DATA<20> 13: FCS 27: LDS 41: Z3_DATA<21> 14: A<9>.PIN 28: A<12>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs LAN_BASEADR<5> XXX.XXXXXX.............X..X.....X..XXXX........... 16 LAN_BASEADR<9> XX.XXXXXXX...............XX.......XXXXX........... 16 D_10_IOBUFE/D_10_IOBUFE_TRST XX........X.X....X..................X............. 6 LAN_BASEADR<7> XXX.XXXXXX..............X.X....X...XXXX........... 16 D<5> XX.........XX....X..........X.......X...X......... 8 D<4> XX.........XX....X...........X......X..X.......... 8 IDE_CS<0> ...........................X...................... 1 LAN_BASEADR<2> XXX.XXXXXX............X...X......X.XXXX........... 16 IDE_CS<1> ..............................X................... 1 LAN_BASEADR<1> XXX.XXXXXX...........X....X.......XXXXX........... 16 IDE_A<0> .............X.................................... 1 LAN_BASEADR<15> XX.XXXXXXX..........X.....X....X...XXXX........... 16 IDE_A<2> ...............X.................................. 1 IDE_A<1> ..............X................................... 1 LAN_BASEADR<13> XX.XXXXXXX.........X......X.....X..XXXX........... 16 IDE_R X...............X................................. 2 LAN_BASEADR<10> XX.XXXXXXX........X.......X......X.XXXX........... 16 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 46/8 Number of signals used by logic mapping into function block: 46 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ<8>_BUFR 9 4<- 0 0 FB2_1 (b) (b) A_LAN<4> 2 1<- /\4 0 FB2_2 9 I/O O A_LAN<7> 1 0 /\1 3 FB2_3 10 I/O O IDE_BASEADR<3> 6 1<- 0 0 FB2_4 (b) (b) A_LAN<6> 2 0 /\1 2 FB2_5 11 I/O O LAN_CFG<1> 0 0 \/1 4 FB2_6 12 I/O O IDE_BASEADR<2> 6 1<- 0 0 FB2_7 (b) (b) LAN_CFG<3> 0 0 \/3 2 FB2_8 13 I/O O IDE_BASEADR<1> 6 3<- \/2 0 FB2_9 (b) (b) D<6> 7 2<- 0 0 FB2_10 14 I/O I/O (unused) 0 0 \/5 0 FB2_11 (b) (b) D<3> 7 5<- \/3 0 FB2_12 15 I/O I/O IDE_BASEADR<0> 6 3<- \/2 0 FB2_13 (b) (b) D<7> 7 2<- 0 0 FB2_14 16 I/O I/O D<1> 7 2<- 0 0 FB2_15 17 I/O I/O DQ_4_IOBUFE/DQ_4_IOBUFE_TRST 6 3<- /\2 0 FB2_16 (b) (b) D<8> 7 5<- /\3 0 FB2_17 19 I/O I/O (unused) 0 0 /\5 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: AS 17: FCS 32: D<10>.PIN 2: AUTOCONFIG_Z2_ACCESS 18: IDE_BASEADR<0> 33: D<9>.PIN 3: AUTO_CONFIG_Z2_DONE<0> 19: IDE_BASEADR<1> 34: D<8>.PIN 4: AUTO_CONFIG_Z2_DONE<1> 20: IDE_BASEADR<2> 35: RESET 5: AUTO_CONFIG_Z2_DONE<2> 21: IDE_BASEADR<3> 36: RW 6: A<1> 22: LAN_ACCESS 37: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 7: A<2> 23: LAN_A_INIT<6> 38: UDS 8: A<3> 24: LAN_D_INIT<8> 39: Z3_ADR<3> 9: A<4> 25: LDS 40: Z3_ADR<5> 10: A<5> 26: DQ<8>.PIN 41: Z3_ADR<6> 11: A<6> 27: DQ<7>.PIN 42: Z3_DATA<17> 12: CP_CS 28: DQ<6>.PIN 43: Z3_DATA<19> 13: DQ_DATA<8> 29: DQ<3>.PIN 44: Z3_DATA<22> 14: DS0 30: DQ<1>.PIN 45: Z3_DATA<23> 15: DS1 31: D<11>.PIN 46: Z3_DATA<24> 16: D_10_IOBUFE/D_10_IOBUFE_TRST Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs DQ<8>_BUFR ............XXX.X....X.XX........XXX.X............ 11 A_LAN<4> ........X..X......................X...X........... 4 A_LAN<7> ..................................X.....X......... 2 IDE_BASEADR<3> XXXXXXXXXXX.........X...X.....X...XXXX............ 18 A_LAN<6> ......................X...........X....X.......... 3 LAN_CFG<1> .................................................. 0 IDE_BASEADR<2> XXXXXXXXXXX........X....X......X..XXXX............ 18 LAN_CFG<3> .................................................. 0 IDE_BASEADR<1> XXXXXXXXXXX.......X.....X.......X.XXXX............ 18 D<6> XX.............XX....X.....X.......X.......X...... 8 D<3> XX.............XX....X......X......X......X....... 8 IDE_BASEADR<0> XXXXXXXXXXX......X......X........XXXXX............ 18 D<7> XX.............XX....X....X........X........X..... 8 D<1> XX.............XX....X.......X.....X.....X........ 8 DQ_4_IOBUFE/DQ_4_IOBUFE_TRST X..........X.XX.X....X..X.........XX.X............ 10 D<8> XX.............XX....X...X.........X.........X.... 8 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_IRQ_OUT 3 0 0 2 FB3_1 (b) (b) IDE_W 1 0 0 4 FB3_2 28 I/O O (unused) 0 0 0 5 FB3_3 (b) LAN_A_INIT<3> 1 0 0 4 FB3_4 (b) (b) SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 2 0 0 3 FB3_5 (b) (b) Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D 2 0 0 3 FB3_6 (b) (b) LAN_RST_SM_FSM_FFd7 2 0 0 3 FB3_7 (b) (b) LAN_IRQ_D0 2 0 0 3 FB3_8 (b) (b) CP_WE_QUIRK 2 0 0 3 FB3_9 (b) (b) $OpTx$FX_DC$84 2 0 0 3 FB3_10 30 GCK/I/O GCK $OpTx$FX_DC$83 2 0 0 3 FB3_11 (b) (b) Z3_ADR<9> 3 0 0 2 FB3_12 31 I/O I Z3_ADR<8> 3 0 0 2 FB3_13 (b) (b) INT2_OUT 1 0 0 4 FB3_14 32 GCK/I/O O ROM_B<0> 0 0 \/3 2 FB3_15 33 I/O O $OpTx$INV$62 4 3<- \/4 0 FB3_16 (b) (b) $OpTx$INV$61 14 9<- 0 0 FB3_17 (b) (b) (unused) 0 0 /\5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: AS 14: LAN_BASEADR<14> 27: D<14>.PIN 2: C1 15: LAN_BASEADR<15> 28: D<13>.PIN 3: C3 16: LAN_BASEADR<5> 29: D<12>.PIN 4: CP_WE_S 17: LAN_BASEADR<6> 30: D<11>.PIN 5: FCS 18: LAN_BASEADR<7> 31: D<10>.PIN 6: A<10>.PIN 19: LAN_BASEADR<8> 32: D<9>.PIN 7: A<11>.PIN 20: LAN_BASEADR<9> 33: D<8>.PIN 8: IDE_W_S 21: LAN_INT_ENABLE 34: A<21>.PIN 9: LAN_A_INIT<3> 22: LAN_INT 35: A<22>.PIN 10: LAN_BASEADR<10> 23: LAN_IRQ_D0 36: RESET 11: LAN_BASEADR<11> 24: LAN_IRQ_OUT 37: SHUT_UP_Z2<0> 12: LAN_BASEADR<12> 25: A<23>.PIN 38: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 13: LAN_BASEADR<13> 26: D<15>.PIN 39: Z3 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_IRQ_OUT .....................XXX...........X.... 4 IDE_W X......X................................ 2 LAN_A_INIT<3> ...................................X.... 1 SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF .XX..................................... 2 Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D .............X............X............. 2 LAN_RST_SM_FSM_FFd7 ........X..........................X.... 2 LAN_IRQ_D0 .....................X.............X.... 2 CP_WE_QUIRK ...X.................................X.. 2 $OpTx$FX_DC$84 .................X......X............... 2 $OpTx$FX_DC$83 ...............X.................X...... 2 Z3_ADR<9> ....X.X............................X.... 3 Z3_ADR<8> ....XX.............................X.... 3 INT2_OUT ....................X..X................ 2 ROM_B<0> ........................................ 0 $OpTx$INV$62 ............X...X..........X......X..... 4 $OpTx$INV$61 .........XXX..X...XX.....X..XXXXX...X.X. 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 47/7 Number of signals used by logic mapping into function block: 47 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use SHUT_UP_Z2<2> 4 0 /\1 0 FB4_1 (b) (b) D<0> 7 2<- 0 0 FB4_2 2 GTS/I/O I/O IDE_BASEADR<7> 6 3<- /\2 0 FB4_3 (b) (b) IDE_BASEADR<6> 6 4<- /\3 0 FB4_4 (b) (b) A_LAN<1> 1 0 /\4 0 FB4_5 3 GTS/I/O O A_LAN<0> 1 0 \/2 2 FB4_6 4 I/O O IDE_BASEADR<5> 6 2<- \/1 0 FB4_7 (b) (b) A_LAN<3> 3 1<- \/3 0 FB4_8 5 GTS/I/O O IDE_BASEADR<4> 6 3<- \/2 0 FB4_9 (b) (b) CP_BASEADR<7> 6 2<- \/1 0 FB4_10 (b) (b) CP_BASEADR<6> 6 1<- 0 0 FB4_11 (b) (b) A_LAN<2> 2 0 \/1 2 FB4_12 6 GTS/I/O O CP_BASEADR<5> 6 1<- 0 0 FB4_13 (b) (b) A_LAN<5> 2 0 \/3 0 FB4_14 7 I/O O CP_BASEADR<4> 6 3<- \/2 0 FB4_15 (b) (b) CP_BASEADR<2> 6 2<- \/1 0 FB4_16 (b) (b) CP_BASEADR<1> 6 1<- 0 0 FB4_17 (b) (b) CP_BASEADR<0> 6 1<- 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: AS 17: CP_BASEADR<6> 33: D<12>.PIN 2: AUTOCONFIG_Z2_ACCESS 18: CP_BASEADR<7> 34: D<10>.PIN 3: AUTO_CONFIG_Z2_DONE<0> 19: CP_CS 35: D<9>.PIN 4: AUTO_CONFIG_Z2_DONE<1> 20: D_10_IOBUFE/D_10_IOBUFE_TRST 36: D<8>.PIN 5: AUTO_CONFIG_Z2_DONE<2> 21: FCS 37: RESET 6: A<1> 22: IDE_BASEADR<4> 38: RW 7: A<2> 23: IDE_BASEADR<5> 39: SHUT_UP_Z2<2> 8: A<3> 24: IDE_BASEADR<6> 40: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 9: A<4> 25: IDE_BASEADR<7> 41: UDS 10: A<5> 26: LAN_ACCESS 42: Z3_ADR<2> 11: A<6> 27: LAN_A_INIT<3> 43: Z3_ADR<4> 12: CP_BASEADR<0> 28: LDS 44: Z3_ADR_0 13: CP_BASEADR<1> 29: DQ<0>.PIN 45: Z3_ADR_1 14: CP_BASEADR<2> 30: D<15>.PIN 46: Z3_A_LOW 15: CP_BASEADR<4> 31: D<14>.PIN 47: Z3_DATA<16> 16: CP_BASEADR<5> 32: D<13>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs SHUT_UP_Z2<2> XXXXXXXXXXX................X........XXXXX......... 17 D<0> XX.................XX....X..X........X........X... 8 IDE_BASEADR<7> XXXXXXXXXXX.............X..X.X......XX.XX......... 18 IDE_BASEADR<6> XXXXXXXXXXX............X...X..X.....XX.XX......... 18 A_LAN<1> ....................................X......X...... 2 A_LAN<0> ....................................X........X.... 2 IDE_BASEADR<5> XXXXXXXXXXX...........X....X...X....XX.XX......... 18 A_LAN<3> .......X..........X.......X.........X....X........ 5 IDE_BASEADR<4> XXXXXXXXXXX..........X.....X....X...XX.XX......... 18 CP_BASEADR<7> XXXX.XXXXXX......X.........X.X......XX.XX......... 17 CP_BASEADR<6> XXXX.XXXXXX.....X..........X..X.....XX.XX......... 17 A_LAN<2> ......X...........X.................X.......X..... 4 CP_BASEADR<5> XXXX.XXXXXX....X...........X...X....XX.XX......... 17 A_LAN<5> .........X........X.................X.....X....... 4 CP_BASEADR<4> XXXX.XXXXXX...X............X....X...XX.XX......... 17 CP_BASEADR<2> XXXX.XXXXXX..X.............X.....X..XX.XX......... 17 CP_BASEADR<1> XXXX.XXXXXX.X..............X......X.XX.XX......... 17 CP_BASEADR<0> XXXX.XXXXXXX...............X.......XXX.XX......... 17 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 50/4 Number of signals used by logic mapping into function block: 50 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use AUTOCONFIG_Z2_ACCESS 5 0 0 0 FB5_1 (b) (b) CP_CS 19 14<- 0 0 FB5_2 34 I/O O (unused) 0 0 /\5 0 FB5_3 (b) (b) (unused) 0 0 /\5 0 FB5_4 (b) (b) ROM_OE 1 0 /\4 0 FB5_5 35 I/O O AUTO_CONFIG_Z2_DONE<2> 4 0 0 1 FB5_6 (b) (b) AUTO_CONFIG_Z2_DONE_CYCLE<2> 4 0 0 1 FB5_7 (b) (b) Z3_ADR<2> 3 0 0 2 FB5_8 38 GCK/I/O (b) Z3_ADR<3> 3 0 \/2 0 FB5_9 (b) (b) D<2> 7 2<- 0 0 FB5_10 39 I/O I/O Z3_ADR<4> 3 0 \/2 0 FB5_11 (b) (b) D<9> 7 2<- 0 0 FB5_12 40 I/O I/O Z3_ADR_1 3 0 \/2 0 FB5_13 (b) (b) D<10> 7 2<- 0 0 FB5_14 41 I/O I/O D<11> 7 2<- 0 0 FB5_15 43 I/O I/O $OpTx$$OpTx$FX_DC$87_INV$1549 1 0 /\2 2 FB5_16 (b) (b) D<12> 9 4<- 0 0 FB5_17 44 I/O I/O (unused) 0 0 /\4 1 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: AS 18: CP_BASEADR<4> 35: DQ<2>.PIN 2: AUTOBOOT_OFF 19: CP_BASEADR<5> 36: A<20>.PIN 3: AUTOCONFIG_Z2_ACCESS 20: CP_BASEADR<6> 37: A<21>.PIN 4: AUTO_CONFIG_Z2_DONE<0> 21: CP_BASEADR<7> 38: A<16>.PIN 5: AUTO_CONFIG_Z2_DONE<1> 22: D_10_IOBUFE/D_10_IOBUFE_TRST 39: A<22>.PIN 6: AUTO_CONFIG_Z2_DONE<2> 23: D_Z2_OUT<0> 40: RESET 7: AUTO_CONFIG_Z2_DONE_CYCLE<2> 24: FCS 41: ROM_OE_S 8: A<1> 25: LAN_ACCESS 42: RW 9: A<3> 26: LDS 43: SHUT_UP_Z2<1> 10: A<4> 27: A<17>.PIN 44: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 11: A<5> 28: A<23>.PIN 45: UDS 12: A<6> 29: A<18>.PIN 46: Z3_DATA<18> 13: CFIN 30: A<19>.PIN 47: Z3_DATA<25> 14: CP_BASEADR<0> 31: DQ<12>.PIN 48: Z3_DATA<26> 15: CP_BASEADR<1> 32: DQ<11>.PIN 49: Z3_DATA<27> 16: CP_BASEADR<2> 33: DQ<10>.PIN 50: Z3_DATA<28> 17: CP_BASEADR<3> 34: DQ<9>.PIN Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs AUTOCONFIG_Z2_ACCESS X..XXX......X.............XXXX.....XXXXX.................... 14 CP_CS X............XXXXXXXX.....XXXX.....XXXXX..X................. 19 ROM_OE XX......................................X................... 3 AUTO_CONFIG_Z2_DONE<2> X....XX................................X...X................ 5 AUTO_CONFIG_Z2_DONE_CYCLE<2> X.XXXXXXXXXX.............X.............X.X.XX............... 16 Z3_ADR<2> .........X.............X...............X.................... 3 Z3_ADR<3> ..........X............X...............X.................... 3 D<2> X.X..................X.XX.........X......X...X.............. 8 Z3_ADR<4> ...........X...........X...............X.................... 3 D<9> X.X..................X.XX........X.......X....X............. 8 Z3_ADR_1 ........X..............X...............X.................... 3 D<10> X.X..................X.XX.......X........X.....X............ 8 D<11> X.X..................X.XX......X.........X......X........... 8 $OpTx$$OpTx$FX_DC$87_INV$1549 .......X.X.................................................. 2 D<12> X.X..................XXXX.....X..........X.......X.......... 9 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_WR_RST 2 0 0 3 FB6_1 (b) (b) LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O A_LAN<12> 1 0 0 4 FB6_3 136 I/O O LAN_RST_SM_FSM_FFd6 2 0 0 3 FB6_4 (b) (b) A_LAN<13> 1 0 0 4 FB6_5 137 I/O O A_LAN<10> 1 0 0 4 FB6_6 138 I/O O LAN_RST_SM_FSM_FFd5 2 0 0 3 FB6_7 (b) (b) A_LAN<11> 1 0 0 4 FB6_8 139 I/O O LAN_RST_SM_FSM_FFd4 2 0 0 3 FB6_9 (b) (b) A_LAN<8> 1 0 0 4 FB6_10 140 I/O O LAN_RST_SM_FSM_FFd3 2 0 0 3 FB6_11 (b) (b) LAN_RST_SM_FSM_FFd2 2 0 0 3 FB6_12 (b) (b) LAN_RST_SM_FSM_FFd1 2 0 0 3 FB6_13 (b) (b) A_LAN<9> 1 0 0 4 FB6_14 142 I/O O LAN_D_INIT<8> 2 0 0 3 FB6_15 143 GSR/I/O I LAN_D_INIT<1> 2 0 0 3 FB6_16 (b) (b) LAN_CS_RST 2 0 0 3 FB6_17 (b) (b) LAN_A_INIT<6> 2 0 0 3 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: LAN_A_INIT<3> 6: LAN_RST_SM_FSM_FFd5 11: Z3_ADR<11> 2: LAN_RST_SM_FSM_FFd1 7: LAN_RST_SM_FSM_FFd6 12: Z3_ADR<12> 3: LAN_RST_SM_FSM_FFd2 8: LAN_RST_SM_FSM_FFd7 13: Z3_ADR<7> 4: LAN_RST_SM_FSM_FFd3 9: RESET 14: Z3_ADR<8> 5: LAN_RST_SM_FSM_FFd4 10: Z3_ADR<10> 15: Z3_ADR<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_WR_RST ...X..X.X............................... 3 LAN_CFG<2> ........................................ 0 A_LAN<12> ........X.X............................. 2 LAN_RST_SM_FSM_FFd6 .......XX............................... 2 A_LAN<13> ........X..X............................ 2 A_LAN<10> ........X.....X......................... 2 LAN_RST_SM_FSM_FFd5 ......X.X............................... 2 A_LAN<11> ........XX.............................. 2 LAN_RST_SM_FSM_FFd4 .....X..X............................... 2 A_LAN<8> ........X...X........................... 2 LAN_RST_SM_FSM_FFd3 ....X...X............................... 2 LAN_RST_SM_FSM_FFd2 ...X....X............................... 2 LAN_RST_SM_FSM_FFd1 .XX.....X............................... 3 A_LAN<9> ........X....X.......................... 2 LAN_D_INIT<8> X....XXXX............................... 5 LAN_D_INIT<1> .XXXX...X............................... 5 LAN_CS_RST XX......X............................... 3 LAN_A_INIT<6> X....XXXX............................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use SHUT_UP_Z2<0> 4 0 /\1 0 FB7_1 (b) (b) CP_RD_S 3 0 \/2 0 FB7_2 (b) (b) D<13> 9 4<- 0 0 FB7_3 45 I/O I/O AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 1<- /\2 0 FB7_4 (b) (b) D<14> 9 5<- /\1 0 FB7_5 46 I/O I/O (unused) 0 0 /\5 0 FB7_6 (b) (b) (unused) 0 0 \/5 0 FB7_7 (b) (b) D_Z2_OUT<0> 15 10<- 0 0 FB7_8 (b) (b) (unused) 0 0 /\5 0 FB7_9 (b) (b) AUTO_CONFIG_Z2_DONE_CYCLE<0> 4 0 \/1 0 FB7_10 (b) (b) (unused) 0 0 \/5 0 FB7_11 (b) (b) D<15> 9 6<- \/2 0 FB7_12 48 I/O I/O (unused) 0 0 \/5 0 FB7_13 (b) (b) D_Z2_OUT<1> 17 12<- 0 0 FB7_14 (b) (b) (unused) 0 0 /\5 0 FB7_15 49 I/O I (unused) 0 0 \/5 0 FB7_16 (b) (b) D_Z2_OUT<2> 16 11<- 0 0 FB7_17 (b) (b) (unused) 0 0 /\5 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$87_INV$1549 12: A<5> 23: DQ<14>.PIN 2: AS 13: A<6> 24: DQ<13>.PIN 3: AUTOCONFIG_Z2_ACCESS 14: CP_CS 25: RESET 4: AUTO_CONFIG_Z2_DONE<0> 15: D_10_IOBUFE/D_10_IOBUFE_TRST 26: RW 5: AUTO_CONFIG_Z2_DONE<1> 16: D_Z2_OUT<1> 27: SHUT_UP_Z2<0> 6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 17: D_Z2_OUT<2> 28: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 18: D_Z2_OUT<3> 29: UDS 8: A<1> 19: FCS 30: Z3_DATA<29> 9: A<2> 20: LAN_ACCESS 31: Z3_DATA<30> 10: A<3> 21: LDS 32: Z3_DATA<31> 11: A<4> 22: DQ<15>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs SHUT_UP_Z2<0> .XXX...XXXXXX.......X...XXXXX........... 15 CP_RD_S .X...........X......X....X.XX........... 6 D<13> .XX...........XX..XX...X.X...X.......... 9 AUTO_CONFIG_Z2_DONE_CYCLE<1> .XXXX.XX.XXXX.......X...XX.XX........... 15 D<14> .XX...........X.X.XX..X..X....X......... 9 D_Z2_OUT<0> .XXXX..XXXXXX.......X...X..XX........... 14 AUTO_CONFIG_Z2_DONE_CYCLE<0> .XXX.X.X.XXXX.......X...XX.XX........... 14 D<15> .XX...........X..XXX.X...X.....X........ 9 D_Z2_OUT<1> XXXXX..XXXXXX.......X...X..XX........... 15 D_Z2_OUT<2> .XXXX..XXXXXX.......X...X..XX........... 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/4 1 FB8_1 (b) (b) DQ<12> 9 4<- 0 0 FB8_2 130 I/O I/O DQ<14> 9 4<- 0 0 FB8_3 131 I/O I/O (unused) 0 0 /\4 1 FB8_4 (b) (b) LAN_WRH 3 0 \/2 0 FB8_5 132 I/O O LAN_BASEADR<8> 6 2<- \/1 0 FB8_6 (b) (b) LAN_BASEADR<6> 6 1<- 0 0 FB8_7 (b) (b) LAN_CS 3 0 \/1 1 FB8_8 133 I/O O LAN_BASEADR<4> 6 1<- 0 0 FB8_9 (b) (b) LAN_RD 1 0 \/3 1 FB8_10 134 I/O O LAN_BASEADR<3> 6 3<- \/2 0 FB8_11 (b) (b) LAN_BASEADR<14> 6 2<- \/1 0 FB8_12 (b) (b) LAN_BASEADR<12> 6 1<- 0 0 FB8_13 (b) (b) LAN_BASEADR<11> 6 1<- 0 0 FB8_14 (b) (b) LAN_BASEADR<0> 6 2<- /\1 0 FB8_15 (b) (b) CP_BASEADR<3> 6 3<- /\2 0 FB8_16 (b) (b) (unused) 0 0 /\3 2 FB8_17 (b) (b) SHUT_UP_Z2<1> 4 0 0 1 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: AS 15: DS0 29: LAN_WRH_S 2: AUTOCONFIG_Z2_ACCESS 16: DS1 30: LAN_WR_RST 3: AUTO_CONFIG_Z2_DONE<0> 17: FCS 31: LDS 4: AUTO_CONFIG_Z2_DONE<1> 18: LAN_ACCESS 32: D<14>.PIN 5: A<1> 19: LAN_BASEADR<0> 33: D<12>.PIN 6: A<2> 20: LAN_BASEADR<11> 34: D<11>.PIN 7: A<3> 21: LAN_BASEADR<12> 35: D<8>.PIN 8: A<4> 22: LAN_BASEADR<14> 36: RESET 9: A<5> 23: LAN_BASEADR<3> 37: RW 10: A<6> 24: LAN_BASEADR<4> 38: SHUT_UP_Z2<1> 11: CP_BASEADR<3> 25: LAN_BASEADR<6> 39: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 12: DQ_4_IOBUFE/DQ_4_IOBUFE_TRST 26: LAN_BASEADR<8> 40: UDS 13: DQ_DATA<12> 27: LAN_CS_RST 41: Z3_ADR<13> 14: DQ_DATA<14> 28: LAN_RD_S Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs DQ<12> ...........XX.XXXX............X.X..XX..X.......... 11 DQ<14> ...........X.XXXXX............XX...XX..X.......... 11 LAN_WRH ................X...........XX.....X.............. 4 LAN_BASEADR<8> XX.XXXXXXX...............X....X...XXX.XX.......... 16 LAN_BASEADR<6> XXX.XXXXXX..............X.....XX...XX.XX.......... 16 LAN_CS .................X........X........X....X......... 4 LAN_BASEADR<4> XXX.XXXXXX.............X......X.X..XX.XX.......... 16 LAN_RD ................X..........X.......X.............. 3 LAN_BASEADR<3> XXX.XXXXXX............X.......X..X.XX.XX.......... 16 LAN_BASEADR<14> XX.XXXXXXX...........X........XX...XX.XX.......... 16 LAN_BASEADR<12> XX.XXXXXXX..........X.........X.X..XX.XX.......... 16 LAN_BASEADR<11> XX.XXXXXXX.........X..........X..X.XX.XX.......... 16 LAN_BASEADR<0> XXX.XXXXXX........X...........X...XXX.XX.......... 16 CP_BASEADR<3> XXXXXXXXXXX...................X..X.XX.XX.......... 17 SHUT_UP_Z2<1> XXXXXXXXXX....................X....XXXXX.......... 16 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB9 *********************************** Number of function block inputs used/remaining: 49/5 Number of signals used by logic mapping into function block: 49 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB9_1 (b) (b) LAN_ACCESS 17 12<- 0 0 FB9_2 50 I/O I LAN_SM_FSM_FFd1 2 1<- /\4 0 FB9_3 51 I/O I Z3_ADR<11> 3 0 /\1 1 FB9_4 (b) (b) $OpTx$FX_DC$81 2 0 \/3 0 FB9_5 52 I/O I $OpTx$INV$63 15 10<- 0 0 FB9_6 53 I/O I (unused) 0 0 /\5 0 FB9_7 (b) (b) Z3_ADR<12> 3 0 /\2 0 FB9_8 54 I/O I LAN_SM_FSM_FFd13 1 0 0 4 FB9_9 (b) (b) IDE_ENABLE 3 0 \/2 0 FB9_10 (b) (b) A<8> 5 2<- \/2 0 FB9_11 56 I/O I/O DQ_SWAP 10 5<- 0 0 FB9_12 57 I/O I LAN_SM_FSM_FFd2 2 0 /\3 0 FB9_13 (b) (b) A<9> 5 0 0 0 FB9_14 58 I/O I/O IDE_W_S 3 0 0 2 FB9_15 (b) (b) $OpTx$FX_DC$82 2 0 0 3 FB9_16 (b) (b) A<10> 5 0 0 0 FB9_17 59 I/O I/O LAN_SM_FSM_FFd4 2 0 \/3 0 FB9_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$81 18: LAN_ACCESS 34: A<19>.PIN 2: $OpTx$FX_DC$82 19: LAN_BASEADR<0> 35: DQ<10>.PIN 3: $OpTx$FX_DC$83 20: LAN_BASEADR<1> 36: DQ<9>.PIN 4: $OpTx$FX_DC$84 21: LAN_BASEADR<2> 37: DQ<8>.PIN 5: $OpTx$INV$61 22: LAN_BASEADR<3> 38: DQ<2>.PIN 6: $OpTx$INV$62 23: LAN_BASEADR<4> 39: A<13>.PIN 7: AS 24: LAN_SM_FSM_FFd1 40: DQ<1>.PIN 8: DQ_SWAP 25: LAN_SM_FSM_FFd2 41: DQ<0>.PIN 9: FCS 26: LAN_SM_FSM_FFd5 42: A<14>.PIN 10: IDE_ACCESS 27: LAN_SM_FSM_FFd8 43: A<20>.PIN 11: IDE_BASEADR<0> 28: LAN_SM_FSM_FFd9 44: A<21>.PIN 12: IDE_BASEADR<1> 29: LAN_SM_RST 45: A<16>.PIN 13: IDE_BASEADR<2> 30: Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D 46: RESET 14: IDE_BASEADR<3> 31: A<17>.PIN 47: RW 15: IDE_BASEADR<4> 32: A<23>.PIN 48: SHUT_UP_Z2<2> 16: IDE_BASEADR<5> 33: A<18>.PIN 49: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 17: IDE_BASEADR<7> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs LAN_ACCESS ..XXXX..X.........XXXXX......XX.XX........X.XX.... 17 LAN_SM_FSM_FFd1 .......................XX...X..................... 3 Z3_ADR<11> ........X.............................X......X.... 3 $OpTx$FX_DC$81 .....................X...........X................ 2 $OpTx$INV$63 ..........XXXXXXX.............XXXX........XXX..X.. 15 Z3_ADR<12> ........X................................X...X.... 3 LAN_SM_FSM_FFd13 ............................X..................... 1 IDE_ENABLE ......X..X...................................XX.X. 5 A<8> .......XX........X.......X..X.......X...X.....X... 8 DQ_SWAP XXXXXX..X.........XXX........XX.X.....X..X..XX.... 17 LAN_SM_FSM_FFd2 ..........................X.X..................... 2 A<9> .......XX........X.......X..X......X...X......X... 8 IDE_W_S ......X..X...................................XX.X. 5 $OpTx$FX_DC$82 ......................X...................X....... 2 A<10> .......XX........X.......X..X.....X..X........X... 8 LAN_SM_FSM_FFd4 ...........................XX..................... 2 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB10 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ<4>_BUFR 9 8<- \/4 0 FB10_1 (b) (b) DQ<1> 10 5<- 0 0 FB10_2 117 I/O I/O DQ<0> 9 5<- /\1 0 FB10_3 118 I/O I/O (unused) 0 0 /\5 0 FB10_4 (b) (b) DQ<3> 9 4<- 0 0 FB10_5 119 I/O I/O DQ<2> 9 8<- /\4 0 FB10_6 120 I/O I/O (unused) 0 0 /\5 0 FB10_7 (b) (b) DQ<5> 9 7<- /\3 0 FB10_8 121 I/O I/O (unused) 0 0 /\5 0 FB10_9 (b) (b) DQ<4> 2 0 /\2 1 FB10_10 124 I/O I/O DQ<7> 9 4<- 0 0 FB10_11 125 I/O I/O DQ<6> 9 8<- /\4 0 FB10_12 126 I/O I/O (unused) 0 0 /\5 0 FB10_13 (b) (b) DQ<8> 2 0 /\3 0 FB10_14 128 I/O I/O (unused) 0 0 \/3 2 FB10_15 (b) (b) (unused) 0 0 \/5 0 FB10_16 (b) (b) DQ<10> 10 8<- \/3 0 FB10_17 129 I/O I/O (unused) 0 0 \/5 0 FB10_18 (b) (b) Signals Used by Logic in Function Block 1: DQ<4>_BUFR 12: DQ_DATA<7> 22: D<6>.PIN 2: DQ<8>_BUFR 13: DS0 23: D<5>.PIN 3: DQ_4_IOBUFE/DQ_4_IOBUFE_TRST 14: DS1 24: D<4>.PIN 4: DQ_DATA<0> 15: FCS 25: D<3>.PIN 5: DQ_DATA<10> 16: LAN_ACCESS 26: D<2>.PIN 6: DQ_DATA<1> 17: LAN_D_INIT<1> 27: D<1>.PIN 7: DQ_DATA<2> 18: LAN_D_INIT<8> 28: D<0>.PIN 8: DQ_DATA<3> 19: LDS 29: RESET 9: DQ_DATA<4> 20: D<10>.PIN 30: RW 10: DQ_DATA<5> 21: D<7>.PIN 31: UDS 11: DQ_DATA<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ<4>_BUFR ........X...XXXXX.X....X....XXX......... 11 DQ<1> ..X..X......XXXXX.X.......X.XXX......... 12 DQ<0> ..XX........XXXX..X........XXXX......... 11 DQ<3> ..X....X....XXXX..X.....X...XXX......... 11 DQ<2> ..X...X.....XXXX..X......X..XXX......... 11 DQ<5> ..X......X..XXXX..X...X.....XXX......... 11 DQ<4> X.X..................................... 2 DQ<7> ..X........XXXXX..X.X.......XXX......... 11 DQ<6> ..X.......X.XXXX..X..X......XXX......... 11 DQ<8> .XX..................................... 2 DQ<10> ..X.X.......XXXX.XXX........XXX......... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 34/20 Number of signals used by logic mapping into function block: 34 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$1248 1 0 0 4 FB11_1 (b) (b) Z3_DATA<30> 4 0 0 1 FB11_2 (b) (b) A<11> 5 0 0 0 FB11_3 60 I/O I/O Z3_DATA<29> 4 0 0 1 FB11_4 (b) (b) A<12> 5 0 0 0 FB11_5 61 I/O I/O Z3_DATA<28> 4 0 0 1 FB11_6 (b) (b) Z3_DATA<27> 4 0 0 1 FB11_7 (b) (b) Z3_DATA<22> 4 0 0 1 FB11_8 (b) (b) Z3_DATA<21> 4 0 0 1 FB11_9 (b) (b) A<13> 5 0 0 0 FB11_10 64 I/O I/O A<14> 5 0 0 0 FB11_11 66 I/O I/O INT6_OUT 1 0 0 4 FB11_12 68 I/O O Z3_DATA<20> 4 0 0 1 FB11_13 (b) (b) ROM_B<1> 0 0 0 5 FB11_14 69 I/O O Z3_DATA<19> 4 0 0 1 FB11_15 (b) (b) LAN_READY 4 0 0 1 FB11_16 (b) (b) CP_WE 1 0 \/2 2 FB11_17 70 I/O O Z3_A_LOW 7 2<- 0 0 FB11_18 (b) (b) Signals Used by Logic in Function Block 1: AS 13: LAN_SM_FSM_FFd12 24: LDS 2: CP_IRQ 14: LAN_SM_FSM_FFd13 25: DQ<14>.PIN 3: CP_WE_QUIRK 15: LAN_SM_FSM_FFd2 26: DQ<13>.PIN 4: CP_WE_S 16: LAN_SM_FSM_FFd3 27: DQ<12>.PIN 5: DQ_SWAP 17: LAN_SM_FSM_FFd4 28: DQ<11>.PIN 6: DS0 18: LAN_SM_FSM_FFd5 29: DQ<6>.PIN 7: DS1 19: LAN_SM_FSM_FFd6 30: DQ<5>.PIN 8: FCS 20: LAN_SM_FSM_FFd7 31: DQ<4>.PIN 9: LAN_ACCESS 21: LAN_SM_FSM_FFd8 32: DQ<3>.PIN 10: LAN_SM_FSM_FFd1 22: LAN_SM_FSM_FFd9 33: RW 11: LAN_SM_FSM_FFd10 23: LAN_SM_RST 34: UDS 12: LAN_SM_FSM_FFd11 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$1248 .........XXXX.X.XXXXXX.................. 11 Z3_DATA<30> ....X..............X..X.X...X........... 5 A<11> ....X..XX........X....X....X...XX....... 8 Z3_DATA<29> ....X..............X..X..X...X.......... 5 A<12> ....X..XX........X....X...X...X.X....... 8 Z3_DATA<28> ....X..............X..X...X...X......... 5 Z3_DATA<27> ....X..............X..X....X...X........ 5 Z3_DATA<22> ....X..............X..X.X...X........... 5 Z3_DATA<21> ....X..............X..X..X...X.......... 5 A<13> ....X..XX........X....X..X...X..X....... 8 A<14> ....X..XX........X....X.X...X...X....... 8 INT6_OUT .X...................................... 1 Z3_DATA<20> ....X..............X..X...X...X......... 5 ROM_B<1> ........................................ 0 Z3_DATA<19> ....X..............X..X....X...X........ 5 LAN_READY .....XX..XX.X.XX.X.X..X................. 10 CP_WE X.XX.................................... 3 Z3_A_LOW .....XX...X..XXX..XXX.XX.........X...... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** Number of function block inputs used/remaining: 35/19 Number of signals used by logic mapping into function block: 35 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<11> 10 5<- 0 0 FB12_1 (b) (b) LAN_CFG<4> 0 0 /\4 1 FB12_2 110 I/O O LAN_SM_FSM_FFd8 4 0 \/1 0 FB12_3 111 I/O I LAN_SM_FSM_FFd10 3 1<- \/3 0 FB12_4 (b) (b) DQ<15> 9 4<- 0 0 FB12_5 112 I/O I/O LAN_SM_RST 4 0 /\1 0 FB12_6 (b) (b) (unused) 0 0 \/5 0 FB12_7 (b) (b) DQ<13> 9 5<- \/1 0 FB12_8 113 I/O I/O (unused) 0 0 \/5 0 FB12_9 (b) (b) DQ<11> 10 6<- \/1 0 FB12_10 115 I/O I/O (unused) 0 0 \/5 0 FB12_11 (b) (b) DQ<9> 10 6<- \/1 0 FB12_12 116 I/O I/O (unused) 0 0 \/5 0 FB12_13 (b) (b) DQ_DATA<5> 10 6<- \/1 0 FB12_14 (b) (b) (unused) 0 0 \/5 0 FB12_15 (b) (b) DQ_DATA<3> 10 6<- \/1 0 FB12_16 (b) (b) (unused) 0 0 \/5 0 FB12_17 (b) (b) DQ_DATA<13> 10 6<- \/1 0 FB12_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1248 13: FCS 25: D<15>.PIN 2: BERR 14: A<11>.PIN 26: D<13>.PIN 3: DQ_4_IOBUFE/DQ_4_IOBUFE_TRST 15: LAN_ACCESS 27: D<11>.PIN 4: DQ_DATA<11> 16: LAN_D_INIT<1> 28: D<9>.PIN 5: DQ_DATA<13> 17: LAN_D_INIT<8> 29: D<5>.PIN 6: DQ_DATA<15> 18: LAN_SM_FSM_FFd13 30: D<3>.PIN 7: DQ_DATA<3> 19: LAN_SM_FSM_FFd3 31: A<21>.PIN 8: DQ_DATA<5> 20: LAN_SM_FSM_FFd6 32: RESET 9: DQ_DATA<9> 21: LAN_SM_RST 33: RW 10: DQ_SWAP 22: LDS 34: UDS 11: DS0 23: A<19>.PIN 35: Z3_ADR<13> 12: DS1 24: A<13>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<11> X..X.....X...X...XX.XXX...X..X...X...... 12 LAN_CFG<4> ........................................ 0 LAN_SM_FSM_FFd8 ..........XX.....XX.XX..........XXX..... 9 LAN_SM_FSM_FFd10 .................X.XXX..........XXX..... 7 DQ<15> ..X..X....XXX.X......X..X......XXX...... 11 LAN_SM_RST .X........XXX.X......X.........X.X...... 8 DQ<13> ..X.X.....XXX.X......X...X.....XXX...... 11 DQ<11> ..XX......XXX.X.X....X....X....XXX...... 12 DQ<9> ..X.....X.XXX.XX.....X.....X...XXX...... 12 DQ_DATA<5> X......X.X.......XX.XX.X.X..X.X..X...... 12 DQ_DATA<3> X.....X..X...X...XX.XXX...X..X...X...... 12 DQ_DATA<13> X...X....X.......XX.XX.X.X..X.X..X...... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB13 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<10> 10 5<- 0 0 FB13_1 (b) (b) CP_RD 1 1<- /\5 0 FB13_2 71 I/O O (unused) 0 0 /\1 4 FB13_3 (b) (b) (unused) 0 0 \/5 0 FB13_4 (b) (b) DQ_DATA<6> 10 5<- 0 0 FB13_5 (b) (b) (unused) 0 0 \/5 0 FB13_6 (b) (b) DQ_DATA<4> 10 5<- 0 0 FB13_7 (b) (b) A<15> 5 0 0 0 FB13_8 74 I/O I/O (unused) 0 0 \/5 0 FB13_9 (b) (b) DQ_DATA<2> 10 5<- 0 0 FB13_10 (b) (b) (unused) 0 0 0 5 FB13_11 75 I/O I (unused) 0 0 \/4 1 FB13_12 (b) (b) DQ_DATA<15> 10 5<- 0 0 FB13_13 (b) (b) LAN_WRL 3 0 /\1 1 FB13_14 76 I/O O (unused) 0 0 \/5 0 FB13_15 77 I/O I DQ_DATA<14> 10 5<- 0 0 FB13_16 (b) (b) (unused) 0 0 \/5 0 FB13_17 78 I/O I DQ_DATA<12> 10 5<- 0 0 FB13_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1248 15: LAN_SM_FSM_FFd13 29: D<12>.PIN 2: AS 16: LAN_SM_FSM_FFd3 30: D<10>.PIN 3: CP_RD_S 17: LAN_SM_FSM_FFd5 31: A<14>.PIN 4: DQ_DATA<10> 18: LAN_SM_RST 32: D<7>.PIN 5: DQ_DATA<12> 19: LAN_WRL_S 33: D<6>.PIN 6: DQ_DATA<14> 20: LAN_WR_RST 34: D<4>.PIN 7: DQ_DATA<15> 21: LDS 35: D<2>.PIN 8: DQ_DATA<2> 22: A<23>.PIN 36: A<20>.PIN 9: DQ_DATA<4> 23: A<18>.PIN 37: A<15>.PIN 10: DQ_DATA<6> 24: DQ<15>.PIN 38: A<22>.PIN 11: DQ_SWAP 25: A<12>.PIN 39: RESET 12: FCS 26: DQ<7>.PIN 40: RW 13: A<10>.PIN 27: D<15>.PIN 41: UDS 14: LAN_ACCESS 28: D<14>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<10> X..X......X.X.XX.X..X.X......X....X.....X......... 12 CP_RD .XX............................................... 2 DQ_DATA<6> X........XX...XX.X..X......X..X.X....X..X......... 12 DQ_DATA<4> X.......X.X...XX.X..X...X...X....X.X....X......... 12 A<15> ..........XX.X..XX.....X.X.............X.......... 8 DQ_DATA<2> X......X..X.X.XX.X..X.X......X....X.....X......... 12 DQ_DATA<15> X.....X...X...XX.X..XX....X....X....X...X......... 12 LAN_WRL ...........X......XX..................X........... 4 DQ_DATA<14> X....X....X...XX.X..X......X..X.X....X..X......... 12 DQ_DATA<12> X...X.....X...XX.X..X...X...X....X.X....X......... 12 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB14 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB14_1 (b) (b) D_Z2_OUT<3> 14 9<- 0 0 FB14_2 (b) (b) OVR 1 0 /\4 0 FB14_3 100 I/O O AUTO_CONFIG_Z2_DONE<1> 4 0 0 1 FB14_4 (b) (b) IDE_ACCESS 4 0 0 1 FB14_5 101 I/O (b) CP_WE_S 3 0 0 2 FB14_6 102 I/O I IDE_R_S 3 0 0 2 FB14_7 (b) (b) ROM_OE_S 3 0 0 2 FB14_8 103 I/O I Z3_ADR<10> 3 0 0 2 FB14_9 (b) (b) Z3_ADR<13> 3 0 0 2 FB14_10 104 I/O I CFOUT 1 0 0 4 FB14_11 105 I/O O Z3_ADR<5> 3 0 0 2 FB14_12 (b) (b) Z3_ADR<6> 3 0 0 2 FB14_13 (b) (b) SLAVE 4 0 0 1 FB14_14 106 I/O O OWN 0 0 0 5 FB14_15 107 I/O O Z3_ADR<7> 3 0 0 2 FB14_16 (b) (b) Z3_ADR_0 3 0 0 2 FB14_17 (b) (b) AUTO_CONFIG_Z2_DONE<0> 4 0 0 1 FB14_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$INV$63 12: A<4> 22: LAN_ACCESS 2: AS 13: A<5> 23: LDS 3: AUTOCONFIG_Z2_ACCESS 14: A<6> 24: A<8>.PIN 4: AUTO_CONFIG_Z2_DONE<0> 15: A<7> 25: A<12>.PIN 5: AUTO_CONFIG_Z2_DONE<1> 16: CP_CS 26: A<15>.PIN 6: AUTO_CONFIG_Z2_DONE<2> 17: FCS 27: A<22>.PIN 7: AUTO_CONFIG_Z2_DONE_CYCLE<0> 18: IDE_ACCESS 28: RESET 8: AUTO_CONFIG_Z2_DONE_CYCLE<1> 19: A<9>.PIN 29: RW 9: A<1> 20: IDE_BASEADR<6> 30: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 10: A<2> 21: IDE_ENABLE 31: UDS 11: A<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D_Z2_OUT<3> .XXXX...XXXXXX........X....X.XX......... 14 OVR ................X....X.................. 2 AUTO_CONFIG_Z2_DONE<1> .X..X..X...................X.X.......... 5 IDE_ACCESS XX.................X......XX............ 5 CP_WE_S .X.............X......X.....XXX......... 6 IDE_R_S .X...............X..X......XXX.......... 6 ROM_OE_S .X...............X..X......XXX.......... 6 Z3_ADR<10> ................X.......X..X............ 3 Z3_ADR<13> ................X........X.X............ 3 CFOUT ...XXX.................................. 3 Z3_ADR<5> ..............X.X..........X............ 3 Z3_ADR<6> ................X......X...X............ 3 SLAVE .XX............XXX...X.................. 6 OWN ........................................ 0 Z3_ADR<7> ................X.X........X............ 3 Z3_ADR_0 .........X......X..........X............ 3 AUTO_CONFIG_Z2_DONE<0> .X.X..X....................X.X.......... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB15 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<1> 10 5<- 0 0 FB15_1 (b) (b) LAN_SM_FSM_FFd12 2 0 /\2 1 FB15_2 79 I/O I LAN_WRL_S 3 0 0 2 FB15_3 80 I/O I LAN_WRH_S 3 0 0 2 FB15_4 (b) (b) LAN_SM_FSM_FFd7 3 0 0 2 FB15_5 (b) (b) LAN_SM_FSM_FFd3 3 0 0 2 FB15_6 (b) (b) LAN_SM_FSM_FFd9 3 0 0 2 FB15_7 (b) (b) LAN_SM_FSM_FFd11 3 0 \/2 0 FB15_8 81 I/O I LAN_RD_S 4 2<- \/3 0 FB15_9 (b) (b) DQ_DATA<9> 10 5<- 0 0 FB15_10 82 I/O I LAN_SM_FSM_FFd6 3 0 /\2 0 FB15_11 83 I/O I DTACK 1 0 \/4 0 FB15_12 85 I/O O DQ_DATA<7> 10 5<- 0 0 FB15_13 (b) (b) A<23> 5 1<- /\1 0 FB15_14 86 I/O I/O A<22> 5 1<- /\1 0 FB15_15 87 I/O I/O LAN_INT_ENABLE 4 0 /\1 0 FB15_16 (b) (b) A<21> 5 0 0 0 FB15_17 88 I/O I/O LAN_SM_FSM_FFd5 2 0 \/3 0 FB15_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1248 15: LAN_SM_FSM_FFd12 29: DQ<14>.PIN 2: DQ_DATA<1> 16: LAN_SM_FSM_FFd13 30: DQ<13>.PIN 3: DQ_DATA<7> 17: LAN_SM_FSM_FFd3 31: DQ<7>.PIN 4: DQ_DATA<9> 18: LAN_SM_FSM_FFd4 32: DQ<6>.PIN 5: DQ_SWAP 19: LAN_SM_FSM_FFd5 33: DQ<5>.PIN 6: DS0 20: LAN_SM_FSM_FFd6 34: D<15>.PIN 7: DS1 21: LAN_SM_FSM_FFd7 35: D<9>.PIN 8: FCS 22: LAN_SM_FSM_FFd8 36: D<7>.PIN 9: A<9>.PIN 23: LAN_SM_FSM_FFd9 37: D<1>.PIN 10: LAN_ACCESS 24: LAN_SM_RST 38: A<15>.PIN 11: LAN_INT_ENABLE 25: LDS 39: RW 12: LAN_READY 26: A<17>.PIN 40: UDS 13: LAN_SM_FSM_FFd10 27: A<23>.PIN 41: Z3_ADR<13> 14: LAN_SM_FSM_FFd11 28: DQ<15>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<1> XX..X...X......XX......XXX........X.X..X.......... 12 LAN_SM_FSM_FFd12 ..............XX.......X................X......... 4 LAN_WRL_S ......X..............XXX...............X.......... 5 LAN_WRH_S .....X...............XXXX......................... 5 LAN_SM_FSM_FFd7 .....XX......X......X..X.......................... 5 LAN_SM_FSM_FFd3 .....XX.........XX.....X.......................... 5 LAN_SM_FSM_FFd9 ...............X.......XX.............XXX......... 6 LAN_SM_FSM_FFd11 ...............X.......XX.............XXX......... 6 LAN_RD_S ............XX.X...X...X..............X.X......... 7 DQ_DATA<9> X..XX...X......XX......XXX........X.X..X.......... 12 LAN_SM_FSM_FFd6 .....XX.............X..X.......................... 4 DTACK .......X...X...................................... 2 DQ_DATA<7> X.X.X..........XX......XX.X......X.X.X.X.......... 12 A<23> ....X..X.X........X....X...X..X.......X........... 8 A<22> ....X..X.X........X....X....X..X......X........... 8 LAN_INT_ENABLE ......X...X...X........X..X......X....XX.......... 8 A<21> ....X..X.X........X....X.....X..X.....X........... 8 LAN_SM_FSM_FFd5 ............X.....X....X.......................... 3 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB16 *********************************** Number of function block inputs used/remaining: 30/24 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<0> 10 5<- 0 0 FB16_1 (b) (b) A<20> 5 0 0 0 FB16_2 91 I/O I/O A<19> 5 0 0 0 FB16_3 92 I/O I/O (unused) 0 0 \/5 0 FB16_4 (b) (b) DQ_DATA<8> 10 5<- 0 0 FB16_5 93 I/O I A<18> 5 0 0 0 FB16_6 94 I/O I/O Z3_DATA<17> 4 0 0 1 FB16_7 (b) (b) A<17> 5 0 0 0 FB16_8 95 I/O I/O Z3_DATA<18> 4 0 0 1 FB16_9 (b) (b) MTACK 0 0 0 5 FB16_10 96 I/O O A<16> 5 0 0 0 FB16_11 97 I/O I/O Z3_DATA<23> 4 0 0 1 FB16_12 98 I/O I Z3_DATA<24> 4 0 0 1 FB16_13 (b) (b) Z3_DATA<25> 4 0 0 1 FB16_14 (b) (b) Z3_DATA<26> 4 0 0 1 FB16_15 (b) (b) Z3_DATA<31> 4 0 0 1 FB16_16 (b) (b) Z3_DATA<16> 4 0 0 1 FB16_17 (b) (b) (unused) 0 0 \/5 0 FB16_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1248 11: LAN_SM_RST 21: DQ<4>.PIN 2: DQ_DATA<0> 12: LDS 22: DQ<3>.PIN 3: DQ_DATA<8> 13: A<8>.PIN 23: DQ<2>.PIN 4: DQ_SWAP 14: DQ<15>.PIN 24: DQ<1>.PIN 5: FCS 15: DQ<12>.PIN 25: DQ<0>.PIN 6: LAN_ACCESS 16: DQ<11>.PIN 26: D<8>.PIN 7: LAN_SM_FSM_FFd13 17: DQ<10>.PIN 27: D<0>.PIN 8: LAN_SM_FSM_FFd3 18: DQ<9>.PIN 28: A<16>.PIN 9: LAN_SM_FSM_FFd5 19: DQ<8>.PIN 29: RW 10: LAN_SM_FSM_FFd7 20: DQ<7>.PIN 30: UDS Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<0> XX.X..XX..XXX............XXX.X.......... 12 A<20> ...XXX..X.X...X.....X.......X........... 8 A<19> ...XXX..X.X....X.....X......X........... 8 DQ_DATA<8> X.XX..XX..XXX............XXX.X.......... 12 A<18> ...XXX..X.X.....X.....X.....X........... 8 Z3_DATA<17> ...X.....XX......X.....X................ 5 A<17> ...XXX..X.X......X.....X....X........... 8 Z3_DATA<18> ...X.....XX.....X.....X................. 5 MTACK ........................................ 0 A<16> ...XXX..X.X.......X.....X...X........... 8 Z3_DATA<23> ...X.....XX..X.....X.................... 5 Z3_DATA<24> ...X.....XX.......X.....X............... 5 Z3_DATA<25> ...X.....XX......X.....X................ 5 Z3_DATA<26> ...X.....XX.....X.....X................. 5 Z3_DATA<31> ...X.....XX..X.....X.................... 5 Z3_DATA<16> ...X.....XX.......X.....X............... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$$OpTx$FX_DC$87_INV$1549 <= (NOT A(4) AND NOT A(1)); $OpTx$FX_DC$1248 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd9 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd11 AND NOT LAN_SM_FSM_FFd4); $OpTx$FX_DC$81 <= A(19).PIN XOR $OpTx$FX_DC$81 <= LAN_BASEADR(3); $OpTx$FX_DC$82 <= A(20).PIN XOR $OpTx$FX_DC$82 <= LAN_BASEADR(4); $OpTx$FX_DC$83 <= A(21).PIN XOR $OpTx$FX_DC$83 <= LAN_BASEADR(5); $OpTx$FX_DC$84 <= A(23).PIN XOR $OpTx$FX_DC$84 <= LAN_BASEADR(7); $OpTx$INV$61 <= ((NOT Z3) OR (SHUT_UP_Z2(0)) OR (NOT D(9).PIN AND LAN_BASEADR(9)) OR (D(10).PIN AND NOT LAN_BASEADR(10)) OR (NOT D(10).PIN AND LAN_BASEADR(10)) OR (D(11).PIN AND NOT LAN_BASEADR(11)) OR (NOT D(11).PIN AND LAN_BASEADR(11)) OR (D(12).PIN AND NOT LAN_BASEADR(12)) OR (NOT D(12).PIN AND LAN_BASEADR(12)) OR (D(15).PIN AND NOT LAN_BASEADR(15)) OR (NOT D(15).PIN AND LAN_BASEADR(15)) OR (D(8).PIN AND NOT LAN_BASEADR(8)) OR (NOT D(8).PIN AND LAN_BASEADR(8)) OR (D(9).PIN AND NOT LAN_BASEADR(9))); $OpTx$INV$62 <= ((D(13).PIN AND NOT LAN_BASEADR(13)) OR (NOT D(13).PIN AND LAN_BASEADR(13)) OR (LAN_BASEADR(6) AND NOT A(22).PIN) OR (NOT LAN_BASEADR(6) AND A(22).PIN)); $OpTx$INV$63 <= ((SHUT_UP_Z2(2)) OR (IDE_BASEADR(2) AND NOT A(18).PIN) OR (NOT IDE_BASEADR(2) AND A(18).PIN) OR (NOT IDE_BASEADR(3) AND A(19).PIN) OR (Z3_ADR(12).EXP) OR (IDE_BASEADR(3) AND NOT A(19).PIN) OR (IDE_BASEADR(4) AND NOT A(20).PIN) OR (NOT IDE_BASEADR(4) AND A(20).PIN) OR (IDE_BASEADR(5) AND NOT A(21).PIN) OR (NOT IDE_BASEADR(5) AND A(21).PIN) OR (IDE_BASEADR(0) AND NOT A(16).PIN) OR (NOT IDE_BASEADR(0) AND A(16).PIN) OR (IDE_BASEADR(1) AND NOT A(17).PIN) OR (NOT IDE_BASEADR(1) AND A(17).PIN)); FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(8) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); A(8) <= A_I(8) when A_OE(8) = '1' else 'Z'; A_OE(8) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(9) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); A(9) <= A_I(9) when A_OE(9) = '1' else 'Z'; A_OE(9) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(10) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); A(10) <= A_I(10) when A_OE(10) = '1' else 'Z'; A_OE(10) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(11) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); A(11) <= A_I(11) when A_OE(11) = '1' else 'Z'; A_OE(11) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(12) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); A(12) <= A_I(12) when A_OE(12) = '1' else 'Z'; A_OE(12) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(13) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); A(13) <= A_I(13) when A_OE(13) = '1' else 'Z'; A_OE(13) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(14) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); A(14) <= A_I(14) when A_OE(14) = '1' else 'Z'; A_OE(14) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(15) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); A(15) <= A_I(15) when A_OE(15) = '1' else 'Z'; A_OE(15) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(16) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); A(16) <= A_I(16) when A_OE(16) = '1' else 'Z'; A_OE(16) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(17) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); A(17) <= A_I(17) when A_OE(17) = '1' else 'Z'; A_OE(17) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(18) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); A(18) <= A_I(18) when A_OE(18) = '1' else 'Z'; A_OE(18) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(19) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); A(19) <= A_I(19) when A_OE(19) = '1' else 'Z'; A_OE(19) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(20) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); A(20) <= A_I(20) when A_OE(20) = '1' else 'Z'; A_OE(20) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(21) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); A(21) <= A_I(21) when A_OE(21) = '1' else 'Z'; A_OE(21) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(22) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); A(22) <= A_I(22) when A_OE(22) = '1' else 'Z'; A_OE(22) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd5); A(23) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); A(23) <= A_I(23) when A_OE(23) = '1' else 'Z'; A_OE(23) <= (RW AND NOT FCS AND LAN_ACCESS); FDCPE_AUTOCONFIG_Z2_ACCESS: FDCPE port map (AUTOCONFIG_Z2_ACCESS,AUTOCONFIG_Z2_ACCESS_D,NOT AS,NOT RESET,'0'); AUTOCONFIG_Z2_ACCESS_D <= ((NOT AUTO_CONFIG_Z2_DONE(0) AND A(23).PIN AND A(22).PIN AND A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT A(20).PIN AND NOT A(18).PIN) OR (NOT AUTO_CONFIG_Z2_DONE(1) AND A(23).PIN AND A(22).PIN AND A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT A(20).PIN AND NOT A(18).PIN) OR (NOT AUTO_CONFIG_Z2_DONE(2) AND A(23).PIN AND A(22).PIN AND A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT A(20).PIN AND NOT A(18).PIN)); FDCPE_AUTO_CONFIG_Z2_DONE0: FDCPE port map (AUTO_CONFIG_Z2_DONE(0),AUTO_CONFIG_Z2_DONE_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS); AUTO_CONFIG_Z2_DONE_D(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0)); FDCPE_AUTO_CONFIG_Z2_DONE1: FDCPE port map (AUTO_CONFIG_Z2_DONE(1),AUTO_CONFIG_Z2_DONE_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS); AUTO_CONFIG_Z2_DONE_D(1) <= (NOT AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1)); FDCPE_AUTO_CONFIG_Z2_DONE2: FDCPE port map (AUTO_CONFIG_Z2_DONE(2),AUTO_CONFIG_Z2_DONE_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS); AUTO_CONFIG_Z2_DONE_D(2) <= (NOT AUTO_CONFIG_Z2_DONE(2) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(2)); FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(0),AUTO_CONFIG_Z2_DONE_CYCLE_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0'); AUTO_CONFIG_Z2_DONE_CYCLE_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(1),AUTO_CONFIG_Z2_DONE_CYCLE_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0'); AUTO_CONFIG_Z2_DONE_CYCLE_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE2: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(2),AUTO_CONFIG_Z2_DONE_CYCLE_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0'); AUTO_CONFIG_Z2_DONE_CYCLE_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW)); A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0)); A_LAN(2) <= NOT (((NOT A(2) AND RESET AND NOT CP_CS) OR (RESET AND NOT Z3_ADR_1 AND CP_CS))); A_LAN(3) <= ((RESET AND A(3) AND NOT CP_CS) OR (NOT RESET AND LAN_A_INIT(3)) OR (RESET AND Z3_ADR(2) AND CP_CS)); A_LAN(4) <= NOT (((RESET AND NOT Z3_ADR(3) AND CP_CS) OR (NOT A(4) AND RESET AND NOT CP_CS))); A_LAN(5) <= NOT (((NOT A(5) AND RESET AND NOT CP_CS) OR (RESET AND NOT Z3_ADR(4) AND CP_CS))); A_LAN(6) <= ((RESET AND Z3_ADR(5)) OR (NOT RESET AND LAN_A_INIT(6))); A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6))); A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7))); A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8))); A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9))); A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10))); A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11))); A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12))); CFOUT <= NOT ((AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND AUTO_CONFIG_Z2_DONE(2))); FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); CP_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,NOT AS,'0',NOT RESET); CP_CS_D <= ((SHUT_UP_Z2(1)) OR (EXP29_.EXP) OR (CP_BASEADR(0) AND NOT A(16).PIN) OR (NOT CP_BASEADR(0) AND A(16).PIN) OR (NOT CP_BASEADR(2) AND A(18).PIN) OR (CP_BASEADR(7) AND NOT A(23).PIN) OR (NOT CP_BASEADR(7) AND A(23).PIN) OR (CP_BASEADR(6) AND NOT A(22).PIN) OR (NOT CP_BASEADR(6) AND A(22).PIN)); CP_RD <= NOT ((NOT AS AND NOT CP_RD_S)); FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0'); CP_RD_S_D <= ((NOT AS AND NOT UDS AND RW AND NOT CP_CS) OR (NOT AS AND NOT LDS AND RW AND NOT CP_CS)); CP_WE <= NOT ((NOT AS AND NOT CP_WE_S AND CP_WE_QUIRK)); FDCPE_CP_WE_QUIRK: FDCPE port map (CP_WE_QUIRK,CP_WE_S,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0'); FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0'); CP_WE_S_D <= ((NOT AS AND NOT UDS AND NOT RW AND NOT CP_CS) OR (NOT AS AND NOT LDS AND NOT RW AND NOT CP_CS)); D_I(0) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(16) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(0).PIN) OR (FCS AND DQ(0).PIN) OR (NOT LAN_ACCESS AND DQ(0).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(1) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(17) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(1).PIN) OR (FCS AND DQ(1).PIN) OR (NOT LAN_ACCESS AND DQ(1).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(2) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(18) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(2).PIN) OR (FCS AND DQ(2).PIN) OR (NOT LAN_ACCESS AND DQ(2).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(3) <= ((FCS AND DQ(3).PIN) OR (NOT LAN_ACCESS AND DQ(3).PIN) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS) OR (Z3_DATA(19) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(3).PIN)); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(4) <= ((FCS AND DQ(4).PIN) OR (NOT LAN_ACCESS AND DQ(4).PIN) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS) OR (Z3_DATA(20) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(4).PIN)); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(5) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS) OR (Z3_DATA(21) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(5).PIN) OR (FCS AND DQ(5).PIN) OR (NOT LAN_ACCESS AND DQ(5).PIN)); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(6) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(22) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(6).PIN) OR (FCS AND DQ(6).PIN) OR (NOT LAN_ACCESS AND DQ(6).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(7) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(23) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(7).PIN) OR (FCS AND DQ(7).PIN) OR (NOT LAN_ACCESS AND DQ(7).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(8) <= ((FCS AND DQ(8).PIN) OR (NOT LAN_ACCESS AND DQ(8).PIN) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS) OR (Z3_DATA(24) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(8).PIN)); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(9) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(25) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(9).PIN) OR (FCS AND DQ(9).PIN) OR (NOT LAN_ACCESS AND DQ(9).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(10) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(26) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(10).PIN) OR (FCS AND DQ(10).PIN) OR (NOT LAN_ACCESS AND DQ(10).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(11) <= ((NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS) OR (Z3_DATA(27) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT RW AND DQ(11).PIN) OR (FCS AND DQ(11).PIN) OR (NOT LAN_ACCESS AND DQ(11).PIN) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(12) <= ((AS AND FCS AND DQ(12).PIN) OR (Z3_DATA(28) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS AND D_Z2_OUT(0)) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND D_Z2_OUT(0)) OR (NOT RW AND DQ(12).PIN) OR (AS AND NOT LAN_ACCESS AND DQ(12).PIN) OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(12).PIN) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(12).PIN)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(13) <= ((AS AND FCS AND DQ(13).PIN) OR (Z3_DATA(29) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS AND D_Z2_OUT(1)) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND D_Z2_OUT(1)) OR (NOT RW AND DQ(13).PIN) OR (AS AND NOT LAN_ACCESS AND DQ(13).PIN) OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(13).PIN) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(13).PIN)); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(14) <= ((AS AND FCS AND DQ(14).PIN) OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(14).PIN) OR (Z3_DATA(30) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT AS AND RW AND FCS AND AUTOCONFIG_Z2_ACCESS AND D_Z2_OUT(2)) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND D_Z2_OUT(2)) OR (NOT RW AND DQ(14).PIN) OR (AS AND NOT LAN_ACCESS AND DQ(14).PIN) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(14).PIN)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= D_10_IOBUFE/D_10_IOBUFE_TRST; D_I(15) <= ((AUTO_CONFIG_Z2_DONE_CYCLE(0).EXP) OR (AS AND FCS AND DQ(15).PIN) OR (AS AND NOT LAN_ACCESS AND DQ(15).PIN) OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(15).PIN) OR (Z3_DATA(31) AND RW AND NOT FCS AND LAN_ACCESS) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND D_Z2_OUT(3)) OR (NOT RW AND DQ(15).PIN) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(15).PIN)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= D_10_IOBUFE/D_10_IOBUFE_TRST; DQ_I(0) <= ((RESET AND UDS AND LDS AND DS1 AND DS0 AND D(0).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(0)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(0)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(0)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(0)) OR (RESET AND RW AND D(0).PIN) OR (RESET AND FCS AND D(0).PIN) OR (RESET AND NOT LAN_ACCESS AND D(0).PIN)); DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z'; DQ_OE(0) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(1) <= ((RESET AND UDS AND LDS AND DS1 AND DS0 AND D(1).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(1)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(1)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(1)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(1)) OR (NOT RESET AND LAN_D_INIT(1)) OR (RESET AND RW AND D(1).PIN) OR (RESET AND FCS AND D(1).PIN) OR (RESET AND NOT LAN_ACCESS AND D(1).PIN)); DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z'; DQ_OE(1) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(2) <= ((DQ_5_IOBUFE.EXP) OR (RESET AND RW AND D(2).PIN) OR (RESET AND FCS AND D(2).PIN) OR (RESET AND NOT LAN_ACCESS AND D(2).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(2).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(2))); DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z'; DQ_OE(2) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(3) <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(3)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(3)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(3)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(3)) OR (RESET AND RW AND D(3).PIN) OR (RESET AND FCS AND D(3).PIN) OR (RESET AND NOT LAN_ACCESS AND D(3).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(3).PIN)); DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z'; DQ_OE(3) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ(4)_BUFR <= ((DQ_10_IOBUFE.EXP) OR (RESET AND RW AND D(4).PIN) OR (RESET AND FCS AND D(4).PIN) OR (RESET AND NOT LAN_ACCESS AND D(4).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(4).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(4)) OR (NOT RESET AND LAN_D_INIT(1))); DQ_I(4) <= DQ(4)_BUFR; DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z'; DQ_OE(4) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(5) <= ((_19_.EXP) OR (RESET AND RW AND D(5).PIN) OR (RESET AND FCS AND D(5).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(5).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(5)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(5)) OR (RESET AND NOT LAN_ACCESS AND D(5).PIN)); DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z'; DQ_OE(5) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(6) <= ((_18_.EXP) OR (RESET AND RW AND D(6).PIN) OR (RESET AND FCS AND D(6).PIN) OR (RESET AND NOT LAN_ACCESS AND D(6).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(6).PIN) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(6))); DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z'; DQ_OE(6) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(7)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(7)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(7)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(7)) OR (RESET AND RW AND D(7).PIN) OR (RESET AND FCS AND D(7).PIN) OR (RESET AND NOT LAN_ACCESS AND D(7).PIN) OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(7).PIN)); DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z'; DQ_OE(7) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ(8)_BUFR <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(8)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(8)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(8)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(8)) OR (NOT RESET AND LAN_D_INIT(8)) OR (RESET AND D(8).PIN AND RW) OR (RESET AND D(8).PIN AND FCS) OR (RESET AND D(8).PIN AND NOT LAN_ACCESS) OR (RESET AND D(8).PIN AND UDS AND LDS AND DS1 AND DS0)); DQ_I(8) <= DQ(8)_BUFR; DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z'; DQ_OE(8) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(9) <= ((DQ_11_IOBUFE.EXP) OR (RESET AND D(9).PIN AND FCS) OR (RESET AND D(9).PIN AND UDS AND LDS AND DS1 AND DS0) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(9)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(9)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(9)) OR (NOT RESET AND LAN_D_INIT(1)) OR (RESET AND D(9).PIN AND RW) OR (RESET AND D(9).PIN AND NOT LAN_ACCESS)); DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z'; DQ_OE(9) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(10) <= ((EXP48_.EXP) OR (RESET AND D(10).PIN AND RW) OR (RESET AND D(10).PIN AND FCS) OR (RESET AND D(10).PIN AND NOT LAN_ACCESS) OR (RESET AND D(10).PIN AND UDS AND LDS AND DS1 AND DS0) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(10)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z'; DQ_OE(10) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(11) <= ((DQ_13_IOBUFE.EXP) OR (RESET AND D(11).PIN AND FCS) OR (RESET AND D(11).PIN AND UDS AND LDS AND DS1 AND DS0) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(11)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(11)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(11)) OR (NOT RESET AND LAN_D_INIT(8)) OR (RESET AND D(11).PIN AND RW) OR (RESET AND D(11).PIN AND NOT LAN_ACCESS)); DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z'; DQ_OE(11) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(12) <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(12)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(12)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(12)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(12)) OR (RESET AND D(12).PIN AND RW) OR (RESET AND D(12).PIN AND FCS) OR (RESET AND D(12).PIN AND NOT LAN_ACCESS) OR (RESET AND D(12).PIN AND UDS AND LDS AND DS1 AND DS0)); DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z'; DQ_OE(12) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(13) <= ((RESET AND D(13).PIN AND UDS AND LDS AND DS1 AND DS0) OR (RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(13)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(13)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(13)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(13)) OR (RESET AND D(13).PIN AND RW) OR (RESET AND D(13).PIN AND FCS) OR (RESET AND D(13).PIN AND NOT LAN_ACCESS)); DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z'; DQ_OE(13) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(14) <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(14)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(14)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(14)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(14)) OR (RESET AND D(14).PIN AND RW) OR (RESET AND D(14).PIN AND FCS) OR (RESET AND D(14).PIN AND NOT LAN_ACCESS) OR (RESET AND D(14).PIN AND UDS AND LDS AND DS1 AND DS0)); DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z'; DQ_OE(14) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_I(15) <= ((RESET AND NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(15)) OR (RESET AND NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(15)) OR (RESET AND NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(15)) OR (RESET AND NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS AND DQ_DATA(15)) OR (RESET AND D(15).PIN AND RW) OR (RESET AND D(15).PIN AND FCS) OR (RESET AND D(15).PIN AND NOT LAN_ACCESS) OR (RESET AND D(15).PIN AND UDS AND LDS AND DS1 AND DS0)); DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z'; DQ_OE(15) <= DQ_4_IOBUFE/DQ_4_IOBUFE_TRST; DQ_4_IOBUFE/DQ_4_IOBUFE_TRST <= ((NOT RESET) OR (NOT LDS AND NOT RW AND NOT FCS AND LAN_ACCESS) OR (NOT DS1 AND NOT RW AND NOT FCS AND LAN_ACCESS) OR (NOT DS0 AND NOT RW AND NOT FCS AND LAN_ACCESS) OR (NOT AS AND NOT RW AND NOT CP_CS) OR (NOT UDS AND NOT RW AND NOT FCS AND LAN_ACCESS)); FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(0) <= ((D(8).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(8).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN) OR (UDS AND LDS AND A(16).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND A(8).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$1248) OR (A(16).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(8).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN)); FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(1) <= ((UDS AND LDS AND A(17).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND A(9).PIN AND LAN_SM_FSM_FFd13) OR (D(9).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(9).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN) OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$1248) OR (A(17).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(9).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN)); FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(2) <= ((D(10).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(10).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN) OR (UDS AND LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND A(18).PIN) OR (UDS AND LDS AND NOT DQ_SWAP AND A(10).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$1248) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(18).PIN) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(10).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN)); FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(3) <= ((DQ_DATA(5).EXP) OR (D(11).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(11).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN) OR (UDS AND LDS AND A(19).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$1248) OR (A(19).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(11).PIN)); FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(4) <= ((D(12).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(12).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN) OR (UDS AND LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND A(20).PIN) OR (UDS AND LDS AND NOT DQ_SWAP AND A(12).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$1248) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(20).PIN) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(12).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN)); FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(5) <= ((DQ_9_IOBUFE.EXP) OR (D(13).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(13).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN) OR (UDS AND LDS AND A(21).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$1248) OR (A(21).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(13).PIN)); FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(6) <= ((D(14).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(14).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN) OR (UDS AND LDS AND A(22).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND A(14).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$1248) OR (A(22).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(14).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN)); FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(7) <= ((D(15).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(15).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN) OR (UDS AND LDS AND A(23).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND A(15).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$1248) OR (A(23).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(15).PIN) OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN)); FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(8) <= ((D(8).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN) OR (UDS AND LDS AND A(16).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND DQ_SWAP AND A(8).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$1248) OR (A(16).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(8).PIN) OR (D(8).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(9) <= ((D(9).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN) OR (UDS AND LDS AND A(17).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND DQ_SWAP AND A(9).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$1248) OR (A(17).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(9).PIN) OR (D(9).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(10) <= ((D(10).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN) OR (UDS AND LDS AND DQ_SWAP AND A(10).PIN AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND A(18).PIN) OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$1248) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(10).PIN) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(18).PIN) OR (D(10).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(11) <= ((NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN) OR (UDS AND LDS AND A(19).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND DQ_SWAP AND A(11).PIN AND LAN_SM_FSM_FFd13) OR (D(11).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$1248) OR (A(19).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(11).PIN) OR (D(11).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(12) <= ((D(12).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN) OR (UDS AND LDS AND DQ_SWAP AND A(12).PIN AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND A(20).PIN) OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$1248) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(12).PIN) OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(20).PIN) OR (D(12).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(13) <= ((DQ_DATA(3).EXP) OR (D(13).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (D(13).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN) OR (UDS AND LDS AND DQ_SWAP AND A(13).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$1248) OR (A(21).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(13).PIN)); FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(14) <= ((D(14).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN) OR (UDS AND LDS AND A(22).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND DQ_SWAP AND A(14).PIN AND LAN_SM_FSM_FFd13) OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$1248) OR (A(22).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(14).PIN) OR (D(14).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(15) <= ((D(15).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN) OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN) OR (UDS AND LDS AND DQ_SWAP AND A(15).PIN AND LAN_SM_FSM_FFd13) OR (UDS AND LDS AND A(23).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13) OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$1248) OR (A(23).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3) OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(15).PIN) OR (D(15).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)); FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT RESET); DQ_SWAP_D <= ((LAN_BASEADR(0) AND LAN_BASEADR(1) AND NOT LAN_BASEADR(2) AND A(17).PIN AND A(16).PIN AND A(13).PIN AND A(14).PIN AND NOT A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (NOT LAN_BASEADR(0) AND NOT LAN_BASEADR(1) AND LAN_BASEADR(2) AND NOT A(17).PIN AND NOT A(16).PIN AND A(13).PIN AND A(14).PIN AND A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (LAN_BASEADR(0) AND NOT LAN_BASEADR(1) AND NOT LAN_BASEADR(2) AND NOT A(17).PIN AND A(16).PIN AND A(13).PIN AND A(14).PIN AND NOT A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (NOT LAN_BASEADR(0) AND LAN_BASEADR(1) AND NOT LAN_BASEADR(2) AND A(17).PIN AND NOT A(16).PIN AND A(13).PIN AND A(14).PIN AND NOT A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (NOT LAN_BASEADR(0) AND NOT LAN_BASEADR(1) AND NOT LAN_BASEADR(2) AND NOT A(17).PIN AND NOT A(16).PIN AND A(13).PIN AND A(14).PIN AND NOT A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (LAN_BASEADR(0) AND LAN_BASEADR(1) AND LAN_BASEADR(2) AND A(17).PIN AND A(16).PIN AND A(13).PIN AND A(14).PIN AND A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (LAN_BASEADR(0) AND NOT LAN_BASEADR(1) AND LAN_BASEADR(2) AND NOT A(17).PIN AND A(16).PIN AND A(13).PIN AND A(14).PIN AND A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61) OR (NOT LAN_BASEADR(0) AND LAN_BASEADR(1) AND LAN_BASEADR(2) AND A(17).PIN AND NOT A(16).PIN AND A(13).PIN AND A(14).PIN AND A(18).PIN AND NOT Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D AND NOT $OpTx$FX_DC$81 AND NOT $OpTx$FX_DC$82 AND NOT $OpTx$FX_DC$83 AND NOT $OpTx$FX_DC$84 AND NOT $OpTx$INV$62 AND NOT $OpTx$INV$61)); DTACK_I <= '0'; DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; DTACK_OE <= (NOT FCS AND LAN_READY); D_10_IOBUFE/D_10_IOBUFE_TRST <= ((NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT AS AND RW AND NOT CP_CS) OR (RW AND NOT FCS AND LAN_ACCESS)); FDCPE_D_Z2_OUT0: FDCPE port map (D_Z2_OUT(0),D_Z2_OUT_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); D_Z2_OUT_D(0) <= ((AS) OR (A(6)) OR (NOT AUTOCONFIG_Z2_ACCESS) OR (A(5) AND A(4)) OR (A(5) AND NOT A(2)) OR (UDS AND LDS) OR (A(4) AND NOT A(2) AND NOT A(3)) OR (A(4) AND A(1) AND NOT A(3)) OR (NOT A(4) AND NOT A(2) AND A(1)) OR (A(2) AND NOT A(1) AND A(3)) OR (NOT A(5) AND NOT A(4) AND A(1) AND A(3)) OR (NOT A(5) AND A(1) AND AUTO_CONFIG_Z2_DONE(0) AND NOT A(3)) OR (NOT A(5) AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT A(3))); FDCPE_D_Z2_OUT1: FDCPE port map (D_Z2_OUT(1),D_Z2_OUT_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); D_Z2_OUT_D(1) <= ((AS) OR (A(6)) OR (NOT AUTOCONFIG_Z2_ACCESS) OR (D_15_IOBUFE.EXP) OR (A(5) AND NOT A(2)) OR (A(5) AND NOT $OpTx$$OpTx$FX_DC$87_INV$1549) OR (UDS AND LDS) OR (NOT A(4) AND A(2) AND A(3)) OR (NOT A(4) AND NOT A(1) AND A(3)) OR (A(4) AND A(2) AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(3)) OR (A(4) AND NOT A(2) AND A(1) AND A(3)) OR (A(4) AND NOT A(2) AND NOT A(1) AND NOT A(3)) OR (A(4) AND NOT A(1) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT A(3)) OR (NOT A(5) AND A(2) AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND $OpTx$$OpTx$FX_DC$87_INV$1549)); FDCPE_D_Z2_OUT2: FDCPE port map (D_Z2_OUT(2),D_Z2_OUT_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); D_Z2_OUT_D(2) <= ((AS) OR (A(6)) OR (NOT AUTOCONFIG_Z2_ACCESS) OR (A(5) AND A(4)) OR (A(5) AND NOT A(2)) OR (A(4) AND NOT A(2)) OR (NOT A(4) AND A(3)) OR (A(1) AND A(3)) OR (SHUT_UP_Z2(0).EXP) OR (A(5) AND NOT A(1)) OR (UDS AND LDS) OR (A(4) AND NOT A(1) AND NOT A(3)) OR (NOT A(2) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0)) OR (NOT A(4) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1))); FDCPE_D_Z2_OUT3: FDCPE port map (D_Z2_OUT(3),D_Z2_OUT_D(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); D_Z2_OUT_D(3) <= ((NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND A(3) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)); IDE_A(0) <= A(9).PIN; IDE_A(1) <= A(10).PIN; IDE_A(2) <= A(11).PIN; FDCPE_IDE_ACCESS: FDCPE port map (IDE_ACCESS,IDE_ACCESS_D,NOT AS,NOT RESET,'0'); IDE_ACCESS_D <= ((IDE_BASEADR(6) AND A(22).PIN AND NOT $OpTx$INV$63) OR (NOT IDE_BASEADR(6) AND NOT A(22).PIN AND NOT $OpTx$INV$63)); FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(8).PIN AND NOT IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(8).PIN AND NOT IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(8).PIN AND IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(8).PIN AND IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(9).PIN AND NOT IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(9).PIN AND NOT IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(9).PIN AND IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(9).PIN AND IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(10).PIN AND NOT IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(10).PIN AND NOT IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(10).PIN AND IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(10).PIN AND IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(11).PIN AND NOT IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(11).PIN AND NOT IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(11).PIN AND IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(11).PIN AND IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(12).PIN AND NOT IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(12).PIN AND NOT IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(12).PIN AND IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(12).PIN AND IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(13).PIN AND NOT IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(13).PIN AND NOT IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(13).PIN AND IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(13).PIN AND IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(14).PIN AND NOT IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(14).PIN AND NOT IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(14).PIN AND IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(14).PIN AND IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(15).PIN AND NOT IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(15).PIN AND NOT IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(15).PIN AND IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(15).PIN AND IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); IDE_CS(0) <= NOT A(12).PIN; IDE_CS(1) <= NOT A(13).PIN; FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET,IDE_ENABLE_CE); IDE_ENABLE_CE <= (NOT AS AND NOT RW AND IDE_ACCESS); IDE_R <= NOT ((NOT AS AND NOT IDE_R_S)); FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_R_S_D <= (NOT AS AND RW AND IDE_ACCESS AND NOT IDE_ENABLE); IDE_W <= NOT ((NOT AS AND NOT IDE_W_S)); FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); IDE_W_S_D <= (NOT AS AND NOT RW AND IDE_ACCESS); INT2_OUT_I <= '0'; INT2_OUT <= INT2_OUT_I when INT2_OUT_OE = '1' else 'Z'; INT2_OUT_OE <= (NOT LAN_IRQ_OUT AND LAN_INT_ENABLE); INT6_OUT_I <= '0'; INT6_OUT <= INT6_OUT_I when INT6_OUT_OE = '1' else 'Z'; INT6_OUT_OE <= NOT CP_IRQ; FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT RESET,'0'); LAN_ACCESS_D <= (( Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D) OR ($OpTx$FX_DC$83) OR ($OpTx$FX_DC$84) OR ($OpTx$INV$62) OR ($OpTx$INV$61) OR (LAN_SM_FSM_FFd4.EXP) OR (LAN_BASEADR(0) AND NOT A(16).PIN) OR (NOT LAN_BASEADR(0) AND A(16).PIN) OR (LAN_BASEADR(1) AND NOT A(17).PIN) OR (NOT LAN_BASEADR(1) AND A(17).PIN) OR (LAN_BASEADR(2) AND NOT A(18).PIN) OR (NOT LAN_BASEADR(2) AND A(18).PIN) OR (LAN_BASEADR(3) AND NOT A(19).PIN)); FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET); FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),LAN_A_INIT_D(6),CLK_EXT,'0',RESET); LAN_A_INIT_D(6) <= (NOT LAN_RST_SM_FSM_FFd6 AND NOT LAN_RST_SM_FSM_FFd5 AND NOT LAN_RST_SM_FSM_FFd7 AND NOT LAN_A_INIT(3)); FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(8) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR9: FTCPE port map (LAN_BASEADR(9),LAN_BASEADR_T(9),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(9) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR10: FTCPE port map (LAN_BASEADR(10),LAN_BASEADR_T(10),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(10) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR11: FTCPE port map (LAN_BASEADR(11),LAN_BASEADR_T(11),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(11) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR12: FTCPE port map (LAN_BASEADR(12),LAN_BASEADR_T(12),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(12) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(13) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(14) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); FTCPE_LAN_BASEADR15: FTCPE port map (LAN_BASEADR(15),LAN_BASEADR_T(15),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); LAN_BASEADR_T(15) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT UDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS) OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT LDS AND A(6) AND NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)); LAN_CFG_I(1) <= '0'; LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z'; LAN_CFG_OE(1) <= '0'; LAN_CFG_I(2) <= '0'; LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z'; LAN_CFG_OE(2) <= '0'; LAN_CFG_I(3) <= '0'; LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z'; LAN_CFG_OE(3) <= '0'; LAN_CFG_I(4) <= '0'; LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z'; LAN_CFG_OE(4) <= '0'; LAN_CS <= ((NOT RESET AND LAN_CS_RST) OR (Z3_ADR(13) AND LAN_CS_RST) OR (RESET AND NOT Z3_ADR(13) AND LAN_ACCESS)); FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0'); LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_A_INIT(3)); FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_D_INIT_D(1),CLK_EXT,RESET,'0'); LAN_D_INIT_D(1) <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd4); FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),LAN_D_INIT_D(8),CLK_EXT,RESET,'0'); LAN_D_INIT_D(8) <= (NOT LAN_RST_SM_FSM_FFd6 AND NOT LAN_RST_SM_FSM_FFd5 AND NOT LAN_RST_SM_FSM_FFd7 AND NOT LAN_A_INIT(3)); FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,'0','0'); LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT UDS AND NOT RW AND LAN_SM_FSM_FFd12 AND NOT LAN_INT_ENABLE AND NOT LAN_SM_RST) OR (NOT D(15).PIN AND NOT UDS AND NOT RW AND LAN_SM_FSM_FFd12 AND LAN_INT_ENABLE AND NOT LAN_SM_RST) OR (UDS AND NOT DS1 AND A(23).PIN AND NOT RW AND LAN_SM_FSM_FFd12 AND NOT LAN_INT_ENABLE AND NOT LAN_SM_RST) OR (UDS AND NOT DS1 AND NOT A(23).PIN AND NOT RW AND LAN_SM_FSM_FFd12 AND LAN_INT_ENABLE AND NOT LAN_SM_RST)); FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET); FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET); LAN_IRQ_OUT_D <= ((LAN_INT) OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0)); LAN_RD <= (RESET AND NOT FCS AND LAN_RD_S); FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_RD_S_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd11) OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd11 AND Z3_ADR(13)) OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd11 AND NOT LAN_SM_FSM_FFd13)); FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,LAN_SM_RST,'0'); LAN_READY_D <= ((NOT DS1 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (NOT DS0 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)); FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd1_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd2); FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd3,CLK_EXT,RESET,'0'); FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd4,CLK_EXT,RESET,'0'); FDCPE_LAN_RST_SM_FSM_FFd4: FDCPE port map (LAN_RST_SM_FSM_FFd4,LAN_RST_SM_FSM_FFd5,CLK_EXT,RESET,'0'); FDCPE_LAN_RST_SM_FSM_FFd5: FDCPE port map (LAN_RST_SM_FSM_FFd5,LAN_RST_SM_FSM_FFd6,CLK_EXT,RESET,'0'); FDCPE_LAN_RST_SM_FSM_FFd6: FDCPE port map (LAN_RST_SM_FSM_FFd6,LAN_RST_SM_FSM_FFd7,CLK_EXT,RESET,'0'); FDCPE_LAN_RST_SM_FSM_FFd7: FDCPE port map (LAN_RST_SM_FSM_FFd7,LAN_A_INIT(3),CLK_EXT,RESET,'0'); FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd1_D <= (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); FDCPE_LAN_SM_FSM_FFd10: FDCPE port map (LAN_SM_FSM_FFd10,LAN_SM_FSM_FFd10_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd10_D <= ((LAN_SM_FSM_FFd6) OR (UDS AND LDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)); FDCPE_LAN_SM_FSM_FFd11: FDCPE port map (LAN_SM_FSM_FFd11,LAN_SM_FSM_FFd11_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd11_D <= ((NOT UDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13) OR (NOT LDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)); FTCPE_LAN_SM_FSM_FFd12: FTCPE port map (LAN_SM_FSM_FFd12,LAN_SM_FSM_FFd12_T,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd12_T <= (NOT LAN_SM_FSM_FFd12 AND Z3_ADR(13) AND LAN_SM_FSM_FFd13); FDCPE_LAN_SM_FSM_FFd13: FDCPE port map (LAN_SM_FSM_FFd13,'0',CLK_EXT,'0',LAN_SM_RST); FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd8,CLK_EXT,LAN_SM_RST,'0'); FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4) OR (DS1 AND DS0 AND LAN_SM_FSM_FFd3)); FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd9,CLK_EXT,LAN_SM_RST,'0'); FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd5_D <= (NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10); FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd6_D <= ((NOT DS1 AND LAN_SM_FSM_FFd7) OR (NOT DS0 AND LAN_SM_FSM_FFd7)); FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd7_D <= ((LAN_SM_FSM_FFd11) OR (DS1 AND DS0 AND LAN_SM_FSM_FFd7)); FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd8_D <= ((NOT DS1 AND LAN_SM_FSM_FFd3) OR (NOT DS0 AND LAN_SM_FSM_FFd3) OR (UDS AND LDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)); FDCPE_LAN_SM_FSM_FFd9: FDCPE port map (LAN_SM_FSM_FFd9,LAN_SM_FSM_FFd9_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd9_D <= ((NOT UDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13) OR (NOT LDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)); FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,NOT CLK_EXT,'0','0'); LAN_SM_RST_D <= ((RESET AND NOT UDS AND NOT FCS AND LAN_ACCESS AND BERR) OR (RESET AND NOT LDS AND NOT FCS AND LAN_ACCESS AND BERR) OR (RESET AND NOT DS1 AND NOT FCS AND LAN_ACCESS AND BERR) OR (RESET AND NOT DS0 AND NOT FCS AND LAN_ACCESS AND BERR)); LAN_WRH <= ((NOT RESET AND LAN_WR_RST) OR (FCS AND LAN_WR_RST) OR (RESET AND NOT FCS AND LAN_WRH_S)); FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd9) OR (NOT DS0 AND LAN_SM_FSM_FFd8)); LAN_WRL <= ((NOT RESET AND LAN_WR_RST) OR (FCS AND LAN_WR_RST) OR (RESET AND NOT FCS AND LAN_WRL_S)); FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd9) OR (NOT DS1 AND LAN_SM_FSM_FFd8)); FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0'); LAN_WR_RST_D <= (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd6); MTACK_I <= '0'; MTACK <= MTACK_I when MTACK_OE = '1' else 'Z'; MTACK_OE <= '0'; Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D <= LAN_BASEADR(14) XOR Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000/Mcompar_LAN_ACCESS_cmp_eq0000_or0007_xor0000_D <= D(14).PIN; OVR_I <= '0'; OVR <= OVR_I when OVR_OE = '1' else 'Z'; OVR_OE <= (NOT FCS AND LAN_ACCESS); OWN_I <= '0'; OWN <= OWN_I when OWN_OE = '1' else 'Z'; OWN_OE <= '0'; ROM_B(0) <= '0'; ROM_B(1) <= '0'; ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S AND NOT AUTOBOOT_OFF)); FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); ROM_OE_S_D <= (NOT AS AND RW AND IDE_ACCESS AND IDE_ENABLE); FTCPE_SHUT_UP_Z20: FTCPE port map (SHUT_UP_Z2(0),SHUT_UP_Z2_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); SHUT_UP_Z2_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(0)) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(0))); FTCPE_SHUT_UP_Z21: FTCPE port map (SHUT_UP_Z2(1),SHUT_UP_Z2_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); SHUT_UP_Z2_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1)) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1))); FTCPE_SHUT_UP_Z22: FTCPE port map (SHUT_UP_Z2(2),SHUT_UP_Z2_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET); SHUT_UP_Z2_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(2)) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(2))); SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C1 XOR SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C3; SLAVE <= ((AS AND FCS) OR (AS AND NOT LAN_ACCESS) OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND CP_CS) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND NOT IDE_ACCESS AND CP_CS)); FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT RESET); FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0'); Z3_A_LOW_D <= ((DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd13) OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd13) OR (NOT UDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6) OR (NOT UDS AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6) OR (NOT LDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6) OR (NOT LDS AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6)); FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,LAN_SM_FSM_FFd7); Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-10-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 D<0> 74 A<15> 3 A_LAN<1> 75 AUTOBOOT_OFF 4 A_LAN<0> 76 LAN_WRL 5 A_LAN<3> 77 FCS 6 A_LAN<2> 78 DS1 7 A_LAN<5> 79 Z3 8 VCC 80 AS 9 A_LAN<4> 81 UDS 10 A_LAN<7> 82 LDS 11 A_LAN<6> 83 RW 12 LAN_CFG<1> 84 VCC 13 LAN_CFG<3> 85 DTACK 14 D<6> 86 A<23> 15 D<3> 87 A<22> 16 D<7> 88 A<21> 17 D<1> 89 GND 18 GND 90 GND 19 D<8> 91 A<20> 20 D<5> 92 A<19> 21 D<4> 93 DS0 22 IDE_CS<0> 94 A<18> 23 IDE_CS<1> 95 A<17> 24 IDE_A<0> 96 MTACK 25 IDE_A<2> 97 A<16> 26 IDE_A<1> 98 BERR 27 IDE_R 99 GND 28 IDE_W 100 OVR 29 GND 101 TIE 30 CLK_EXT 102 C3 31 CP_IRQ 103 C1 32 INT2_OUT 104 CFIN 33 ROM_B<0> 105 CFOUT 34 CP_CS 106 SLAVE 35 ROM_OE 107 OWN 36 GND 108 GND 37 VCC 109 VCC 38 TIE 110 LAN_CFG<4> 39 D<2> 111 LAN_INT 40 D<9> 112 DQ<15> 41 D<10> 113 DQ<13> 42 VCC 114 GND 43 D<11> 115 DQ<11> 44 D<12> 116 DQ<9> 45 D<13> 117 DQ<1> 46 D<14> 118 DQ<0> 47 GND 119 DQ<3> 48 D<15> 120 DQ<2> 49 A<5> 121 DQ<5> 50 A<4> 122 TDO 51 A<6> 123 GND 52 A<3> 124 DQ<4> 53 A<7> 125 DQ<7> 54 A<2> 126 DQ<6> 55 VCC 127 VCC 56 A<8> 128 DQ<8> 57 A<1> 129 DQ<10> 58 A<9> 130 DQ<12> 59 A<10> 131 DQ<14> 60 A<11> 132 LAN_WRH 61 A<12> 133 LAN_CS 62 GND 134 LAN_RD 63 TDI 135 LAN_CFG<2> 64 A<13> 136 A_LAN<12> 65 TMS 137 A_LAN<13> 66 A<14> 138 A_LAN<10> 67 TCK 139 A_LAN<11> 68 INT6_OUT 140 A_LAN<8> 69 ROM_B<1> 141 VCC 70 CP_WE 142 A_LAN<9> 71 CP_RD 143 RESET 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-10-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 15