MDF Database:  version 1.0
MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144
MACROCELL | 8 | 10 | Z3_DATA<0>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<8>.PIN  | DQ<0>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 231 | 217 | 158
EQ | 7 | 
   A<8>.D = DQ_SWAP & DQ<8>.PIN
	# !DQ_SWAP & DQ<0>.PIN;
   A<8>.CLK = CLK_EXT;	// GCK
   A<8>.AP = LAN_SM_RST;
   A<8>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<8>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 5 | Z3_DATA<10>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<2>.PIN  | DQ<10>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 220 | 234 | 158
EQ | 7 | 
   A<18>.D = DQ_SWAP & DQ<2>.PIN
	# !DQ_SWAP & DQ<10>.PIN;
   A<18>.CLK = CLK_EXT;	// GCK
   A<18>.AP = LAN_SM_RST;
   A<18>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<18>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 2 | Z3_DATA<11>
ATTRIBUTES | 8685506 | 0
OUTPUTMC | 1 | 15 | 1
INPUTS | 11 | DQ_SWAP  | DQ<3>.PIN  | DQ<12>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | Z3_DATA<25>.EXP
INPUTMC | 8 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 15 | 3
INPUTP | 3 | 219 | 235 | 158
EXPORTS | 1 | 15 | 1
IMPORTS | 1 | 15 | 3
EQ | 9 | 
   A<19>.D = DQ_SWAP & DQ<3>.PIN
;Imported pterms FB16_4
	# !DQ_SWAP & DQ<11>.PIN;
   A<19>.CLK = CLK_EXT;	// GCK
   A<19>.AP = LAN_SM_RST;
   A<19>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<19>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
    Z3_DATA<11>.EXP  =  !DQ_SWAP & DQ<12>.PIN
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 1 | Z3_DATA<12>
ATTRIBUTES | 8685506 | 0
OUTPUTMC | 1 | 15 | 0
INPUTS | 11 | DQ_SWAP  | DQ<4>.PIN  | DQ<10>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | Z3_DATA<11>.EXP
INPUTMC | 8 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 15 | 2
INPUTP | 3 | 225 | 234 | 158
EXPORTS | 1 | 15 | 0
IMPORTS | 1 | 15 | 2
EQ | 9 | 
   A<20>.D = DQ_SWAP & DQ<4>.PIN
;Imported pterms FB16_3
	# !DQ_SWAP & DQ<12>.PIN;
   A<20>.CLK = CLK_EXT;	// GCK
   A<20>.AP = LAN_SM_RST;
   A<20>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<20>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
    Z3_DATA<12>.EXP  =  !DQ_SWAP & DQ<10>.PIN
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 16 | Z3_DATA<13>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<5>.PIN  | DQ<13>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 221 | 204 | 158
EQ | 7 | 
   A<21>.D = DQ_SWAP & DQ<5>.PIN
	# !DQ_SWAP & DQ<13>.PIN;
   A<21>.CLK = CLK_EXT;	// GCK
   A<21>.AP = LAN_SM_RST;
   A<21>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<21>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 14 | Z3_DATA<14>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<6>.PIN  | DQ<14>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 227 | 236 | 158
EQ | 7 | 
   A<22>.D = DQ_SWAP & DQ<6>.PIN
	# !DQ_SWAP & DQ<14>.PIN;
   A<22>.CLK = CLK_EXT;	// GCK
   A<22>.AP = LAN_SM_RST;
   A<22>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<22>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 13 | Z3_DATA<15>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<7>.PIN  | DQ<15>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 226 | 202 | 158
EQ | 7 | 
   A<23>.D = DQ_SWAP & DQ<7>.PIN
	# !DQ_SWAP & DQ<15>.PIN;
   A<23>.CLK = CLK_EXT;	// GCK
   A<23>.AP = LAN_SM_RST;
   A<23>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<23>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 13 | Z3_DATA<1>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<9>.PIN  | DQ<1>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 209 | 216 | 158
EQ | 7 | 
   A<9>.D = DQ_SWAP & DQ<9>.PIN
	# !DQ_SWAP & DQ<1>.PIN;
   A<9>.CLK = CLK_EXT;	// GCK
   A<9>.AP = LAN_SM_RST;
   A<9>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<9>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 16 | Z3_DATA<2>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<2>.PIN  | DQ<10>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 220 | 234 | 158
EQ | 7 | 
   A<10>.D = DQ_SWAP & DQ<10>.PIN
	# !DQ_SWAP & DQ<2>.PIN;
   A<10>.CLK = CLK_EXT;	// GCK
   A<10>.AP = LAN_SM_RST;
   A<10>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<10>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 2 | Z3_DATA<3>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<3>.PIN  | DQ<11>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 219 | 207 | 158
EQ | 7 | 
   A<11>.D = DQ_SWAP & DQ<11>.PIN
	# !DQ_SWAP & DQ<3>.PIN;
   A<11>.CLK = CLK_EXT;	// GCK
   A<11>.AP = LAN_SM_RST;
   A<11>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<11>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 4 | Z3_DATA<4>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<4>.PIN  | DQ<12>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 225 | 235 | 158
EQ | 7 | 
   A<12>.D = DQ_SWAP & DQ<12>.PIN
	# !DQ_SWAP & DQ<4>.PIN;
   A<12>.CLK = CLK_EXT;	// GCK
   A<12>.AP = LAN_SM_RST;
   A<12>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<12>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 9 | Z3_DATA<5>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<5>.PIN  | DQ<13>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 221 | 204 | 158
EQ | 7 | 
   A<13>.D = DQ_SWAP & DQ<13>.PIN
	# !DQ_SWAP & DQ<5>.PIN;
   A<13>.CLK = CLK_EXT;	// GCK
   A<13>.AP = LAN_SM_RST;
   A<13>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<13>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 10 | Z3_DATA<6>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<6>.PIN  | DQ<14>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 227 | 236 | 158
EQ | 7 | 
   A<14>.D = DQ_SWAP & DQ<14>.PIN
	# !DQ_SWAP & DQ<6>.PIN;
   A<14>.CLK = CLK_EXT;	// GCK
   A<14>.AP = LAN_SM_RST;
   A<14>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<14>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 12 | 7 | Z3_DATA<7>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<7>.PIN  | DQ<15>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 226 | 202 | 158
EQ | 7 | 
   A<15>.D = DQ_SWAP & DQ<15>.PIN
	# !DQ_SWAP & DQ<7>.PIN;
   A<15>.CLK = CLK_EXT;	// GCK
   A<15>.AP = LAN_SM_RST;
   A<15>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<15>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 10 | Z3_DATA<8>
ATTRIBUTES | 8685506 | 0
OUTPUTMC | 1 | 15 | 11
INPUTS | 9 | Z3_ADR<13>  | ROM_B_0_OBUF$BUF3.EXP  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 8 | 13 | 16 | 15 | 9 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 1 | 158
EXPORTS | 1 | 15 | 11
IMPORTS | 1 | 15 | 9
EQ | 12 | 
   A<16>.D = ;Imported pterms FB16_10
	  DQ_SWAP & DQ<0>.PIN
	# !DQ_SWAP & DQ<8>.PIN;
   A<16>.CLK = CLK_EXT;	// GCK
   A<16>.AP = LAN_SM_RST;
   A<16>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<16>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
    Z3_DATA<8>.EXP  =  LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & RW
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 7 | Z3_DATA<9>
ATTRIBUTES | 8685506 | 0
INPUTS | 10 | DQ_SWAP  | DQ<9>.PIN  | DQ<1>.PIN  | LAN_SM_RST  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3
INPUTMC | 7 | 0 | 15 | 8 | 0 | 13 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15
INPUTP | 3 | 209 | 216 | 158
EQ | 7 | 
   A<17>.D = DQ_SWAP & DQ<1>.PIN
	# !DQ_SWAP & DQ<9>.PIN;
   A<17>.CLK = CLK_EXT;	// GCK
   A<17>.AP = LAN_SM_RST;
   A<17>.OE = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   A<17>.CE = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 3 | 8 | AUTO_CONFIG_Z2_DONE<0>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 15 | 3 | 8 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 6 | 13 | 10 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 1 | 3 | 4 | 3 | 17
INPUTS | 5 | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE_CYCLE<0>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET  | AS
INPUTMC | 3 | 3 | 8 | 1 | 17 | 13 | 3
INPUTP | 2 | 263 | 152
EQ | 5 | 
   !AUTO_CONFIG_Z2_DONE<0>.D = !AUTO_CONFIG_Z2_DONE<0> & 
	!AUTO_CONFIG_Z2_DONE_CYCLE<0>;
   AUTO_CONFIG_Z2_DONE<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE<0>.AR = !RESET;
   AUTO_CONFIG_Z2_DONE<0>.CE = AS;

MACROCELL | 3 | 9 | AUTO_CONFIG_Z2_DONE<1>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 12 | 3 | 9 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 6 | 13 | 10 | 1 | 0 | 3 | 16 | 1 | 3 | 3 | 3 | 3 | 17
INPUTS | 5 | AUTO_CONFIG_Z2_DONE<1>  | AUTO_CONFIG_Z2_DONE_CYCLE<1>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET  | AS
INPUTMC | 3 | 3 | 9 | 1 | 15 | 13 | 3
INPUTP | 2 | 263 | 152
EQ | 5 | 
   !AUTO_CONFIG_Z2_DONE<1>.D = !AUTO_CONFIG_Z2_DONE<1> & 
	!AUTO_CONFIG_Z2_DONE_CYCLE<1>;
   AUTO_CONFIG_Z2_DONE<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE<1>.AR = !RESET;
   AUTO_CONFIG_Z2_DONE<1>.CE = AS;

MACROCELL | 8 | 17 | AUTO_CONFIG_Z2_DONE<2>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 3 | 8 | 17 | 1 | 12 | 13 | 10
INPUTS | 5 | AUTO_CONFIG_Z2_DONE<2>  | AUTO_CONFIG_Z2_DONE_CYCLE<2>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET  | AS
INPUTMC | 3 | 8 | 17 | 1 | 12 | 13 | 3
INPUTP | 2 | 263 | 152
EQ | 5 | 
   !AUTO_CONFIG_Z2_DONE<2>.D = !AUTO_CONFIG_Z2_DONE<2> & 
	!AUTO_CONFIG_Z2_DONE_CYCLE<2>;
   AUTO_CONFIG_Z2_DONE<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE<2>.AR = !RESET;
   AUTO_CONFIG_Z2_DONE<2>.CE = AS;

MACROCELL | 1 | 17 | AUTO_CONFIG_Z2_DONE_CYCLE<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 2 | 3 | 8 | 1 | 17
INPUTS | 13 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE_CYCLE<0>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<6>  | A<3>  | A<1>  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 5 | 3 | 8 | 1 | 17 | 4 | 17 | 5 | 12 | 13 | 3
INPUTP | 8 | 152 | 158 | 97 | 91 | 98 | 99 | 107 | 263
EQ | 5 | 
   AUTO_CONFIG_Z2_DONE_CYCLE<0>.T = !AS & !AUTO_CONFIG_Z2_DONE<0> & 
	!AUTO_CONFIG_Z2_DONE_CYCLE<0> & AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & 
	A<3> & !A<1> & !$OpTx$FX_DC$46;
   AUTO_CONFIG_Z2_DONE_CYCLE<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE_CYCLE<0>.AR = !RESET;

MACROCELL | 1 | 15 | AUTO_CONFIG_Z2_DONE_CYCLE<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 2 | 3 | 9 | 1 | 15
INPUTS | 14 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTO_CONFIG_Z2_DONE_CYCLE<1>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<6>  | A<3>  | A<1>  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 6 | 3 | 8 | 3 | 9 | 1 | 15 | 4 | 17 | 5 | 12 | 13 | 3
INPUTP | 8 | 152 | 158 | 97 | 91 | 98 | 99 | 107 | 263
EQ | 6 | 
   AUTO_CONFIG_Z2_DONE_CYCLE<1>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	!AUTO_CONFIG_Z2_DONE<1> & !AUTO_CONFIG_Z2_DONE_CYCLE<1> & 
	AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & A<3> & !A<1> & 
	!$OpTx$FX_DC$46;
   AUTO_CONFIG_Z2_DONE_CYCLE<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE_CYCLE<1>.AR = !RESET;

MACROCELL | 1 | 12 | AUTO_CONFIG_Z2_DONE_CYCLE<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 2 | 8 | 17 | 1 | 12
INPUTS | 15 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTO_CONFIG_Z2_DONE<2>  | AUTO_CONFIG_Z2_DONE_CYCLE<2>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<6>  | A<3>  | A<1>  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 7 | 3 | 8 | 3 | 9 | 8 | 17 | 1 | 12 | 4 | 17 | 5 | 12 | 13 | 3
INPUTP | 8 | 152 | 158 | 97 | 91 | 98 | 99 | 107 | 263
EQ | 6 | 
   AUTO_CONFIG_Z2_DONE_CYCLE<2>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	AUTO_CONFIG_Z2_DONE<1> & !AUTO_CONFIG_Z2_DONE<2> & 
	!AUTO_CONFIG_Z2_DONE_CYCLE<2> & AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & 
	A<3> & !A<1> & !$OpTx$FX_DC$46;
   AUTO_CONFIG_Z2_DONE_CYCLE<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   AUTO_CONFIG_Z2_DONE_CYCLE<2>.AR = !RESET;

MACROCELL | 6 | 17 | CP_BASEADR<0>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 17 | 4 | 3
INPUTS | 5 | D<8>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<0>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 17 | 13 | 3
INPUTP | 2 | 32 | 263
EQ | 4 | 
   CP_BASEADR<0>.D = D<8>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<0> & !$OpTx$FX_DC$74;
   CP_BASEADR<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<0>.AP = !RESET;

MACROCELL | 6 | 16 | CP_BASEADR<1>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 16 | 4 | 3
INPUTS | 5 | D<9>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<1>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 16 | 13 | 3
INPUTP | 2 | 73 | 263
EQ | 4 | 
   CP_BASEADR<1>.D = D<9>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<1> & !$OpTx$FX_DC$74;
   CP_BASEADR<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<1>.AP = !RESET;

MACROCELL | 6 | 15 | CP_BASEADR<2>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 15 | 4 | 2
INPUTS | 5 | D<10>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<2>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 15 | 13 | 3
INPUTP | 2 | 74 | 263
EQ | 4 | 
   CP_BASEADR<2>.D = D<10>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<2> & !$OpTx$FX_DC$74;
   CP_BASEADR<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<2>.AP = !RESET;

MACROCELL | 6 | 14 | CP_BASEADR<3>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 14 | 4 | 2
INPUTS | 5 | D<11>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<3>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 14 | 13 | 3
INPUTP | 2 | 77 | 263
EQ | 4 | 
   CP_BASEADR<3>.D = D<11>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<3> & !$OpTx$FX_DC$74;
   CP_BASEADR<3>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<3>.AP = !RESET;

MACROCELL | 6 | 13 | CP_BASEADR<4>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 6 | 13 | 4 | 0 | 4 | 2
INPUTS | 5 | D<12>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<4>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 13 | 13 | 3
INPUTP | 2 | 78 | 263
EQ | 4 | 
   CP_BASEADR<4>.D = D<12>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<4> & !$OpTx$FX_DC$74;
   CP_BASEADR<4>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<4>.AP = !RESET;

MACROCELL | 6 | 12 | CP_BASEADR<5>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 12 | 4 | 0
INPUTS | 5 | D<13>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<5>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 12 | 13 | 3
INPUTP | 2 | 80 | 263
EQ | 4 | 
   CP_BASEADR<5>.D = D<13>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<5> & !$OpTx$FX_DC$74;
   CP_BASEADR<5>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<5>.AP = !RESET;

MACROCELL | 6 | 10 | CP_BASEADR<6>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 10 | 4 | 0
INPUTS | 5 | D<14>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<6>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 10 | 13 | 3
INPUTP | 2 | 81 | 263
EQ | 4 | 
   CP_BASEADR<6>.D = D<14>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<6> & !$OpTx$FX_DC$74;
   CP_BASEADR<6>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<6>.AP = !RESET;

MACROCELL | 6 | 9 | CP_BASEADR<7>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 9 | 4 | 1
INPUTS | 5 | D<15>.PIN  | $OpTx$FX_DC$74  | CP_BASEADR<7>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 0 | 6 | 9 | 13 | 3
INPUTP | 2 | 89 | 263
EQ | 4 | 
   CP_BASEADR<7>.D = D<15>.PIN & $OpTx$FX_DC$74
	# CP_BASEADR<7> & !$OpTx$FX_DC$74;
   CP_BASEADR<7>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   CP_BASEADR<7>.AP = !RESET;

MACROCELL | 6 | 8 | IDE_BASEADR<0>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 6 | 8 | 0 | 16 | 0 | 0
INPUTS | 5 | D<8>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<0>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 6 | 8 | 13 | 3
INPUTP | 2 | 32 | 263
EQ | 4 | 
   IDE_BASEADR<0>.D = D<8>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<0> & !$OpTx$FX_DC$73;
   IDE_BASEADR<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<0>.AP = !RESET;

MACROCELL | 6 | 7 | IDE_BASEADR<1>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 7 | 0 | 16
INPUTS | 5 | D<9>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<1>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 6 | 7 | 13 | 3
INPUTP | 2 | 73 | 263
EQ | 4 | 
   IDE_BASEADR<1>.D = D<9>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<1> & !$OpTx$FX_DC$73;
   IDE_BASEADR<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<1>.AP = !RESET;

MACROCELL | 6 | 6 | IDE_BASEADR<2>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 6 | 0 | 16
INPUTS | 5 | D<10>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<2>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 6 | 6 | 13 | 3
INPUTP | 2 | 74 | 263
EQ | 4 | 
   IDE_BASEADR<2>.D = D<10>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<2> & !$OpTx$FX_DC$73;
   IDE_BASEADR<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<2>.AP = !RESET;

MACROCELL | 6 | 5 | IDE_BASEADR<3>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 5 | 0 | 17
INPUTS | 5 | D<11>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<3>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 6 | 5 | 13 | 3
INPUTP | 2 | 77 | 263
EQ | 4 | 
   IDE_BASEADR<3>.D = D<11>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<3> & !$OpTx$FX_DC$73;
   IDE_BASEADR<3>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<3>.AP = !RESET;

MACROCELL | 6 | 3 | IDE_BASEADR<4>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 6 | 3 | 0 | 1
INPUTS | 5 | D<12>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<4>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 6 | 3 | 13 | 3
INPUTP | 2 | 78 | 263
EQ | 4 | 
   IDE_BASEADR<4>.D = D<12>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<4> & !$OpTx$FX_DC$73;
   IDE_BASEADR<4>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<4>.AP = !RESET;

MACROCELL | 12 | 17 | IDE_BASEADR<5>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 17 | 0 | 1
INPUTS | 5 | D<13>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<5>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 12 | 17 | 13 | 3
INPUTP | 2 | 80 | 263
EQ | 4 | 
   IDE_BASEADR<5>.D = D<13>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<5> & !$OpTx$FX_DC$73;
   IDE_BASEADR<5>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<5>.AP = !RESET;

MACROCELL | 12 | 16 | IDE_BASEADR<6>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 16 | 0 | 0
INPUTS | 5 | D<14>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<6>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 12 | 16 | 13 | 3
INPUTP | 2 | 81 | 263
EQ | 4 | 
   IDE_BASEADR<6>.D = D<14>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<6> & !$OpTx$FX_DC$73;
   IDE_BASEADR<6>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<6>.AP = !RESET;

MACROCELL | 12 | 15 | IDE_BASEADR<7>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 15 | 0 | 0
INPUTS | 5 | D<15>.PIN  | $OpTx$FX_DC$73  | IDE_BASEADR<7>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 1 | 3 | 12 | 15 | 13 | 3
INPUTP | 2 | 89 | 263
EQ | 4 | 
   IDE_BASEADR<7>.D = D<15>.PIN & $OpTx$FX_DC$73
	# IDE_BASEADR<7> & !$OpTx$FX_DC$73;
   IDE_BASEADR<7>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_BASEADR<7>.AP = !RESET;

MACROCELL | 12 | 14 | LAN_BASEADR<0>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 14 | 5 | 1
INPUTS | 5 | LAN_BASEADR<0>  | $OpTx$FX_DC$72  | D<8>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 14 | 1 | 6 | 13 | 3
INPUTP | 2 | 32 | 263
EQ | 4 | 
   LAN_BASEADR<0>.D = D<8>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<0> & !$OpTx$FX_DC$72;
   LAN_BASEADR<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<0>.AP = !RESET;

MACROCELL | 7 | 17 | LAN_BASEADR<10>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 17 | 5 | 15
INPUTS | 5 | LAN_BASEADR<10>  | $OpTx$FX_DC$77  | D<10>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 17 | 3 | 17 | 13 | 3
INPUTP | 2 | 74 | 263
EQ | 4 | 
   LAN_BASEADR<10>.D = D<10>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<10> & !$OpTx$FX_DC$77;
   LAN_BASEADR<10>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<10>.AP = !RESET;

MACROCELL | 7 | 16 | LAN_BASEADR<11>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 7 | 16 | 5 | 16 | 5 | 15
INPUTS | 5 | LAN_BASEADR<11>  | $OpTx$FX_DC$77  | D<11>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 16 | 3 | 17 | 13 | 3
INPUTP | 2 | 77 | 263
EQ | 4 | 
   LAN_BASEADR<11>.D = D<11>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<11> & !$OpTx$FX_DC$77;
   LAN_BASEADR<11>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<11>.AP = !RESET;

MACROCELL | 12 | 12 | LAN_BASEADR<12>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 12 | 12 | 5 | 14 | 5 | 17
INPUTS | 5 | LAN_BASEADR<12>  | $OpTx$FX_DC$77  | D<12>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 12 | 3 | 17 | 13 | 3
INPUTP | 2 | 78 | 263
EQ | 4 | 
   LAN_BASEADR<12>.D = D<12>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<12> & !$OpTx$FX_DC$77;
   LAN_BASEADR<12>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<12>.AP = !RESET;

MACROCELL | 7 | 15 | LAN_BASEADR<13>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 15 | 5 | 17
INPUTS | 5 | LAN_BASEADR<13>  | $OpTx$FX_DC$77  | D<13>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 15 | 3 | 17 | 13 | 3
INPUTP | 2 | 80 | 263
EQ | 4 | 
   LAN_BASEADR<13>.D = D<13>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<13> & !$OpTx$FX_DC$77;
   LAN_BASEADR<13>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<13>.AP = !RESET;

MACROCELL | 7 | 14 | LAN_BASEADR<14>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 14 | 5 | 17
INPUTS | 5 | LAN_BASEADR<14>  | $OpTx$FX_DC$77  | D<14>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 14 | 3 | 17 | 13 | 3
INPUTP | 2 | 81 | 263
EQ | 4 | 
   LAN_BASEADR<14>.D = D<14>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<14> & !$OpTx$FX_DC$77;
   LAN_BASEADR<14>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<14>.AP = !RESET;

MACROCELL | 7 | 13 | LAN_BASEADR<15>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 13 | 5 | 15
INPUTS | 5 | LAN_BASEADR<15>  | $OpTx$FX_DC$77  | D<15>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 13 | 3 | 17 | 13 | 3
INPUTP | 2 | 89 | 263
EQ | 4 | 
   LAN_BASEADR<15>.D = D<15>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<15> & !$OpTx$FX_DC$77;
   LAN_BASEADR<15>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<15>.AP = !RESET;

MACROCELL | 12 | 11 | LAN_BASEADR<1>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 12 | 11 | 5 | 13 | 5 | 1
INPUTS | 5 | LAN_BASEADR<1>  | $OpTx$FX_DC$72  | D<9>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 11 | 1 | 6 | 13 | 3
INPUTP | 2 | 73 | 263
EQ | 4 | 
   LAN_BASEADR<1>.D = D<9>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<1> & !$OpTx$FX_DC$72;
   LAN_BASEADR<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<1>.AP = !RESET;

MACROCELL | 7 | 12 | LAN_BASEADR<2>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 12 | 5 | 13
INPUTS | 5 | LAN_BASEADR<2>  | $OpTx$FX_DC$72  | D<10>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 12 | 1 | 6 | 13 | 3
INPUTP | 2 | 74 | 263
EQ | 4 | 
   LAN_BASEADR<2>.D = D<10>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<2> & !$OpTx$FX_DC$72;
   LAN_BASEADR<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<2>.AP = !RESET;

MACROCELL | 7 | 11 | LAN_BASEADR<3>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 7 | 11 | 5 | 13 | 5 | 0
INPUTS | 5 | LAN_BASEADR<3>  | $OpTx$FX_DC$72  | D<11>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 11 | 1 | 6 | 13 | 3
INPUTP | 2 | 77 | 263
EQ | 4 | 
   LAN_BASEADR<3>.D = D<11>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<3> & !$OpTx$FX_DC$72;
   LAN_BASEADR<3>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<3>.AP = !RESET;

MACROCELL | 7 | 10 | LAN_BASEADR<4>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 10 | 5 | 0
INPUTS | 5 | LAN_BASEADR<4>  | $OpTx$FX_DC$72  | D<12>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 10 | 1 | 6 | 13 | 3
INPUTP | 2 | 78 | 263
EQ | 4 | 
   LAN_BASEADR<4>.D = D<12>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<4> & !$OpTx$FX_DC$72;
   LAN_BASEADR<4>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<4>.AP = !RESET;

MACROCELL | 7 | 8 | LAN_BASEADR<5>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 8 | 5 | 0
INPUTS | 5 | LAN_BASEADR<5>  | $OpTx$FX_DC$72  | D<13>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 8 | 1 | 6 | 13 | 3
INPUTP | 2 | 80 | 263
EQ | 4 | 
   LAN_BASEADR<5>.D = D<13>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<5> & !$OpTx$FX_DC$72;
   LAN_BASEADR<5>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<5>.AP = !RESET;

MACROCELL | 7 | 6 | LAN_BASEADR<6>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 7 | 6 | 5 | 14
INPUTS | 5 | LAN_BASEADR<6>  | $OpTx$FX_DC$72  | D<14>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 7 | 6 | 1 | 6 | 13 | 3
INPUTP | 2 | 81 | 263
EQ | 4 | 
   LAN_BASEADR<6>.D = D<14>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<6> & !$OpTx$FX_DC$72;
   LAN_BASEADR<6>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<6>.AP = !RESET;

MACROCELL | 12 | 10 | LAN_BASEADR<7>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 10 | 5 | 14
INPUTS | 5 | LAN_BASEADR<7>  | $OpTx$FX_DC$72  | D<15>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 10 | 1 | 6 | 13 | 3
INPUTP | 2 | 89 | 263
EQ | 4 | 
   LAN_BASEADR<7>.D = D<15>.PIN & $OpTx$FX_DC$72
	# LAN_BASEADR<7> & !$OpTx$FX_DC$72;
   LAN_BASEADR<7>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<7>.AP = !RESET;

MACROCELL | 12 | 9 | LAN_BASEADR<8>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 9 | 5 | 16
INPUTS | 5 | LAN_BASEADR<8>  | $OpTx$FX_DC$77  | D<8>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 9 | 3 | 17 | 13 | 3
INPUTP | 2 | 32 | 263
EQ | 4 | 
   LAN_BASEADR<8>.D = D<8>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<8> & !$OpTx$FX_DC$77;
   LAN_BASEADR<8>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<8>.AP = !RESET;

MACROCELL | 12 | 8 | LAN_BASEADR<9>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 12 | 8 | 5 | 16
INPUTS | 5 | LAN_BASEADR<9>  | $OpTx$FX_DC$77  | D<9>.PIN  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 8 | 3 | 17 | 13 | 3
INPUTP | 2 | 73 | 263
EQ | 4 | 
   LAN_BASEADR<9>.D = D<9>.PIN & $OpTx$FX_DC$77
	# LAN_BASEADR<9> & !$OpTx$FX_DC$77;
   LAN_BASEADR<9>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   LAN_BASEADR<9>.AP = !RESET;

MACROCELL | 8 | 14 | LAN_IRQ_OUT
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 8 | 14 | 2 | 13
INPUTS | 4 | LAN_IRQ_OUT  | LAN_IRQ_D0  | LAN_INT  | RESET
INPUTMC | 2 | 8 | 14 | 8 | 2
INPUTP | 2 | 201 | 263
EQ | 4 | 
   LAN_IRQ_OUT.D = LAN_INT
	# LAN_IRQ_OUT & !LAN_IRQ_D0;
   LAN_IRQ_OUT.CLK = CLK_EXT;	// GCK
   LAN_IRQ_OUT.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 17 | Z3_DATA<16>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 3 | 1 | 15 | 16
INPUTS | 9 | LAN_SM_FSM_FFd3  | BUF_LAN_READY  | Z3_ADR<13>  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | RW  | Z3_DATA<26>.EXP
INPUTMC | 8 | 10 | 15 | 14 | 6 | 13 | 16 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 15 | 0
INPUTP | 1 | 158
EXPORTS | 1 | 15 | 16
IMPORTS | 1 | 15 | 0
EQ | 13 | 
   Z3_DATA<16>.D = ;Imported pterms FB16_1
	  DQ_SWAP & DQ<8>.PIN
	# !DQ_SWAP & DQ<0>.PIN;
   Z3_DATA<16>.CLK = CLK_EXT;	// GCK
   Z3_DATA<16>.AP = LAN_SM_RST;
   Z3_DATA<16>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
    Z3_DATA<16>.EXP  =  !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	LAN_SM_FSM_FFd3 & BUF_LAN_READY
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & !RW
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 8 | Z3_DATA<17>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 14
INPUTS | 7 | DQ_SWAP  | DQ<9>.PIN  | DQ<1>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 209 | 216
EQ | 6 | 
   Z3_DATA<17>.D = DQ_SWAP & DQ<9>.PIN
	# !DQ_SWAP & DQ<1>.PIN;
   Z3_DATA<17>.CLK = CLK_EXT;	// GCK
   Z3_DATA<17>.AP = LAN_SM_RST;
   Z3_DATA<17>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 6 | Z3_DATA<18>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 9
INPUTS | 7 | DQ_SWAP  | DQ<2>.PIN  | DQ<10>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 220 | 234
EQ | 6 | 
   Z3_DATA<18>.D = DQ_SWAP & DQ<10>.PIN
	# !DQ_SWAP & DQ<2>.PIN;
   Z3_DATA<18>.CLK = CLK_EXT;	// GCK
   Z3_DATA<18>.AP = LAN_SM_RST;
   Z3_DATA<18>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 14 | Z3_DATA<19>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 11
INPUTS | 7 | DQ_SWAP  | DQ<3>.PIN  | DQ<11>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 219 | 207
EQ | 6 | 
   Z3_DATA<19>.D = DQ_SWAP & DQ<11>.PIN
	# !DQ_SWAP & DQ<3>.PIN;
   Z3_DATA<19>.CLK = CLK_EXT;	// GCK
   Z3_DATA<19>.AP = LAN_SM_RST;
   Z3_DATA<19>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 12 | Z3_DATA<20>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 5
INPUTS | 7 | DQ_SWAP  | DQ<4>.PIN  | DQ<12>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 225 | 235
EQ | 6 | 
   Z3_DATA<20>.D = DQ_SWAP & DQ<12>.PIN
	# !DQ_SWAP & DQ<4>.PIN;
   Z3_DATA<20>.CLK = CLK_EXT;	// GCK
   Z3_DATA<20>.AP = LAN_SM_RST;
   Z3_DATA<20>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 8 | Z3_DATA<21>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 4
INPUTS | 7 | DQ_SWAP  | DQ<5>.PIN  | DQ<13>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 221 | 204
EQ | 6 | 
   Z3_DATA<21>.D = DQ_SWAP & DQ<13>.PIN
	# !DQ_SWAP & DQ<5>.PIN;
   Z3_DATA<21>.CLK = CLK_EXT;	// GCK
   Z3_DATA<21>.AP = LAN_SM_RST;
   Z3_DATA<21>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 7 | Z3_DATA<22>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 9
INPUTS | 7 | DQ_SWAP  | DQ<6>.PIN  | DQ<14>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 227 | 236
EQ | 6 | 
   Z3_DATA<22>.D = DQ_SWAP & DQ<14>.PIN
	# !DQ_SWAP & DQ<6>.PIN;
   Z3_DATA<22>.CLK = CLK_EXT;	// GCK
   Z3_DATA<22>.AP = LAN_SM_RST;
   Z3_DATA<22>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 6 | Z3_DATA<23>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 13
INPUTS | 7 | DQ_SWAP  | DQ<7>.PIN  | DQ<15>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 226 | 202
EQ | 6 | 
   Z3_DATA<23>.D = DQ_SWAP & DQ<15>.PIN
	# !DQ_SWAP & DQ<7>.PIN;
   Z3_DATA<23>.CLK = CLK_EXT;	// GCK
   Z3_DATA<23>.AP = LAN_SM_RST;
   Z3_DATA<23>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 4 | Z3_DATA<24>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 16
INPUTS | 7 | DQ_SWAP  | DQ<8>.PIN  | DQ<0>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 231 | 217
EQ | 6 | 
   Z3_DATA<24>.D = DQ_SWAP & DQ<0>.PIN
	# !DQ_SWAP & DQ<8>.PIN;
   Z3_DATA<24>.CLK = CLK_EXT;	// GCK
   Z3_DATA<24>.AP = LAN_SM_RST;
   Z3_DATA<24>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 3 | Z3_DATA<25>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 4 | 11 | 15 | 2
INPUTS | 8 | DQ_SWAP  | DQ<9>.PIN  | DQ<1>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | DQ<11>.PIN
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 3 | 209 | 216 | 207
EXPORTS | 1 | 15 | 2
EQ | 7 | 
   Z3_DATA<25>.D = DQ_SWAP & DQ<1>.PIN
	# !DQ_SWAP & DQ<9>.PIN;
   Z3_DATA<25>.CLK = CLK_EXT;	// GCK
   Z3_DATA<25>.AP = LAN_SM_RST;
   Z3_DATA<25>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
    Z3_DATA<25>.EXP  =  !DQ_SWAP & DQ<11>.PIN
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 0 | Z3_DATA<26>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 4 | 13 | 15 | 17
INPUTS | 9 | DQ_SWAP  | DQ<2>.PIN  | DQ<8>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | DQ<0>.PIN  | Z3_DATA<12>.EXP
INPUTMC | 6 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 15 | 1
INPUTP | 3 | 220 | 231 | 217
EXPORTS | 1 | 15 | 17
IMPORTS | 1 | 15 | 1
EQ | 9 | 
   Z3_DATA<26>.D = DQ_SWAP & DQ<2>.PIN
;Imported pterms FB16_2
	# !DQ_SWAP & DQ<10>.PIN;
   Z3_DATA<26>.CLK = CLK_EXT;	// GCK
   Z3_DATA<26>.AP = LAN_SM_RST;
   Z3_DATA<26>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
    Z3_DATA<26>.EXP  =  DQ_SWAP & DQ<8>.PIN
	# !DQ_SWAP & DQ<0>.PIN
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 5 | Z3_DATA<27>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 14
INPUTS | 7 | DQ_SWAP  | DQ<3>.PIN  | DQ<11>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 219 | 207
EQ | 6 | 
   Z3_DATA<27>.D = DQ_SWAP & DQ<3>.PIN
	# !DQ_SWAP & DQ<11>.PIN;
   Z3_DATA<27>.CLK = CLK_EXT;	// GCK
   Z3_DATA<27>.AP = LAN_SM_RST;
   Z3_DATA<27>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 3 | Z3_DATA<28>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 16
INPUTS | 7 | DQ_SWAP  | DQ<4>.PIN  | DQ<12>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 225 | 235
EQ | 6 | 
   Z3_DATA<28>.D = DQ_SWAP & DQ<4>.PIN
	# !DQ_SWAP & DQ<12>.PIN;
   Z3_DATA<28>.CLK = CLK_EXT;	// GCK
   Z3_DATA<28>.AP = LAN_SM_RST;
   Z3_DATA<28>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 1 | Z3_DATA<29>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 2
INPUTS | 7 | DQ_SWAP  | DQ<5>.PIN  | DQ<13>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 221 | 204
EQ | 6 | 
   Z3_DATA<29>.D = DQ_SWAP & DQ<5>.PIN
	# !DQ_SWAP & DQ<13>.PIN;
   Z3_DATA<29>.CLK = CLK_EXT;	// GCK
   Z3_DATA<29>.AP = LAN_SM_RST;
   Z3_DATA<29>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 0 | Z3_DATA<30>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 7 | DQ_SWAP  | DQ<6>.PIN  | DQ<14>.PIN  | LAN_SM_RST  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 5 | 0 | 15 | 8 | 0 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 2 | 227 | 236
EQ | 6 | 
   Z3_DATA<30>.D = DQ_SWAP & DQ<6>.PIN
	# !DQ_SWAP & DQ<14>.PIN;
   Z3_DATA<30>.CLK = CLK_EXT;	// GCK
   Z3_DATA<30>.AP = LAN_SM_RST;
   Z3_DATA<30>.CE = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 9 | 16 | DQ_10_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 15
INPUTS | 13 | D<10>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<8>  | DQ_DATA<10>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46
INPUTMC | 11 | 9 | 8 | 8 | 3 | 9 | 15 | 4 | 8 | 14 | 8 | 13 | 4 | 0 | 15 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12
INPUTP | 2 | 74 | 263
EXPORTS | 1 | 9 | 15
EQ | 7 | 
   DQ<10> = !RESET & LAN_D_INIT<8>
	# D<10>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<10> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<10>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;
    DQ_10_IOBUFE.EXP  =  D<10>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46

MACROCELL | 11 | 9 | DQ_11_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 8 | D<11>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<8>  | DQ_DATA<11>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 6 | 9 | 8 | 8 | 3 | 15 | 14 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 77 | 263
EQ | 5 | 
   DQ<11> = !RESET & LAN_D_INIT<8>
	# D<11>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<11> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<11>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 1 | DQ_1_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 8 | D<1>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<1>  | DQ_DATA<1>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 6 | 9 | 8 | 8 | 4 | 11 | 16 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 30 | 263
EQ | 5 | 
   DQ<1> = !RESET & LAN_D_INIT<1>
	# D<1>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<1> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<1>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 9 | DQ_4_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 8 | D<4>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<1>  | DQ_DATA<4>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 6 | 9 | 8 | 8 | 4 | 14 | 3 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 38 | 263
EQ | 5 | 
   DQ<4> = !RESET & LAN_D_INIT<1>
	# D<4>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<4> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<4>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 13 | DQ_8_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 14
INPUTS | 14 | D<8>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<8>  | DQ_DATA<8>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<2>.PIN  | $OpTx$FX_DC$46
INPUTMC | 11 | 9 | 8 | 8 | 3 | 9 | 12 | 4 | 8 | 14 | 8 | 13 | 4 | 0 | 15 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12
INPUTP | 3 | 32 | 263 | 71
EXPORTS | 1 | 9 | 14
EQ | 7 | 
   DQ<8> = !RESET & LAN_D_INIT<8>
	# D<8>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<8> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<8>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;
    DQ_8_IOBUFE.EXP  =  !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<2>.PIN & !$OpTx$FX_DC$46

MACROCELL | 11 | 11 | DQ_9_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 11 | 12
INPUTS | 12 | D<9>.PIN  | $OpTx$FX_DC$78  | RESET  | LAN_D_INIT<1>  | DQ_DATA<9>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST  | UDS  | DS1  | A<23>.PIN  | $OpTx$FX_DC$106
INPUTMC | 7 | 9 | 8 | 8 | 4 | 11 | 13 | 4 | 8 | 14 | 8 | 13 | 4 | 14 | 9
INPUTP | 5 | 73 | 263 | 155 | 148 | 161
EXPORTS | 1 | 11 | 12
EQ | 6 | 
   DQ<9> = !RESET & LAN_D_INIT<1>
	# D<9>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<9> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<9>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;
    DQ_9_IOBUFE.EXP  =  UDS & !DS1 & A<23>.PIN & $OpTx$FX_DC$106

MACROCELL | 3 | 1 | D_0_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 3 | 2
INPUTS | 12 | DQ<0>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<16>  | D_9_IOBUFE/D_9_IOBUFE_TRST  | AUTO_CONFIG_Z2_DONE<0>  | A<4>  | A<5>  | A<3>  | A<1>  | $OpTx$FX_DC$95  | A<2>
INPUTMC | 6 | 4 | 8 | 4 | 10 | 15 | 17 | 4 | 15 | 3 | 8 | 13 | 1
INPUTP | 6 | 217 | 97 | 91 | 99 | 107 | 101
EXPORTS | 1 | 3 | 2
EQ | 9 | 
   !D<0> = !Z3_DATA<16> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<0>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<0>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
    D_0_IOBUFE.EXP  =  !AUTO_CONFIG_Z2_DONE<0> & !A<4> & !A<5> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95
	# !AUTO_CONFIG_Z2_DONE<0> & !A<5> & A<2> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95

MACROCELL | 4 | 13 | D_10_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<2>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<26>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 15 | 0 | 4 | 15
INPUTP | 1 | 220
EQ | 5 | 
   !D<10> = !Z3_DATA<26> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<2>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<10>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 4 | 14 | D_11_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<3>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<27>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 10 | 5 | 4 | 15
INPUTP | 1 | 219
EQ | 5 | 
   !D<11> = !Z3_DATA<27> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<3>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<11>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 4 | 16 | D_12_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 9 | DQ<4>.PIN  | $OpTx$FX_DC$86  | Z3_DATA<28>  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS  | AUTOCONFIG_Z2_ACCESS  | D_Z2_OUT<0>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 6 | 4 | 12 | 10 | 3 | 13 | 0 | 4 | 17 | 6 | 1 | 4 | 15
INPUTP | 3 | 225 | 158 | 152
EQ | 6 | 
   D<12> = DQ<4>.PIN & !$OpTx$FX_DC$86
	# Z3_DATA<28> & RW & 
	ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & D_Z2_OUT<0> & RW & 
	!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   D<12>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 6 | 2 | D_13_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 9 | DQ<5>.PIN  | $OpTx$FX_DC$86  | Z3_DATA<29>  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS  | AUTOCONFIG_Z2_ACCESS  | D_Z2_OUT<1>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 6 | 4 | 12 | 10 | 1 | 13 | 0 | 4 | 17 | 3 | 0 | 4 | 15
INPUTP | 3 | 221 | 158 | 152
EQ | 6 | 
   D<13> = DQ<5>.PIN & !$OpTx$FX_DC$86
	# Z3_DATA<29> & RW & 
	ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & D_Z2_OUT<1> & RW & 
	!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   D<13>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 6 | 4 | D_14_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 9 | DQ<6>.PIN  | $OpTx$FX_DC$86  | Z3_DATA<30>  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS  | AUTOCONFIG_Z2_ACCESS  | D_Z2_OUT<2>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 6 | 4 | 12 | 10 | 0 | 13 | 0 | 4 | 17 | 13 | 17 | 4 | 15
INPUTP | 3 | 227 | 158 | 152
EQ | 6 | 
   D<14> = DQ<6>.PIN & !$OpTx$FX_DC$86
	# Z3_DATA<30> & RW & 
	ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & D_Z2_OUT<2> & RW & 
	!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   D<14>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 6 | 11 | D_15_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 9 | DQ<7>.PIN  | $OpTx$FX_DC$86  | Z3_DATA<31>  | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS  | AUTOCONFIG_Z2_ACCESS  | D_Z2_OUT<3>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 6 | 4 | 12 | 10 | 17 | 13 | 0 | 4 | 17 | 12 | 6 | 4 | 15
INPUTP | 3 | 226 | 158 | 152
EQ | 6 | 
   D<15> = DQ<7>.PIN & !$OpTx$FX_DC$86
	# Z3_DATA<31> & RW & 
	ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & D_Z2_OUT<3> & RW & 
	!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
   D<15>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 1 | 14 | D_1_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<1>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<17>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 15 | 8 | 4 | 15
INPUTP | 1 | 216
EQ | 5 | 
   !D<1> = !Z3_DATA<17> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<1>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<1>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 4 | 9 | D_2_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<2>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<18>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 15 | 6 | 4 | 15
INPUTP | 1 | 220
EQ | 5 | 
   !D<2> = !Z3_DATA<18> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<2>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<2>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 1 | 11 | D_3_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<3>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<19>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 10 | 14 | 4 | 15
INPUTP | 1 | 219
EQ | 5 | 
   !D<3> = !Z3_DATA<19> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<3>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<3>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 0 | 5 | D_4_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | Z3_DATA<20>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | DQ<4>.PIN  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 10 | 12 | 4 | 8 | 4 | 10 | 4 | 15
INPUTP | 1 | 225
EQ | 5 | 
   !D<4> = !Z3_DATA<20> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<4>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<4>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 0 | 4 | D_5_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | Z3_DATA<21>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | DQ<5>.PIN  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 10 | 8 | 4 | 8 | 4 | 10 | 4 | 15
INPUTP | 1 | 221
EQ | 5 | 
   !D<5> = !Z3_DATA<21> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<5>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<5>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 1 | 9 | D_6_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | Z3_DATA<22>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | DQ<6>.PIN  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 10 | 7 | 4 | 8 | 4 | 10 | 4 | 15
INPUTP | 1 | 227
EQ | 5 | 
   !D<6> = !Z3_DATA<22> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<6>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<6>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 1 | 13 | D_7_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | Z3_DATA<23>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | DQ<7>.PIN  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 10 | 6 | 4 | 8 | 4 | 10 | 4 | 15
INPUTP | 1 | 226
EQ | 5 | 
   !D<7> = !Z3_DATA<23> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<7>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<7>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 1 | 16 | D_8_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<0>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<24>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 15 | 4 | 4 | 15
INPUTP | 1 | 217
EQ | 5 | 
   !D<8> = !Z3_DATA<24> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<0>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<8>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 4 | 11 | D_9_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 5 | DQ<1>.PIN  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_SC$85  | Z3_DATA<25>  | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 4 | 8 | 4 | 10 | 15 | 3 | 4 | 15
INPUTP | 1 | 216
EQ | 5 | 
   !D<9> = !Z3_DATA<25> & Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85
	# !DQ<1>.PIN & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_SC$85;
   D<9>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;

MACROCELL | 9 | 2 | DQ_0_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<0>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<0>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 9 | 17 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 4 | 263
EQ | 4 | 
   DQ<0> = D<0>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<0> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<0>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 7 | 1 | DQ_12_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<12>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<12>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 14 | 0 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 78 | 263
EQ | 4 | 
   DQ<12> = D<12>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<12> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<12>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 11 | 7 | DQ_13_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<13>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<13>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 14 | 1 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 80 | 263
EQ | 4 | 
   DQ<13> = D<13>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<13> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<13>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 7 | 2 | DQ_14_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<14>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<14>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 14 | 2 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 81 | 263
EQ | 4 | 
   DQ<14> = D<14>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<14> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<14>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 11 | 4 | DQ_15_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<15>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<15>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 11 | 17 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 89 | 263
EQ | 4 | 
   DQ<15> = D<15>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<15> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<15>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 5 | DQ_2_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<2>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<2>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 9 | 14 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 71 | 263
EQ | 4 | 
   DQ<2> = D<2>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<2> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<2>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 4 | DQ_3_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<3>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<3>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 11 | 15 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 28 | 263
EQ | 4 | 
   DQ<3> = D<3>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<3> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<3>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 7 | DQ_5_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<5>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<5>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 14 | 4 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 37 | 263
EQ | 4 | 
   DQ<5> = D<5>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<5> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<5>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 9 | 11 | DQ_6_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 12
INPUTS | 13 | D<6>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<6>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST  | D<8>.PIN  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46
INPUTMC | 10 | 9 | 8 | 14 | 5 | 4 | 8 | 14 | 8 | 13 | 4 | 0 | 15 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12
INPUTP | 3 | 26 | 263 | 32
EXPORTS | 1 | 9 | 12
EQ | 6 | 
   DQ<6> = D<6>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<6> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<6>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;
    DQ_6_IOBUFE.EXP  =  D<8>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46

MACROCELL | 9 | 10 | DQ_7_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 7 | D<7>.PIN  | $OpTx$FX_DC$78  | RESET  | DQ_DATA<7>  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59  | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
INPUTMC | 5 | 9 | 8 | 11 | 14 | 4 | 8 | 14 | 8 | 13 | 4
INPUTP | 2 | 29 | 263
EQ | 4 | 
   DQ<7> = D<7>.PIN & !$OpTx$FX_DC$78
	# RESET & DQ_DATA<7> & !Z3_DATA<6>/Z3_DATA<6>_TRST & 
	!$OpTx$FX_DC$59;
   DQ<7>.OE = DQ_8_IOBUFE/DQ_8_IOBUFE_TRST;

MACROCELL | 0 | 15 | DQ_SWAP
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 57 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 9 | 15 | 7 | 15 | 13 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 9 | 17 | 9 | 15 | 15 | 14 | 14 | 0 | 14 | 1 | 14 | 2 | 11 | 17 | 11 | 16 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 4 | 14 | 5 | 11 | 14 | 9 | 12 | 11 | 13 | 10 | 16 | 9 | 0 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 0 | 11 | 12 | 14 | 6 | 14 | 17 | 0 | 16
INPUTS | 9 | Z3  | SHUT_UP_Z2<0>  | A<13>.PIN  | A<14>.PIN  | Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2  | FCS  | RESET  | AS  | IDE_R_S
INPUTMC | 3 | 12 | 4 | 5 | 16 | 3 | 12
INPUTP | 6 | 151 | 123 | 125 | 147 | 263 | 152
EXPORTS | 1 | 0 | 16
EQ | 5 | 
   !DQ_SWAP.D = Z3 & !SHUT_UP_Z2<0> & A<13>.PIN & A<14>.PIN & 
	!Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2;
   DQ_SWAP.CLK = !FCS;
   DQ_SWAP.AP = !RESET;
    DQ_SWAP.EXP  =  !AS & !IDE_R_S

MACROCELL | 15 | 12 | LAN_SM_FSM_FFd2
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 68 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 17 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 9 | 17 | 9 | 15 | 14 | 17 | 11 | 17 | 14 | 0 | 14 | 2 | 11 | 16 | 11 | 13 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 1 | 14 | 4 | 11 | 14 | 9 | 12 | 11 | 12 | 10 | 17 | 15 | 11 | 14 | 7 | 11 | 0 | 15 | 13 | 14 | 6 | 9 | 3 | 9 | 6 | 14 | 9 | 9 | 0 | 9 | 11 | 9 | 13 | 9 | 16 | 10 | 16 | 11 | 1 | 14 | 5 | 15 | 14
INPUTS | 8 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | BUF_LAN_READY  | LAN_RD_S.EXP  | LAN_SM_RST
INPUTMC | 8 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 5 | 12 | 14 | 6 | 15 | 11 | 8 | 0
EXPORTS | 1 | 15 | 13
IMPORTS | 1 | 15 | 11
EQ | 16 | 
   !LAN_SM_FSM_FFd2.D = !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4
;Imported pterms FB16_12
	# !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd3 & 
	$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !Z3_ADR<13> & !$OpTx$FX_DC$46 & 
	$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & !$OpTx$FX_DC$46;
   LAN_SM_FSM_FFd2.CLK = CLK_EXT;	// GCK
   LAN_SM_FSM_FFd2.AR = LAN_SM_RST;
    LAN_SM_FSM_FFd2.EXP  =  LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!$OpTx$FX_DC$46 & !BUF_LAN_READY
	# !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 15 | LAN_SM_FSM_FFd4
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 68 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 17 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 9 | 17 | 9 | 15 | 14 | 17 | 11 | 17 | 14 | 0 | 14 | 2 | 11 | 16 | 11 | 13 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 1 | 14 | 4 | 11 | 14 | 9 | 12 | 11 | 12 | 10 | 17 | 15 | 11 | 14 | 7 | 10 | 16 | 15 | 13 | 14 | 6 | 9 | 3 | 9 | 6 | 14 | 9 | 9 | 0 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 0 | 11 | 1 | 14 | 5 | 15 | 14
INPUTS | 8 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | LAN_SM_FSM_FFd1  | $OpTx$FX_DC$49  | DQ_DATA<11>.EXP  | LAN_SM_RST  | LAN_SM_FSM_FFd1.EXP
INPUTMC | 8 | 15 | 12 | 15 | 15 | 10 | 15 | 15 | 16 | 2 | 17 | 15 | 14 | 8 | 0 | 15 | 16
IMPORTS | 2 | 15 | 14 | 15 | 16
EQ | 16 | 
   LAN_SM_FSM_FFd4.D = LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3
	# LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1
	# !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 & 
	!$OpTx$FX_DC$49
;Imported pterms FB16_15
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$49
;Imported pterms FB16_17
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13>;
   LAN_SM_FSM_FFd4.CLK = CLK_EXT;	// GCK
   LAN_SM_FSM_FFd4.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 16 | LAN_SM_FSM_FFd1
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 46 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 17 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 11 | 1 | 15 | 15 | 15 | 16 | 10 | 15 | 10 | 17 | 15 | 11 | 14 | 7 | 11 | 0 | 15 | 12 | 14 | 6 | 9 | 3 | 9 | 6 | 14 | 9 | 14 | 10 | 10 | 16
INPUTS | 8 | LAN_SM_FSM_FFd1  | BUF_LAN_READY  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | Z3_ADR<13>  | Z3_DATA<16>.EXP  | LAN_SM_RST
INPUTMC | 8 | 15 | 16 | 14 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 13 | 16 | 15 | 17 | 8 | 0
EXPORTS | 1 | 15 | 15
IMPORTS | 1 | 15 | 17
EQ | 15 | 
   LAN_SM_FSM_FFd1.D = LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1
	# LAN_SM_FSM_FFd1 & !BUF_LAN_READY
	# LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	BUF_LAN_READY
;Imported pterms FB16_18
	# !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	LAN_SM_FSM_FFd3 & BUF_LAN_READY
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & !RW;
   LAN_SM_FSM_FFd1.CLK = CLK_EXT;	// GCK
   LAN_SM_FSM_FFd1.AR = LAN_SM_RST;
    LAN_SM_FSM_FFd1.EXP  =  !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13>
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 15 | LAN_SM_FSM_FFd3
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 53 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 11 | 15 | 15 | 15 | 14 | 10 | 15 | 9 | 17 | 9 | 15 | 15 | 12 | 11 | 17 | 14 | 0 | 14 | 2 | 11 | 16 | 11 | 13 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 1 | 14 | 4 | 11 | 14 | 9 | 12 | 11 | 12 | 10 | 17 | 14 | 17 | 14 | 7 | 11 | 0 | 15 | 13 | 14 | 6 | 9 | 6 | 14 | 9 | 14 | 10 | 9 | 0 | 9 | 11 | 9 | 13 | 9 | 16 | 10 | 16 | 14 | 5 | 15 | 16 | 15 | 17
INPUTS | 9 | LAN_SM_FSM_FFd1  | BUF_LAN_READY  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd3  | Z3_ADR<13>  | RW  | $OpTx$FX_DC$46  | LAN_SM_FSM_FFd4  | LAN_SM_RST
INPUTMC | 8 | 15 | 16 | 14 | 6 | 15 | 12 | 10 | 15 | 13 | 16 | 5 | 12 | 15 | 15 | 8 | 0
INPUTP | 1 | 158
EQ | 7 | 
   LAN_SM_FSM_FFd3.D = LAN_SM_FSM_FFd4
	# LAN_SM_FSM_FFd1 & !BUF_LAN_READY
	# LAN_SM_FSM_FFd3 & !BUF_LAN_READY
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd3 & !Z3_ADR<13> & 
	RW & $OpTx$FX_DC$46;
   LAN_SM_FSM_FFd3.CLK = CLK_EXT;	// GCK
   LAN_SM_FSM_FFd3.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 9 | LAN_RST_SM_FSM_FFd3
ATTRIBUTES | 4358928 | 0
OUTPUTMC | 6 | 8 | 9 | 8 | 11 | 8 | 12 | 8 | 8 | 8 | 15 | 8 | 7
INPUTS | 4 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1  | RESET
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
INPUTP | 1 | 263
EQ | 6 | 
   LAN_RST_SM_FSM_FFd3.T = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & 
	!LAN_RST_SM_FSM_FFd1
	# !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & 
	LAN_RST_SM_FSM_FFd1;
   LAN_RST_SM_FSM_FFd3.CLK = CLK_EXT;	// GCK
   LAN_RST_SM_FSM_FFd3.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 4 | 17 | AUTOCONFIG_Z2_ACCESS
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 18 | 1 | 17 | 1 | 15 | 1 | 12 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 10 | 1 | 8 | 13 | 13 | 1 | 0 | 13 | 1 | 1 | 3 | 1 | 6 | 3 | 16 | 4 | 15 | 4 | 10 | 4 | 12
INPUTS | 12 | CFIN  | A<18>.PIN  | A<17>.PIN  | A<16>.PIN  | A<23>.PIN  | A<22>.PIN  | A<21>.PIN  | A<19>.PIN  | A<20>.PIN  | CFOUT  | AS  | RESET
INPUTMC | 1 | 13 | 10
INPUTP | 11 | 190 | 171 | 172 | 175 | 161 | 162 | 163 | 169 | 167 | 152 | 263
EQ | 5 | 
   AUTOCONFIG_Z2_ACCESS.D = !CFIN & !A<18>.PIN & !A<17>.PIN & !A<16>.PIN & 
	A<23>.PIN & A<22>.PIN & A<21>.PIN & A<19>.PIN & !A<20>.PIN & 
	CFOUT;
   AUTOCONFIG_Z2_ACCESS.CLK = !AS;
   AUTOCONFIG_Z2_ACCESS.AR = !RESET;

MACROCELL | 8 | 11 | LAN_RST_SM_FSM_FFd2
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 6 | 8 | 9 | 8 | 11 | 8 | 12 | 8 | 8 | 8 | 15 | 8 | 7
INPUTS | 4 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1  | RESET
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
INPUTP | 1 | 263
EQ | 5 | 
   !LAN_RST_SM_FSM_FFd2.D = !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2
	# LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & 
	LAN_RST_SM_FSM_FFd1;
   LAN_RST_SM_FSM_FFd2.CLK = CLK_EXT;	// GCK
   LAN_RST_SM_FSM_FFd2.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 12 | LAN_RST_SM_FSM_FFd1
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 6 | 8 | 9 | 8 | 11 | 8 | 12 | 8 | 8 | 8 | 15 | 8 | 7
INPUTS | 4 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1  | RESET
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
INPUTP | 1 | 263
EQ | 4 | 
   LAN_RST_SM_FSM_FFd1.D = !LAN_RST_SM_FSM_FFd3
	# !LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1;
   LAN_RST_SM_FSM_FFd1.CLK = CLK_EXT;	// GCK
   LAN_RST_SM_FSM_FFd1.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 0 | 17 | IDE_ACCESS
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 15 | 13 | 13
INPUTS | 7 | SHUT_UP_Z2<2>  | IDE_BASEADR<3>  | A<19>.PIN  | EXP22_.EXP  | IDE_R_OBUF.EXP  | AS  | RESET
INPUTMC | 4 | 1 | 8 | 6 | 5 | 0 | 0 | 0 | 16
INPUTP | 3 | 169 | 152 | 263
IMPORTS | 2 | 0 | 0 | 0 | 16
EQ | 22 | 
   !IDE_ACCESS.D = SHUT_UP_Z2<2>
	# IDE_BASEADR<3> & !A<19>.PIN
	# !IDE_BASEADR<3> & A<19>.PIN
;Imported pterms FB1_1
	# !IDE_BASEADR<0> & A<16>.PIN
	# IDE_BASEADR<6> & !A<22>.PIN
	# !IDE_BASEADR<6> & A<22>.PIN
	# IDE_BASEADR<7> & !A<23>.PIN
	# !IDE_BASEADR<7> & A<23>.PIN
;Imported pterms FB1_2
	# IDE_BASEADR<4> & !A<20>.PIN
	# !IDE_BASEADR<4> & A<20>.PIN
	# IDE_BASEADR<5> & !A<21>.PIN
	# !IDE_BASEADR<5> & A<21>.PIN
;Imported pterms FB1_17
	# IDE_BASEADR<0> & !A<16>.PIN
	# IDE_BASEADR<1> & !A<17>.PIN
	# !IDE_BASEADR<1> & A<17>.PIN
	# IDE_BASEADR<2> & !A<18>.PIN
	# !IDE_BASEADR<2> & A<18>.PIN;
   IDE_ACCESS.CLK = !AS;
   IDE_ACCESS.AR = !RESET;

MACROCELL | 12 | 5 | LAN_ACCESS
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 3 | 7 | 7 | 13 | 2 | 13 | 0
INPUTS | 5 | Z3  | SHUT_UP_Z2<0>  | Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2  | FCS  | RESET
INPUTMC | 2 | 12 | 4 | 5 | 16
INPUTP | 3 | 151 | 147 | 263
EQ | 4 | 
   LAN_ACCESS.D = Z3 & !SHUT_UP_Z2<0> & 
	!Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2;
   LAN_ACCESS.CLK = !FCS;
   LAN_ACCESS.AR = !RESET;

MACROCELL | 13 | 16 | Z3_ADR<13>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 5 | 15 | 11 | 15 | 10 | 10 | 15 | 15 | 16 | 15 | 17
INPUTS | 3 | A<15>.PIN  | FCS  | RESET
INPUTP | 3 | 139 | 147 | 263
EQ | 3 | 
   Z3_ADR<13>.D = A<15>.PIN;
   Z3_ADR<13>.CLK = !FCS;
   Z3_ADR<13>.AP = !RESET;

MACROCELL | 3 | 10 | IDE_ENABLE
ATTRIBUTES | 8520672 | 0
OUTPUTMC | 2 | 3 | 12 | 3 | 15
INPUTS | 5 | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET  | AS  | IDE_ACCESS  | RW
INPUTMC | 2 | 13 | 3 | 0 | 17
INPUTP | 3 | 263 | 152 | 158
EQ | 4 | 
   IDE_ENABLE.D = Gnd;
   IDE_ENABLE.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_ENABLE.AP = !RESET;
   IDE_ENABLE.CE = !AS & IDE_ACCESS & !RW;

MACROCELL | 9 | 17 | DQ_DATA<0>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 2 | 9 | 17
INPUTS | 13 | DQ_DATA<0>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<8>.PIN  | $OpTx$FX_SC$67  | A<16>.PIN  | D<8>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | LAN_A_INIT<3>.EXP  | LAN_SM_RST
INPUTMC | 10 | 9 | 17 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 9 | 0 | 8 | 0
INPUTP | 3 | 106 | 175 | 32
IMPORTS | 1 | 9 | 0
EQ | 10 | 
   DQ_DATA<0>.D = DQ_DATA<0> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<16>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<8>.PIN & $OpTx$FX_SC$67
	# D<8>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
;Imported pterms FB10_1
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<0>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<0>.CLK = CLK_EXT;	// GCK
   DQ_DATA<0>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 9 | 15 | DQ_DATA<10>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 16 | 9 | 15
INPUTS | 13 | DQ_DATA<10>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<18>.PIN  | $OpTx$FX_SC$67  | A<10>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<2>.PIN  | $OpTx$FX_DC$46  | DQ_10_IOBUFE.EXP  | LAN_SM_RST
INPUTMC | 10 | 9 | 15 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 9 | 16 | 8 | 0
INPUTP | 3 | 171 | 112 | 71
IMPORTS | 1 | 9 | 16
EQ | 10 | 
   DQ_DATA<10>.D = DQ_DATA<10> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<10>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<18>.PIN & $OpTx$FX_SC$67
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<2>.PIN & !$OpTx$FX_DC$46
;Imported pterms FB10_17
	# D<10>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46;
   DQ_DATA<10>.CLK = CLK_EXT;	// GCK
   DQ_DATA<10>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 14 | DQ_DATA<11>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 11 | 9 | 15 | 14 | 15 | 15
INPUTS | 12 | DQ_DATA<11>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<19>.PIN  | $OpTx$FX_SC$67  | A<11>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$49  | Z3_A_LOW.EXP  | LAN_SM_RST
INPUTMC | 10 | 15 | 14 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 2 | 17 | 15 | 13 | 8 | 0
INPUTP | 2 | 169 | 114
EXPORTS | 1 | 15 | 15
IMPORTS | 1 | 15 | 13
EQ | 12 | 
   DQ_DATA<11>.D = DQ_DATA<11> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<11>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<19>.PIN & $OpTx$FX_SC$67
;Imported pterms FB16_14
	# D<11>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<3>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<11>.CLK = CLK_EXT;	// GCK
   DQ_DATA<11>.AP = LAN_SM_RST;
    DQ_DATA<11>.EXP  =  !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$49
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 0 | DQ_DATA<12>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 7 | 1 | 14 | 0 | 14 | 1
INPUTS | 13 | DQ_DATA<12>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<20>.PIN  | $OpTx$FX_SC$67  | D<13>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | D<5>.PIN  | EXP31_.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 0 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 17 | 8 | 0
INPUTP | 3 | 167 | 80 | 37
EXPORTS | 1 | 14 | 1
IMPORTS | 1 | 14 | 17
EQ | 14 | 
   DQ_DATA<12>.D = DQ_DATA<12> & !$OpTx$FX_DC$65
	# !DQ_SWAP & A<20>.PIN & $OpTx$FX_SC$67
;Imported pterms FB15_18
	# DQ_SWAP & A<12>.PIN & $OpTx$FX_SC$67
	# D<12>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<4>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<12>.CLK = CLK_EXT;	// GCK
   DQ_DATA<12>.AP = LAN_SM_RST;
    DQ_DATA<12>.EXP  =  D<13>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<5>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 1 | DQ_DATA<13>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 11 | 7 | 14 | 1 | 14 | 2
INPUTS | 13 | DQ_DATA<13>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<21>.PIN  | $OpTx$FX_SC$67  | A<13>.PIN  | D<14>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | DQ_DATA<12>.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 1 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 0 | 8 | 0
INPUTP | 3 | 163 | 123 | 81
EXPORTS | 1 | 14 | 2
IMPORTS | 1 | 14 | 0
EQ | 12 | 
   DQ_DATA<13>.D = DQ_DATA<13> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<13>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<21>.PIN & $OpTx$FX_SC$67
;Imported pterms FB15_1
	# D<13>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<5>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<13>.CLK = CLK_EXT;	// GCK
   DQ_DATA<13>.AP = LAN_SM_RST;
    DQ_DATA<13>.EXP  =  D<14>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 2 | DQ_DATA<14>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 7 | 2 | 14 | 2
INPUTS | 13 | DQ_DATA<14>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<22>.PIN  | $OpTx$FX_SC$67  | A<14>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<6>.PIN  | $OpTx$FX_DC$46  | DQ_DATA<13>.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 2 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 1 | 8 | 0
INPUTP | 3 | 162 | 125 | 26
IMPORTS | 1 | 14 | 1
EQ | 10 | 
   DQ_DATA<14>.D = DQ_DATA<14> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<14>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<22>.PIN & $OpTx$FX_SC$67
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<6>.PIN & !$OpTx$FX_DC$46
;Imported pterms FB15_2
	# D<14>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46;
   DQ_DATA<14>.CLK = CLK_EXT;	// GCK
   DQ_DATA<14>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 17 | DQ_DATA<15>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 11 | 4 | 11 | 17 | 11 | 16
INPUTS | 13 | DQ_DATA<15>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<23>.PIN  | $OpTx$FX_SC$67  | D<9>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | D<1>.PIN  | LAN_WRL_S.EXP  | LAN_SM_RST
INPUTMC | 10 | 11 | 17 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 0 | 8 | 0
INPUTP | 3 | 161 | 73 | 30
EXPORTS | 1 | 11 | 16
IMPORTS | 1 | 11 | 0
EQ | 14 | 
   DQ_DATA<15>.D = DQ_DATA<15> & !$OpTx$FX_DC$65
	# !DQ_SWAP & A<23>.PIN & $OpTx$FX_SC$67
;Imported pterms FB12_1
	# DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$67
	# D<15>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<7>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<15>.CLK = CLK_EXT;	// GCK
   DQ_DATA<15>.AP = LAN_SM_RST;
    DQ_DATA<15>.EXP  =  D<9>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<1>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 16 | DQ_DATA<1>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 9 | 1 | 11 | 16 | 11 | 15
INPUTS | 13 | DQ_DATA<1>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<9>.PIN  | $OpTx$FX_SC$67  | A<17>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<3>.PIN  | $OpTx$FX_DC$46  | DQ_DATA<15>.EXP  | LAN_SM_RST
INPUTMC | 10 | 11 | 16 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 17 | 8 | 0
INPUTP | 3 | 108 | 172 | 28
EXPORTS | 1 | 11 | 15
IMPORTS | 1 | 11 | 17
EQ | 12 | 
   DQ_DATA<1>.D = DQ_DATA<1> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<17>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<9>.PIN & $OpTx$FX_SC$67
;Imported pterms FB12_18
	# D<9>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<1>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<1>.CLK = CLK_EXT;	// GCK
   DQ_DATA<1>.AP = LAN_SM_RST;
    DQ_DATA<1>.EXP  =  !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<3>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 9 | 14 | DQ_DATA<2>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 5 | 9 | 14
INPUTS | 13 | DQ_DATA<2>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<10>.PIN  | $OpTx$FX_SC$67  | A<18>.PIN  | D<10>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | DQ_8_IOBUFE.EXP  | LAN_SM_RST
INPUTMC | 10 | 9 | 14 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 9 | 13 | 8 | 0
INPUTP | 3 | 112 | 171 | 74
IMPORTS | 1 | 9 | 13
EQ | 10 | 
   DQ_DATA<2>.D = DQ_DATA<2> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<18>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<10>.PIN & $OpTx$FX_SC$67
	# D<10>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
;Imported pterms FB10_14
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<2>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<2>.CLK = CLK_EXT;	// GCK
   DQ_DATA<2>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 15 | DQ_DATA<3>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 4 | 11 | 15
INPUTS | 13 | DQ_DATA<3>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<11>.PIN  | $OpTx$FX_SC$67  | A<19>.PIN  | D<11>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | DQ_DATA<1>.EXP  | LAN_SM_RST
INPUTMC | 10 | 11 | 15 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 16 | 8 | 0
INPUTP | 3 | 114 | 169 | 77
IMPORTS | 1 | 11 | 16
EQ | 10 | 
   DQ_DATA<3>.D = DQ_DATA<3> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<19>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<11>.PIN & $OpTx$FX_SC$67
	# D<11>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
;Imported pterms FB12_17
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<3>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<3>.CLK = CLK_EXT;	// GCK
   DQ_DATA<3>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 3 | DQ_DATA<4>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 9 | 14 | 3
INPUTS | 13 | DQ_DATA<4>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<12>.PIN  | $OpTx$FX_SC$67  | A<20>.PIN  | D<12>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | DQ_DATA<5>.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 3 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 4 | 8 | 0
INPUTP | 3 | 115 | 167 | 78
IMPORTS | 1 | 14 | 4
EQ | 10 | 
   DQ_DATA<4>.D = DQ_DATA<4> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<20>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<12>.PIN & $OpTx$FX_SC$67
	# D<12>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
;Imported pterms FB15_5
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<4>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<4>.CLK = CLK_EXT;	// GCK
   DQ_DATA<4>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 4 | DQ_DATA<5>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 9 | 7 | 14 | 4 | 14 | 3
INPUTS | 13 | DQ_DATA<5>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<13>.PIN  | $OpTx$FX_SC$67  | A<21>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<4>.PIN  | $OpTx$FX_DC$46  | DQ_DATA<6>.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 4 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 5 | 8 | 0
INPUTP | 3 | 123 | 163 | 38
EXPORTS | 1 | 14 | 3
IMPORTS | 1 | 14 | 5
EQ | 12 | 
   DQ_DATA<5>.D = DQ_DATA<5> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<21>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<13>.PIN & $OpTx$FX_SC$67
;Imported pterms FB15_6
	# D<13>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<5>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<5>.CLK = CLK_EXT;	// GCK
   DQ_DATA<5>.AP = LAN_SM_RST;
    DQ_DATA<5>.EXP  =  !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<4>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 5 | DQ_DATA<6>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 9 | 11 | 14 | 5 | 14 | 4
INPUTS | 13 | DQ_DATA<6>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<14>.PIN  | $OpTx$FX_SC$67  | D<13>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | D<5>.PIN  | BUF_LAN_READY.EXP  | LAN_SM_RST
INPUTMC | 10 | 14 | 5 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 14 | 6 | 8 | 0
INPUTP | 3 | 125 | 80 | 37
EXPORTS | 1 | 14 | 4
IMPORTS | 1 | 14 | 6
EQ | 14 | 
   DQ_DATA<6>.D = DQ_DATA<6> & !$OpTx$FX_DC$65
	# !DQ_SWAP & A<14>.PIN & $OpTx$FX_SC$67
;Imported pterms FB15_7
	# DQ_SWAP & A<22>.PIN & $OpTx$FX_SC$67
	# D<14>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<6>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<6>.CLK = CLK_EXT;	// GCK
   DQ_DATA<6>.AP = LAN_SM_RST;
    DQ_DATA<6>.EXP  =  D<13>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<5>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 14 | DQ_DATA<7>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 10 | 11 | 14
INPUTS | 13 | DQ_DATA<7>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<15>.PIN  | $OpTx$FX_SC$67  | A<23>.PIN  | D<15>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | DQ_DATA<9>.EXP  | LAN_SM_RST
INPUTMC | 10 | 11 | 14 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 13 | 8 | 0
INPUTP | 3 | 139 | 161 | 89
IMPORTS | 1 | 11 | 13
EQ | 10 | 
   DQ_DATA<7>.D = DQ_DATA<7> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<23>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$67
	# D<15>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
;Imported pterms FB12_14
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<7>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<7>.CLK = CLK_EXT;	// GCK
   DQ_DATA<7>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 9 | 12 | DQ_DATA<8>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 13 | 9 | 12
INPUTS | 13 | DQ_DATA<8>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<16>.PIN  | $OpTx$FX_SC$67  | A<8>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<0>.PIN  | $OpTx$FX_DC$46  | DQ_6_IOBUFE.EXP  | LAN_SM_RST
INPUTMC | 10 | 9 | 12 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 9 | 11 | 8 | 0
INPUTP | 3 | 175 | 106 | 4
IMPORTS | 1 | 9 | 11
EQ | 10 | 
   DQ_DATA<8>.D = DQ_DATA<8> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<8>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<16>.PIN & $OpTx$FX_SC$67
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<0>.PIN & !$OpTx$FX_DC$46
;Imported pterms FB10_12
	# D<8>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46;
   DQ_DATA<8>.CLK = CLK_EXT;	// GCK
   DQ_DATA<8>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 13 | DQ_DATA<9>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 11 | 11 | 11 | 13 | 11 | 14
INPUTS | 13 | DQ_DATA<9>  | $OpTx$FX_DC$65  | DQ_SWAP  | A<17>.PIN  | $OpTx$FX_SC$67  | A<9>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<7>.PIN  | $OpTx$FX_DC$46  | LAN_INT_ENABLE.EXP  | LAN_SM_RST
INPUTMC | 10 | 11 | 13 | 9 | 3 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 12 | 8 | 0
INPUTP | 3 | 172 | 108 | 29
EXPORTS | 1 | 11 | 14
IMPORTS | 1 | 11 | 12
EQ | 12 | 
   DQ_DATA<9>.D = DQ_DATA<9> & !$OpTx$FX_DC$65
	# DQ_SWAP & A<9>.PIN & $OpTx$FX_SC$67
	# !DQ_SWAP & A<17>.PIN & $OpTx$FX_SC$67
;Imported pterms FB12_13
	# D<9>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<1>.PIN & !$OpTx$FX_DC$46;
   DQ_DATA<9>.CLK = CLK_EXT;	// GCK
   DQ_DATA<9>.AP = LAN_SM_RST;
    DQ_DATA<9>.EXP  =  !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<7>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 12 | LAN_INT_ENABLE
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 4 | 11 | 12 | 10 | 16 | 2 | 13 | 11 | 13
INPUTS | 13 | LAN_INT_ENABLE  | $OpTx$FX_DC$106  | D<15>.PIN  | UDS  | DS1  | D<9>.PIN  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | D<1>.PIN  | DQ_9_IOBUFE.EXP
INPUTMC | 8 | 11 | 12 | 14 | 9 | 0 | 15 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12 | 11 | 11
INPUTP | 5 | 89 | 155 | 148 | 73 | 30
EXPORTS | 1 | 11 | 13
IMPORTS | 1 | 11 | 11
EQ | 10 | 
   LAN_INT_ENABLE.D = LAN_INT_ENABLE & !$OpTx$FX_DC$106
	# D<15>.PIN & !UDS & $OpTx$FX_DC$106
	# UDS & DS1 & LAN_INT_ENABLE
;Imported pterms FB12_12
	# UDS & !DS1 & A<23>.PIN & $OpTx$FX_DC$106;
   LAN_INT_ENABLE.CLK = CLK_EXT;	// GCK
    LAN_INT_ENABLE.EXP  =  D<9>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<1>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 8 | LAN_WR_RST
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 7 | 4 | 12 | 13
INPUTS | 4 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1  | RESET
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
INPUTP | 1 | 263
EQ | 6 | 
   LAN_WR_RST.D = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & 
	!LAN_RST_SM_FSM_FFd1
	# LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & 
	LAN_RST_SM_FSM_FFd1;
   LAN_WR_RST.CLK = CLK_EXT;	// GCK
   LAN_WR_RST.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 10 | 17 | Z3_DATA<31>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 6 | 11 | 10 | 17
INPUTS | 8 | LAN_SM_FSM_FFd4  | Z3_DATA<31>  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$99  | LAN_SM_FSM_FFd1  | CP_WE_OBUF.EXP  | LAN_SM_RST
INPUTMC | 8 | 15 | 15 | 10 | 17 | 15 | 12 | 10 | 15 | 14 | 10 | 15 | 16 | 10 | 16 | 8 | 0
IMPORTS | 1 | 10 | 16
EQ | 13 | 
   Z3_DATA<31>.D = LAN_SM_FSM_FFd4 & Z3_DATA<31>
	# LAN_SM_FSM_FFd2 & Z3_DATA<31> & !$OpTx$FX_DC$99
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd3 & Z3_DATA<31>
	# !LAN_SM_FSM_FFd1 & Z3_DATA<31> & !$OpTx$FX_DC$99
;Imported pterms FB11_17
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1 & DQ<7>.PIN
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1 & DQ<15>.PIN
	# LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & LAN_INT_ENABLE & RW;
   Z3_DATA<31>.CLK = CLK_EXT;	// GCK
   Z3_DATA<31>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 12 | 4 | SHUT_UP_Z2<0>
ATTRIBUTES | 8520612 | 0
OUTPUTMC | 3 | 0 | 15 | 12 | 5 | 12 | 4
INPUTS | 4 | SHUT_UP_Z2<0>  | $OpTx$FX_DC$72  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 12 | 4 | 1 | 6 | 13 | 3
INPUTP | 1 | 263
EQ | 3 | 
   SHUT_UP_Z2<0>.D = SHUT_UP_Z2<0> & !$OpTx$FX_DC$72;
   SHUT_UP_Z2<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   SHUT_UP_Z2<0>.AP = !RESET;

MACROCELL | 1 | 10 | SHUT_UP_Z2<1>
ATTRIBUTES | 4326308 | 0
OUTPUTMC | 2 | 1 | 10 | 4 | 1
INPUTS | 15 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTOCONFIG_Z2_ACCESS  | SHUT_UP_Z2<1>  | RW  | A<4>  | A<5>  | A<6>  | A<2>  | A<3>  | A<1>  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 6 | 3 | 8 | 3 | 9 | 4 | 17 | 1 | 10 | 5 | 12 | 13 | 3
INPUTP | 9 | 152 | 158 | 97 | 91 | 98 | 101 | 99 | 107 | 263
EQ | 6 | 
   SHUT_UP_Z2<1>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	!AUTO_CONFIG_Z2_DONE<1> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<1> & !RW & 
	!A<4> & !A<5> & A<6> & !A<2> & A<3> & !A<1> & 
	!$OpTx$FX_DC$46;
   SHUT_UP_Z2<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   SHUT_UP_Z2<1>.AP = !RESET;

MACROCELL | 1 | 8 | SHUT_UP_Z2<2>
ATTRIBUTES | 4326308 | 0
OUTPUTMC | 2 | 0 | 17 | 1 | 8
INPUTS | 16 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTOCONFIG_Z2_ACCESS  | SHUT_UP_Z2<2>  | RW  | A<4>  | A<5>  | A<6>  | A<2>  | A<3>  | A<1>  | CFOUT  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 7 | 3 | 8 | 3 | 9 | 4 | 17 | 1 | 8 | 13 | 10 | 5 | 12 | 13 | 3
INPUTP | 9 | 152 | 158 | 97 | 91 | 98 | 101 | 99 | 107 | 263
EQ | 6 | 
   SHUT_UP_Z2<2>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	AUTO_CONFIG_Z2_DONE<1> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<2> & !RW & 
	!A<4> & !A<5> & A<6> & !A<2> & A<3> & !A<1> & CFOUT & 
	!$OpTx$FX_DC$46;
   SHUT_UP_Z2<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   SHUT_UP_Z2<2>.AP = !RESET;

MACROCELL | 6 | 1 | D_Z2_OUT<0>
ATTRIBUTES | 8520612 | 0
OUTPUTMC | 1 | 4 | 16
INPUTS | 3 | BUF_D_Z2_OUT<0>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 2 | 3 | 2 | 13 | 3
INPUTP | 1 | 263
EQ | 3 | 
   !D_Z2_OUT<0>.D = BUF_D_Z2_OUT<0>;
   D_Z2_OUT<0>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   D_Z2_OUT<0>.AP = !RESET;

MACROCELL | 3 | 0 | D_Z2_OUT<1>
ATTRIBUTES | 8520612 | 0
OUTPUTMC | 1 | 6 | 2
INPUTS | 8 | $OpTx$FX_DC$95  | A<5>  | BUF_D_Z2_OUT<3>  | A<2>  | BUF_D_Z2_OUT<2>  | $OpTx$FX_DC$77.EXP  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 5 | 13 | 1 | 3 | 6 | 3 | 3 | 3 | 17 | 13 | 3
INPUTP | 3 | 91 | 101 | 263
IMPORTS | 1 | 3 | 17
EQ | 12 | 
   D_Z2_OUT<1>.D = !$OpTx$FX_DC$95
	# A<5> & !BUF_D_Z2_OUT<3>
	# A<2> & !BUF_D_Z2_OUT<2> & BUF_D_Z2_OUT<3>
;Imported pterms FB4_18
	# A<4> & !A<2> & !BUF_D_Z2_OUT<3>
	# A<4> & BUF_D_Z2_OUT<0> & !BUF_D_Z2_OUT<3>
	# !A<4> & A<3> & !A<1>
	# !A<4> & A<2> & !BUF_D_Z2_OUT<0> & BUF_D_Z2_OUT<2>
	# AUTO_CONFIG_Z2_DONE<0> & AUTO_CONFIG_Z2_DONE<1> & 
	A<4> & A<1> & !BUF_D_Z2_OUT<0>;
   D_Z2_OUT<1>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   D_Z2_OUT<1>.AP = !RESET;

MACROCELL | 13 | 17 | D_Z2_OUT<2>
ATTRIBUTES | 8520612 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 3 | BUF_D_Z2_OUT<2>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 2 | 3 | 3 | 13 | 3
INPUTP | 1 | 263
EQ | 3 | 
   D_Z2_OUT<2>.D = BUF_D_Z2_OUT<2>;
   D_Z2_OUT<2>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   D_Z2_OUT<2>.AP = !RESET;

MACROCELL | 12 | 6 | D_Z2_OUT<3>
ATTRIBUTES | 8520612 | 0
OUTPUTMC | 1 | 6 | 11
INPUTS | 3 | BUF_D_Z2_OUT<3>  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 2 | 3 | 6 | 13 | 3
INPUTP | 1 | 263
EQ | 3 | 
   !D_Z2_OUT<3>.D = BUF_D_Z2_OUT<3>;
   D_Z2_OUT<3>.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   D_Z2_OUT<3>.AP = !RESET;

MACROCELL | 3 | 12 | IDE_R_S
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 6 | AS  | IDE_ACCESS  | IDE_ENABLE  | RW  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 0 | 17 | 3 | 10 | 13 | 3
INPUTP | 3 | 152 | 158 | 263
EQ | 3 | 
   !IDE_R_S.D = !AS & IDE_ACCESS & !IDE_ENABLE & RW;
   IDE_R_S.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_R_S.AP = !RESET;

MACROCELL | 3 | 14 | IDE_W_S
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 2 | 1
INPUTS | 5 | AS  | IDE_ACCESS  | RW  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 2 | 0 | 17 | 13 | 3
INPUTP | 3 | 152 | 158 | 263
EQ | 3 | 
   !IDE_W_S.D = !AS & IDE_ACCESS & !RW;
   IDE_W_S.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   IDE_W_S.AP = !RESET;

MACROCELL | 3 | 15 | ROM_OE_S
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 4 | 4
INPUTS | 6 | AS  | IDE_ACCESS  | IDE_ENABLE  | RW  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | RESET
INPUTMC | 3 | 0 | 17 | 3 | 10 | 13 | 3
INPUTP | 3 | 152 | 158 | 263
EQ | 3 | 
   !ROM_OE_S.D = !AS & IDE_ACCESS & IDE_ENABLE & RW;
   ROM_OE_S.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
   ROM_OE_S.AP = !RESET;

MACROCELL | 0 | 12 | Z3_ADR<10>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 7
INPUTS | 3 | A<12>.PIN  | FCS  | RESET
INPUTP | 3 | 115 | 147 | 263
EQ | 3 | 
   Z3_ADR<10>.D = A<12>.PIN;
   Z3_ADR<10>.CLK = !FCS;
   Z3_ADR<10>.AP = !RESET;

MACROCELL | 0 | 10 | Z3_ADR<11>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 2
INPUTS | 3 | A<13>.PIN  | FCS  | RESET
INPUTP | 3 | 123 | 147 | 263
EQ | 3 | 
   Z3_ADR<11>.D = A<13>.PIN;
   Z3_ADR<11>.CLK = !FCS;
   Z3_ADR<11>.AP = !RESET;

MACROCELL | 0 | 8 | Z3_ADR<12>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 4
INPUTS | 3 | A<14>.PIN  | FCS  | RESET
INPUTP | 3 | 125 | 147 | 263
EQ | 3 | 
   Z3_ADR<12>.D = A<14>.PIN;
   Z3_ADR<12>.CLK = !FCS;
   Z3_ADR<12>.AP = !RESET;

MACROCELL | 13 | 15 | Z3_ADR<2>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 3 | 7
INPUTS | 3 | A<4>  | FCS  | RESET
INPUTP | 3 | 97 | 147 | 263
EQ | 3 | 
   Z3_ADR<2>.D = A<4>;
   Z3_ADR<2>.CLK = !FCS;
   Z3_ADR<2>.AP = !RESET;

MACROCELL | 13 | 12 | Z3_ADR<3>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 1 | 1
INPUTS | 3 | A<5>  | FCS  | RESET
INPUTP | 3 | 91 | 147 | 263
EQ | 3 | 
   Z3_ADR<3>.D = A<5>;
   Z3_ADR<3>.CLK = !FCS;
   Z3_ADR<3>.AP = !RESET;

MACROCELL | 13 | 11 | Z3_ADR<4>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 3 | 13
INPUTS | 3 | A<6>  | FCS  | RESET
INPUTP | 3 | 98 | 147 | 263
EQ | 3 | 
   Z3_ADR<4>.D = A<6>;
   Z3_ADR<4>.CLK = !FCS;
   Z3_ADR<4>.AP = !RESET;

MACROCELL | 13 | 9 | Z3_ADR<5>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 1 | 4
INPUTS | 3 | A<7>  | FCS  | RESET
INPUTP | 3 | 100 | 147 | 263
EQ | 3 | 
   Z3_ADR<5>.D = A<7>;
   Z3_ADR<5>.CLK = !FCS;
   Z3_ADR<5>.AP = !RESET;

MACROCELL | 13 | 8 | Z3_ADR<6>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 1 | 2
INPUTS | 3 | A<8>.PIN  | FCS  | RESET
INPUTP | 3 | 106 | 147 | 263
EQ | 3 | 
   Z3_ADR<6>.D = A<8>.PIN;
   Z3_ADR<6>.CLK = !FCS;
   Z3_ADR<6>.AP = !RESET;

MACROCELL | 0 | 6 | Z3_ADR<7>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 9
INPUTS | 3 | A<9>.PIN  | FCS  | RESET
INPUTP | 3 | 108 | 147 | 263
EQ | 3 | 
   Z3_ADR<7>.D = A<9>.PIN;
   Z3_ADR<7>.CLK = !FCS;
   Z3_ADR<7>.AP = !RESET;

MACROCELL | 0 | 3 | Z3_ADR<8>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 13
INPUTS | 3 | A<10>.PIN  | FCS  | RESET
INPUTP | 3 | 112 | 147 | 263
EQ | 3 | 
   Z3_ADR<8>.D = A<10>.PIN;
   Z3_ADR<8>.CLK = !FCS;
   Z3_ADR<8>.AP = !RESET;

MACROCELL | 0 | 2 | Z3_ADR<9>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 5
INPUTS | 3 | A<11>.PIN  | FCS  | RESET
INPUTP | 3 | 114 | 147 | 263
EQ | 3 | 
   Z3_ADR<9>.D = A<11>.PIN;
   Z3_ADR<9>.CLK = !FCS;
   Z3_ADR<9>.AP = !RESET;

MACROCELL | 13 | 7 | Z3_ADR_0
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 3 | 5
INPUTS | 3 | A<2>  | FCS  | RESET
INPUTP | 3 | 101 | 147 | 263
EQ | 3 | 
   Z3_ADR_0.D = A<2>;
   Z3_ADR_0.CLK = !FCS;
   Z3_ADR_0.AP = !RESET;

MACROCELL | 13 | 6 | Z3_ADR_1
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 3 | 11
INPUTS | 3 | A<3>  | FCS  | RESET
INPUTP | 3 | 99 | 147 | 263
EQ | 3 | 
   Z3_ADR_1.D = A<3>;
   Z3_ADR_1.CLK = !FCS;
   Z3_ADR_1.AP = !RESET;

MACROCELL | 8 | 5 | LAN_A_INIT<6>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 1 | 4
INPUTS | 2 | BUF_LAN_D_INIT<1>  | RESET
INPUTMC | 1 | 8 | 7
INPUTP | 1 | 263
EQ | 3 | 
   !LAN_A_INIT<6>.D = BUF_LAN_D_INIT<1>;
   LAN_A_INIT<6>.CLK = CLK_EXT;	// GCK
   LAN_A_INIT<6>.AP = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 15 | LAN_CS_RST
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 7 | 7
INPUTS | 4 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1  | RESET
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
INPUTP | 1 | 263
EQ | 6 | 
   !LAN_CS_RST.D = !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & 
	LAN_RST_SM_FSM_FFd1
	# !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & 
	!LAN_RST_SM_FSM_FFd1;
   LAN_CS_RST.CLK = CLK_EXT;	// GCK
   LAN_CS_RST.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 4 | LAN_D_INIT<1>
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 9 | 1 | 9 | 9 | 11 | 11
INPUTS | 2 | BUF_LAN_D_INIT<1>  | RESET
INPUTMC | 1 | 8 | 7
INPUTP | 1 | 263
EQ | 3 | 
   LAN_D_INIT<1>.D = BUF_LAN_D_INIT<1>;
   LAN_D_INIT<1>.CLK = CLK_EXT;	// GCK
   LAN_D_INIT<1>.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 3 | LAN_D_INIT<8>
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 9 | 16 | 11 | 9 | 9 | 13
INPUTS | 2 | BUF_LAN_D_INIT<1>  | RESET
INPUTMC | 1 | 8 | 7
INPUTP | 1 | 263
EQ | 3 | 
   !LAN_D_INIT<8>.D = BUF_LAN_D_INIT<1>;
   LAN_D_INIT<8>.CLK = CLK_EXT;	// GCK
   LAN_D_INIT<8>.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 2 | LAN_IRQ_D0
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 1 | 8 | 14
INPUTS | 2 | LAN_INT  | RESET
INPUTP | 2 | 201 | 263
EQ | 3 | 
   LAN_IRQ_D0.D = LAN_INT;
   LAN_IRQ_D0.CLK = CLK_EXT;	// GCK
   LAN_IRQ_D0.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 11 | LAN_RD_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 7 | 9 | 15 | 12
INPUTS | 9 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$49  | Z3_ADR<13>  | LAN_SM_RST  | $OpTx$FX_DC$46  | Z3_DATA<8>.EXP
INPUTMC | 9 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 2 | 17 | 13 | 16 | 8 | 0 | 5 | 12 | 15 | 10
EXPORTS | 1 | 15 | 12
IMPORTS | 1 | 15 | 10
EQ | 15 | 
   LAN_RD_S.D = LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1
;Imported pterms FB16_11
	# LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & RW;
   LAN_RD_S.CLK = CLK_EXT;	// GCK
   LAN_RD_S.AR = LAN_SM_RST;
    LAN_RD_S.EXP  =  !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd3 & 
	$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !Z3_ADR<13> & !$OpTx$FX_DC$46 & 
	$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3 & !Z3_ADR<13> & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 1 | LAN_READY
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 14 | 11
INPUTS | 2 | BUF_LAN_READY  | LAN_SM_RST
INPUTMC | 2 | 14 | 6 | 8 | 0
EQ | 3 | 
   !LAN_READY.D = BUF_LAN_READY;
   LAN_READY.CLK = CLK_EXT;	// GCK
   LAN_READY.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 14 | 7 | LAN_WRH_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 7 | 4 | 14 | 6
INPUTS | 8 | DS0  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | LDS  | LAN_SM_FSM_FFd4  | LAN_SM_RST  | $OpTx$FX_DC$49
INPUTMC | 6 | 15 | 12 | 15 | 16 | 10 | 15 | 15 | 15 | 8 | 0 | 2 | 17
INPUTP | 2 | 170 | 157
EXPORTS | 1 | 14 | 6
EQ | 10 | 
   LAN_WRH_S.D = !LDS & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1
	# !DS0 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3;
   LAN_WRH_S.CLK = CLK_EXT;	// GCK
   LAN_WRH_S.AR = LAN_SM_RST;
    LAN_WRH_S.EXP  =  !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 11 | 0 | LAN_WRL_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 12 | 13 | 11 | 17
INPUTS | 13 | DS1  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | DQ_SWAP  | A<15>.PIN  | LAN_SM_RST  | $OpTx$FX_SC$67  | D<15>.PIN  | LAN_SM_FSM_FFd4  | $OpTx$FX_DC$46  | D<7>.PIN  | ROM_B_0_OBUF$BUF4.EXP
INPUTMC | 9 | 15 | 12 | 15 | 16 | 10 | 15 | 0 | 15 | 8 | 0 | 9 | 6 | 15 | 15 | 5 | 12 | 11 | 1
INPUTP | 4 | 148 | 139 | 89 | 29
EXPORTS | 1 | 11 | 17
IMPORTS | 1 | 11 | 1
EQ | 12 | 
   LAN_WRL_S.D = !DS1 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3
;Imported pterms FB12_2
	# !UDS & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1;
   LAN_WRL_S.CLK = CLK_EXT;	// GCK
   LAN_WRL_S.AR = LAN_SM_RST;
    LAN_WRL_S.EXP  =  DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$67
	# D<15>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<7>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 15 | 13 | Z3_A_LOW
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 3 | 5 | 15 | 14
INPUTS | 10 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | BUF_LAN_READY  | LAN_SM_FSM_FFd3  | D<11>.PIN  | DQ_SWAP  | LAN_SM_RST  | $OpTx$FX_DC$46  | D<3>.PIN  | LAN_SM_FSM_FFd2.EXP
INPUTMC | 8 | 15 | 12 | 15 | 15 | 14 | 6 | 10 | 15 | 0 | 15 | 8 | 0 | 5 | 12 | 15 | 12
INPUTP | 2 | 77 | 28
EXPORTS | 1 | 15 | 14
IMPORTS | 1 | 15 | 12
EQ | 17 | 
   !Z3_A_LOW.D = !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	BUF_LAN_READY
	# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd3 & 
	!BUF_LAN_READY
;Imported pterms FB16_13
	# LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!$OpTx$FX_DC$46 & !BUF_LAN_READY
	# !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46;
   Z3_A_LOW.CLK = CLK_EXT;	// GCK
   Z3_A_LOW.AR = LAN_SM_RST;
    Z3_A_LOW.EXP  =  D<11>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<3>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 3 | 11 | A_LAN_2_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 4 | RESET  | A<2>  | CP_CS  | Z3_ADR_1
INPUTMC | 2 | 4 | 1 | 13 | 6
INPUTP | 2 | 263 | 101
EQ | 2 | 
   !A_LAN<2> = RESET & !A<2> & !CP_CS
	# RESET & !Z3_ADR_1 & CP_CS;

MACROCELL | 1 | 1 | A_LAN_4_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 4 | RESET  | A<4>  | CP_CS  | Z3_ADR<3>
INPUTMC | 2 | 4 | 1 | 13 | 12
INPUTP | 2 | 263 | 97
EQ | 2 | 
   !A_LAN<4> = RESET & !A<4> & !CP_CS
	# RESET & !Z3_ADR<3> & CP_CS;

MACROCELL | 3 | 13 | A_LAN_5_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 4 | RESET  | A<5>  | CP_CS  | Z3_ADR<4>
INPUTMC | 2 | 4 | 1 | 13 | 11
INPUTP | 2 | 263 | 91
EQ | 2 | 
   !A_LAN<5> = RESET & !A<5> & !CP_CS
	# RESET & !Z3_ADR<4> & CP_CS;

MACROCELL | 8 | 0 | LAN_SM_RST
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 58 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 17 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 9 | 17 | 9 | 15 | 15 | 14 | 14 | 0 | 14 | 1 | 14 | 2 | 11 | 17 | 11 | 16 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 4 | 14 | 5 | 11 | 14 | 9 | 12 | 11 | 13 | 10 | 17 | 15 | 11 | 8 | 1 | 14 | 7 | 11 | 0 | 15 | 13 | 14 | 9
INPUTS | 3 | RESET  | BERR  | $OpTx$FX_DC$59
INPUTMC | 1 | 14 | 8
INPUTP | 2 | 263 | 176
EQ | 2 | 
   !LAN_SM_RST.D = RESET & BERR & !$OpTx$FX_DC$59;
   !LAN_SM_RST.CLK = CLK_EXT;	// GCK
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 8 | 6 | CP_WE_S
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 2 | 13 | 5 | 10 | 16
INPUTS | 4 | RW  | CP_CS  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
INPUTMC | 3 | 4 | 1 | 5 | 12 | 13 | 3
INPUTP | 1 | 158
EQ | 2 | 
   !CP_WE_S.D = !RW & !CP_CS & !$OpTx$FX_DC$46;
   CP_WE_S.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;

MACROCELL | 3 | 16 | CP_RD_S
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 2 | 12 | 1 | 3 | 17
INPUTS | 13 | RW  | CP_CS  | $OpTx$FX_DC$46  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF  | AS  | AUTO_CONFIG_Z2_DONE<1>  | AUTOCONFIG_Z2_ACCESS  | A<4>  | A<5>  | A<6>  | A<2>  | A<3>  | A<1>
INPUTMC | 5 | 4 | 1 | 5 | 12 | 13 | 3 | 3 | 9 | 4 | 17
INPUTP | 8 | 158 | 152 | 97 | 91 | 98 | 101 | 99 | 107
EXPORTS | 1 | 3 | 17
EQ | 5 | 
   !CP_RD_S.D = RW & !CP_CS & !$OpTx$FX_DC$46;
   CP_RD_S.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;
    CP_RD_S.EXP  =  !AS & !AUTO_CONFIG_Z2_DONE<1> & 
	AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & A<2> & !A<3> & !A<1> & 
	!$OpTx$FX_DC$46

MACROCELL | 13 | 5 | CP_WE_QUIRK
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 1 | 10 | 16
INPUTS | 2 | CP_WE_S  | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
INPUTMC | 2 | 8 | 6 | 13 | 3
EQ | 2 | 
   CP_WE_QUIRK.D = CP_WE_S;
   CP_WE_QUIRK.CLK = SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF;

MACROCELL | 9 | 0 | LAN_A_INIT<3>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 2 | 3 | 7 | 9 | 17
INPUTS | 7 | RESET  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | D<0>.PIN  | $OpTx$FX_DC$46
INPUTMC | 5 | 0 | 15 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12
INPUTP | 2 | 263 | 4
EXPORTS | 1 | 9 | 17
EQ | 5 | 
   LAN_A_INIT<3>.D = Gnd;
   LAN_A_INIT<3>.CLK = CLK_EXT;	// GCK
   LAN_A_INIT<3>.AP = RESET;
    LAN_A_INIT<3>.EXP  =  !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<0>.PIN & !$OpTx$FX_DC$46
GLOBALS | 1 | 2 | CLK_EXT

MACROCELL | 3 | 5 | A_LAN_0_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 4
INPUTS | 3 | RESET  | Z3_A_LOW  | Z3_ADR_0
INPUTMC | 2 | 15 | 13 | 13 | 7
INPUTP | 1 | 263
EXPORTS | 1 | 3 | 4
EQ | 2 | 
   !A_LAN<0> = RESET & !Z3_A_LOW;
    A_LAN_0_OBUF.EXP  =  RESET & !Z3_ADR_0

MACROCELL | 5 | 5 | A_LAN_10_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<9>
INPUTMC | 1 | 0 | 2
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<10> = RESET & !Z3_ADR<9>;

MACROCELL | 5 | 7 | A_LAN_11_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<10>
INPUTMC | 1 | 0 | 12
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<11> = RESET & !Z3_ADR<10>;

MACROCELL | 5 | 2 | A_LAN_12_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<11>
INPUTMC | 1 | 0 | 10
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<12> = RESET & !Z3_ADR<11>;

MACROCELL | 5 | 4 | A_LAN_13_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<12>
INPUTMC | 1 | 0 | 8
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<13> = RESET & !Z3_ADR<12>;

MACROCELL | 3 | 4 | A_LAN_1_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 3
INPUTS | 8 | A<4>  | A<2>  | A<3>  | AUTO_CONFIG_Z2_DONE<0>  | BUF_D_Z2_OUT<3>  | A<1>  | BUF_D_Z2_OUT<0>  | A_LAN_0_OBUF.EXP
INPUTMC | 4 | 3 | 8 | 3 | 6 | 3 | 2 | 3 | 5
INPUTP | 4 | 97 | 101 | 99 | 107
EXPORTS | 1 | 3 | 3
IMPORTS | 1 | 3 | 5
EQ | 7 | 
   !A_LAN<1> = ;Imported pterms FB4_6
	  RESET & !Z3_ADR_0;
    A_LAN_1_OBUF.EXP  =  A<4> & !A<2>
	# !A<4> & A<3>
	# AUTO_CONFIG_Z2_DONE<0> & !A<2> & !BUF_D_Z2_OUT<3>
	# A<4> & !A<3> & !BUF_D_Z2_OUT<3>
	# !A<3> & !A<1> & !BUF_D_Z2_OUT<0>

MACROCELL | 3 | 7 | A_LAN_3_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 6
INPUTS | 10 | RESET  | LAN_A_INIT<3>  | Z3_ADR<2>  | CP_CS  | A<3>  | A<4>  | A<5>  | A<2>  | A<1>  | $OpTx$FX_DC$95
INPUTMC | 4 | 9 | 0 | 13 | 15 | 4 | 1 | 13 | 1
INPUTP | 6 | 263 | 99 | 97 | 91 | 101 | 107
EXPORTS | 1 | 3 | 6
EQ | 5 | 
   A_LAN<3> = !RESET & LAN_A_INIT<3>
	# RESET & Z3_ADR<2> & CP_CS
	# RESET & A<3> & !CP_CS;
    A_LAN_3_OBUF.EXP  =  !A<4> & A<5> & A<2> & !A<3> & !A<1> & 
	$OpTx$FX_DC$95

MACROCELL | 1 | 4 | A_LAN_6_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | RESET  | LAN_A_INIT<6>  | Z3_ADR<5>
INPUTMC | 2 | 8 | 5 | 13 | 9
INPUTP | 1 | 263
EQ | 2 | 
   A_LAN<6> = RESET & Z3_ADR<5>
	# !RESET & LAN_A_INIT<6>;

MACROCELL | 1 | 2 | A_LAN_7_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<6>
INPUTMC | 1 | 13 | 8
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<7> = RESET & !Z3_ADR<6>;

MACROCELL | 5 | 9 | A_LAN_8_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET  | Z3_ADR<7>
INPUTMC | 1 | 0 | 6
INPUTP | 1 | 263
EQ | 1 | 
   !A_LAN<8> = RESET & !Z3_ADR<7>;

MACROCELL | 5 | 13 | A_LAN_9_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 5 | 14
INPUTS | 8 | RESET  | Z3_ADR<8>  | LAN_BASEADR<1>  | A<17>.PIN  | LAN_BASEADR<2>  | A<18>.PIN  | LAN_BASEADR<3>  | A<19>.PIN
INPUTMC | 4 | 0 | 3 | 12 | 11 | 7 | 12 | 7 | 11
INPUTP | 4 | 263 | 172 | 171 | 169
EXPORTS | 1 | 5 | 14
EQ | 5 | 
   !A_LAN<9> = RESET & !Z3_ADR<8>;
    A_LAN_9_OBUF.EXP  =  LAN_BASEADR<1> & !A<17>.PIN
	# LAN_BASEADR<2> & !A<18>.PIN
	# !LAN_BASEADR<2> & A<18>.PIN
	# !LAN_BASEADR<3> & A<19>.PIN

MACROCELL | 12 | 1 | CP_RD_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | AS  | CP_RD_S
INPUTMC | 1 | 3 | 16
INPUTP | 1 | 152
EQ | 1 | 
   !CP_RD = !AS & !CP_RD_S;

MACROCELL | 10 | 16 | CP_WE_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 10 | 17
INPUTS | 12 | AS  | CP_WE_S  | CP_WE_QUIRK  | DQ_SWAP  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | DQ<7>.PIN  | DQ<15>.PIN  | LAN_SM_FSM_FFd3  | LAN_INT_ENABLE  | RW
INPUTMC | 8 | 8 | 6 | 13 | 5 | 0 | 15 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 11 | 12
INPUTP | 4 | 152 | 226 | 202 | 158
EXPORTS | 1 | 10 | 17
EQ | 7 | 
   !CP_WE = !AS & !CP_WE_S & CP_WE_QUIRK;
    CP_WE_OBUF.EXP  =  DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1 & DQ<7>.PIN
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1 & DQ<15>.PIN
	# LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & LAN_INT_ENABLE & RW

MACROCELL | 0 | 16 | IDE_R_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 0 | 17
INPUTS | 7 | IDE_BASEADR<0>  | A<16>.PIN  | IDE_BASEADR<1>  | A<17>.PIN  | IDE_BASEADR<2>  | A<18>.PIN  | DQ_SWAP.EXP
INPUTMC | 4 | 6 | 8 | 6 | 7 | 6 | 6 | 0 | 15
INPUTP | 3 | 175 | 172 | 171
EXPORTS | 1 | 0 | 17
IMPORTS | 1 | 0 | 15
EQ | 7 | 
   !IDE_R = ;Imported pterms FB1_16
	  !AS & !IDE_R_S;
    IDE_R_OBUF.EXP  =  IDE_BASEADR<0> & !A<16>.PIN
	# IDE_BASEADR<1> & !A<17>.PIN
	# !IDE_BASEADR<1> & A<17>.PIN
	# IDE_BASEADR<2> & !A<18>.PIN
	# !IDE_BASEADR<2> & A<18>.PIN

MACROCELL | 2 | 1 | IDE_W_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | AS  | IDE_W_S
INPUTMC | 1 | 3 | 14
INPUTP | 1 | 152
EQ | 1 | 
   !IDE_W = !AS & !IDE_W_S;

MACROCELL | 7 | 7 | LAN_CS_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | RESET  | LAN_CS_RST  | LAN_ACCESS
INPUTMC | 2 | 8 | 15 | 12 | 5
INPUTP | 1 | 263
EQ | 2 | 
   LAN_CS = RESET & LAN_ACCESS
	# !RESET & LAN_CS_RST;

MACROCELL | 7 | 4 | LAN_WRH_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | LAN_WR_RST  | $OpTx$FX_DC$114  | LAN_WRH_S
INPUTMC | 3 | 8 | 8 | 12 | 3 | 14 | 7
EQ | 2 | 
   LAN_WRH = LAN_WR_RST & !$OpTx$FX_DC$114
	# LAN_WRH_S & $OpTx$FX_DC$114;

MACROCELL | 12 | 13 | LAN_WRL_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | LAN_WR_RST  | $OpTx$FX_DC$114  | LAN_WRL_S
INPUTMC | 3 | 8 | 8 | 12 | 3 | 11 | 0
EQ | 2 | 
   LAN_WRL = LAN_WR_RST & !$OpTx$FX_DC$114
	# LAN_WRL_S & $OpTx$FX_DC$114;

MACROCELL | 4 | 4 | ROM_OE_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | AS  | ROM_OE_S  | AUTOBOOT_OFF
INPUTMC | 1 | 3 | 15
INPUTP | 2 | 152 | 142
EQ | 1 | 
   !ROM_OE = !AS & !ROM_OE_S & !AUTOBOOT_OFF;

MACROCELL | 7 | 9 | LAN_RD_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | LAN_RD_S  | $OpTx$FX_DC$114
INPUTMC | 2 | 15 | 11 | 12 | 3
EQ | 1 | 
   LAN_RD = LAN_RD_S & $OpTx$FX_DC$114;

MACROCELL | 13 | 13 | SLAVE_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 5 | AUTOCONFIG_Z2_ACCESS  | IDE_ACCESS  | CP_CS  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS
INPUTMC | 4 | 4 | 17 | 0 | 17 | 4 | 1 | 13 | 0
INPUTP | 1 | 152
EQ | 3 | 
   SLAVE = AS & !ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AUTOCONFIG_Z2_ACCESS & !IDE_ACCESS & CP_CS & 
	!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;

MACROCELL | 14 | 11 | ROM_B_0_OBUF$BUF10
ATTRIBUTES | 265986 | 0
INPUTS | 2 | FCS  | LAN_READY
INPUTMC | 1 | 8 | 1
INPUTP | 1 | 147
EQ | 2 | 
   DTACK = Gnd;
   DTACK.OE = !FCS & LAN_READY;

MACROCELL | 13 | 2 | ROM_B_0_OBUF$BUF2
ATTRIBUTES | 265986 | 0
INPUTS | 2 | FCS  | LAN_ACCESS
INPUTMC | 1 | 12 | 5
INPUTP | 1 | 147
EQ | 2 | 
   OVR = Gnd;
   OVR.OE = !FCS & LAN_ACCESS;

MACROCELL | 2 | 13 | ROM_B_0_OBUF$BUF8
ATTRIBUTES | 265986 | 0
INPUTS | 2 | LAN_IRQ_OUT  | LAN_INT_ENABLE
INPUTMC | 2 | 8 | 14 | 11 | 12
EQ | 2 | 
   INT_OUT = Gnd;
   INT_OUT.OE = !LAN_IRQ_OUT & LAN_INT_ENABLE;

MACROCELL | 10 | 11 | ROM_B_0_OBUF$BUF9
ATTRIBUTES | 265986 | 0
INPUTS | 1 | CP_IRQ
INPUTP | 1 | 59
EQ | 2 | 
   INT_CP_OUT = Gnd;
   INT_CP_OUT.OE = !CP_IRQ;

MACROCELL | 13 | 10 | CFOUT_OBUF
ATTRIBUTES | 396034 | 0
OUTPUTMC | 3 | 4 | 17 | 1 | 8 | 1 | 3
INPUTS | 3 | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTO_CONFIG_Z2_DONE<2>
INPUTMC | 3 | 3 | 8 | 3 | 9 | 8 | 17
EQ | 2 | 
   !CFOUT = AUTO_CONFIG_Z2_DONE<0> & AUTO_CONFIG_Z2_DONE<1> & 
	AUTO_CONFIG_Z2_DONE<2>;

MACROCELL | 4 | 1 | CP_CS_OBUF
ATTRIBUTES | 8782758 | 0
OUTPUTMC | 9 | 3 | 11 | 1 | 1 | 3 | 13 | 8 | 6 | 3 | 16 | 3 | 7 | 13 | 13 | 13 | 4 | 4 | 15
INPUTS | 7 | SHUT_UP_Z2<1>  | CP_BASEADR<7>  | A<23>.PIN  | EXP24_.EXP  | EXP25_.EXP  | AS  | RESET
INPUTMC | 4 | 1 | 10 | 6 | 9 | 4 | 0 | 4 | 2
INPUTP | 3 | 161 | 152 | 263
IMPORTS | 2 | 4 | 0 | 4 | 2
EQ | 22 | 
   CP_CS.D = SHUT_UP_Z2<1>
	# CP_BASEADR<7> & !A<23>.PIN
	# !CP_BASEADR<7> & A<23>.PIN
;Imported pterms FB5_1
	# CP_BASEADR<4> & !A<20>.PIN
	# CP_BASEADR<5> & !A<21>.PIN
	# !CP_BASEADR<5> & A<21>.PIN
	# CP_BASEADR<6> & !A<22>.PIN
	# !CP_BASEADR<6> & A<22>.PIN
;Imported pterms FB5_3
	# CP_BASEADR<2> & !A<18>.PIN
	# !CP_BASEADR<2> & A<18>.PIN
	# CP_BASEADR<3> & !A<19>.PIN
	# !CP_BASEADR<3> & A<19>.PIN
	# !CP_BASEADR<4> & A<20>.PIN
;Imported pterms FB5_4
	# CP_BASEADR<0> & !A<16>.PIN
	# !CP_BASEADR<0> & A<16>.PIN
	# CP_BASEADR<1> & !A<17>.PIN
	# !CP_BASEADR<1> & A<17>.PIN;
   CP_CS.CLK = !AS;
   CP_CS.AP = !RESET;

MACROCELL | 0 | 11 | IDE_A_0_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A<9>.PIN
INPUTP | 1 | 108
EQ | 1 | 
   IDE_A<0> = A<9>.PIN;

MACROCELL | 0 | 14 | IDE_A_1_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A<10>.PIN
INPUTP | 1 | 112
EQ | 1 | 
   IDE_A<1> = A<10>.PIN;

MACROCELL | 0 | 13 | IDE_A_2_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A<11>.PIN
INPUTP | 1 | 114
EQ | 1 | 
   IDE_A<2> = A<11>.PIN;

MACROCELL | 0 | 7 | IDE_CS_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A<12>.PIN
INPUTP | 1 | 115
EQ | 1 | 
   IDE_CS<0> = !A<12>.PIN;

MACROCELL | 0 | 9 | IDE_CS_1_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A<13>.PIN
INPUTP | 1 | 123
EQ | 1 | 
   IDE_CS<1> = !A<13>.PIN;

MACROCELL | 13 | 14 | ROM_B_0_OBUF$BUF1
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 | 
   OWN = Gnd;
   OWN.OE = Gnd;

MACROCELL | 15 | 9 | ROM_B_0_OBUF$BUF3
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 15 | 10
INPUTS | 3 | DQ_SWAP  | DQ<0>.PIN  | DQ<8>.PIN
INPUTMC | 1 | 0 | 15
INPUTP | 2 | 217 | 231
EXPORTS | 1 | 15 | 10
EQ | 4 | 
   MTACK = Gnd;
   MTACK.OE = Gnd;
    ROM_B_0_OBUF$BUF3.EXP  =  DQ_SWAP & DQ<0>.PIN
	# !DQ_SWAP & DQ<8>.PIN

MACROCELL | 11 | 1 | ROM_B_0_OBUF$BUF4
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 11 | 0
INPUTS | 4 | UDS  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 3 | 15 | 12 | 15 | 15 | 15 | 16
INPUTP | 1 | 155
EXPORTS | 1 | 11 | 0
EQ | 4 | 
   LAN_CFG<4> = Gnd;
   LAN_CFG<4>.OE = Gnd;
    ROM_B_0_OBUF$BUF4.EXP  =  !UDS & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	LAN_SM_FSM_FFd1

MACROCELL | 1 | 7 | ROM_B_0_OBUF$BUF5
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 | 
   LAN_CFG<3> = Gnd;
   LAN_CFG<3>.OE = Gnd;

MACROCELL | 5 | 1 | ROM_B_0_OBUF$BUF6
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 5 | 0
INPUTS | 4 | LAN_BASEADR<0>  | A<16>.PIN  | LAN_BASEADR<1>  | A<17>.PIN
INPUTMC | 2 | 12 | 14 | 12 | 11
INPUTP | 2 | 175 | 172
EXPORTS | 1 | 5 | 0
EQ | 5 | 
   LAN_CFG<2> = Gnd;
   LAN_CFG<2>.OE = Gnd;
    ROM_B_0_OBUF$BUF6.EXP  =  LAN_BASEADR<0> & !A<16>.PIN
	# !LAN_BASEADR<0> & A<16>.PIN
	# !LAN_BASEADR<1> & A<17>.PIN

MACROCELL | 1 | 5 | ROM_B_0_OBUF$BUF7
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 | 
   LAN_CFG<1> = Gnd;
   LAN_CFG<1>.OE = Gnd;

MACROCELL | 10 | 13 | ROM_B_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   ROM_B<1> = Gnd;

MACROCELL | 2 | 14 | ROM_B_0_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   ROM_B<0> = Gnd;

MACROCELL | 13 | 0 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 24 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 13 | 13 | 4 | 8 | 14 | 8 | 4 | 12
INPUTS | 2 | FCS  | LAN_ACCESS
INPUTMC | 1 | 12 | 5
INPUTP | 1 | 147
EQ | 1 | 
   ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST = !FCS & LAN_ACCESS;

MACROCELL | 13 | 3 | SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
ATTRIBUTES | 133888 | 0
OUTPUTMC | 52 | 3 | 8 | 3 | 9 | 8 | 17 | 1 | 17 | 1 | 15 | 1 | 12 | 6 | 17 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 6 | 9 | 6 | 8 | 6 | 7 | 6 | 6 | 6 | 5 | 6 | 3 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 7 | 17 | 7 | 16 | 12 | 12 | 7 | 15 | 7 | 14 | 7 | 13 | 12 | 11 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 12 | 10 | 12 | 9 | 12 | 8 | 3 | 10 | 12 | 4 | 1 | 10 | 1 | 8 | 6 | 1 | 3 | 0 | 13 | 17 | 12 | 6 | 3 | 12 | 3 | 14 | 3 | 15 | 8 | 6 | 3 | 16 | 13 | 5
INPUTS | 2 | C1  | C3
INPUTP | 2 | 188 | 187
EQ | 2 | 
   SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF = C1
	$ C3;

MACROCELL | 5 | 12 | $OpTx$FX_DC$46
ATTRIBUTES | 133888 | 0
OUTPUTMC | 40 | 1 | 17 | 1 | 15 | 1 | 12 | 15 | 11 | 10 | 15 | 9 | 17 | 9 | 15 | 15 | 13 | 11 | 17 | 14 | 0 | 14 | 2 | 11 | 16 | 11 | 13 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 1 | 14 | 4 | 11 | 14 | 9 | 12 | 11 | 12 | 1 | 10 | 1 | 8 | 15 | 12 | 8 | 6 | 3 | 16 | 1 | 0 | 13 | 1 | 1 | 3 | 1 | 6 | 9 | 6 | 14 | 8 | 9 | 0 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 0 | 14 | 5 | 14 | 6 | 14 | 17
INPUTS | 2 | UDS  | LDS
INPUTP | 2 | 155 | 157
EQ | 1 | 
   $OpTx$FX_DC$46 = UDS & LDS;

MACROCELL | 1 | 0 | $OpTx$FX_DC$74
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 6 | 17 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 6 | 9
INPUTS | 12 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<2>  | A<3>  | A<1>  | $OpTx$FX_DC$46  | BUF_D_Z2_OUT<0>
INPUTMC | 5 | 3 | 8 | 3 | 9 | 4 | 17 | 5 | 12 | 3 | 2
INPUTP | 7 | 152 | 158 | 97 | 91 | 101 | 99 | 107
EQ | 3 | 
   $OpTx$FX_DC$74 = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	!AUTO_CONFIG_Z2_DONE<1> & AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & !A<2> & 
	A<3> & !A<1> & !$OpTx$FX_DC$46 & !BUF_D_Z2_OUT<0>;

MACROCELL | 3 | 2 | BUF_D_Z2_OUT<0>
ATTRIBUTES | 133888 | 0
OUTPUTMC | 6 | 6 | 1 | 3 | 3 | 1 | 0 | 1 | 3 | 3 | 4 | 3 | 17
INPUTS | 9 | A<4>  | A<5>  | A<3>  | A<1>  | $OpTx$FX_DC$95  | A<2>  | AUTO_CONFIG_Z2_DONE<0>  | D_0_IOBUFE.EXP  | BUF_D_Z2_OUT<2>.EXP
INPUTMC | 4 | 13 | 1 | 3 | 8 | 3 | 1 | 3 | 3
INPUTP | 5 | 97 | 91 | 99 | 107 | 101
IMPORTS | 2 | 3 | 1 | 3 | 3
EQ | 16 | 
   BUF_D_Z2_OUT<0> = !AUTO_CONFIG_Z2_DONE<0> & !A<4> & A<2> & !A<3> & 
	$OpTx$FX_DC$95
	# A<4> & !A<5> & A<3> & A<1> & $OpTx$FX_DC$95
	# !A<4> & A<5> & A<2> & !A<3> & $OpTx$FX_DC$95
	# !A<4> & A<5> & A<2> & A<1> & $OpTx$FX_DC$95
	# !A<5> & !A<2> & A<3> & !A<1> & $OpTx$FX_DC$95
;Imported pterms FB4_2
	# !AUTO_CONFIG_Z2_DONE<0> & !A<4> & !A<5> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95
	# !AUTO_CONFIG_Z2_DONE<0> & !A<5> & A<2> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95
;Imported pterms FB4_4
	# !AUTO_CONFIG_Z2_DONE<1> & !A<4> & !A<5> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95
	# !AUTO_CONFIG_Z2_DONE<1> & !A<5> & A<2> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95;

MACROCELL | 13 | 1 | $OpTx$FX_DC$95
ATTRIBUTES | 133888 | 0
OUTPUTMC | 6 | 3 | 0 | 3 | 2 | 3 | 3 | 3 | 6 | 3 | 1 | 3 | 7
INPUTS | 4 | AS  | AUTOCONFIG_Z2_ACCESS  | A<6>  | $OpTx$FX_DC$46
INPUTMC | 2 | 4 | 17 | 5 | 12
INPUTP | 2 | 152 | 98
EQ | 2 | 
   $OpTx$FX_DC$95 = !AS & AUTOCONFIG_Z2_ACCESS & !A<6> & 
	!$OpTx$FX_DC$46;

MACROCELL | 1 | 3 | $OpTx$FX_DC$73
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 6 | 8 | 6 | 7 | 6 | 6 | 6 | 5 | 6 | 3 | 12 | 17 | 12 | 16 | 12 | 15
INPUTS | 13 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<2>  | A<3>  | A<1>  | CFOUT  | $OpTx$FX_DC$46  | BUF_D_Z2_OUT<0>
INPUTMC | 6 | 3 | 8 | 3 | 9 | 4 | 17 | 13 | 10 | 5 | 12 | 3 | 2
INPUTP | 7 | 152 | 158 | 97 | 91 | 101 | 99 | 107
EQ | 3 | 
   $OpTx$FX_DC$73 = !AS & AUTO_CONFIG_Z2_DONE<0> & 
	AUTO_CONFIG_Z2_DONE<1> & AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & !A<2> & 
	A<3> & !A<1> & CFOUT & !$OpTx$FX_DC$46 & !BUF_D_Z2_OUT<0>;

MACROCELL | 1 | 6 | $OpTx$FX_DC$72
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 12 | 14 | 12 | 11 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 12 | 10 | 12 | 4
INPUTS | 11 | AS  | AUTO_CONFIG_Z2_DONE<0>  | AUTOCONFIG_Z2_ACCESS  | RW  | A<4>  | A<5>  | A<6>  | A<2>  | A<3>  | A<1>  | $OpTx$FX_DC$46
INPUTMC | 3 | 3 | 8 | 4 | 17 | 5 | 12
INPUTP | 8 | 152 | 158 | 97 | 91 | 98 | 101 | 99 | 107
EQ | 3 | 
   $OpTx$FX_DC$72 = !AS & !AUTO_CONFIG_Z2_DONE<0> & 
	AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & !A<2> & A<3> & !A<1> & 
	!$OpTx$FX_DC$46;

MACROCELL | 3 | 17 | $OpTx$FX_DC$77
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 7 | 17 | 7 | 16 | 12 | 12 | 7 | 15 | 7 | 14 | 7 | 13 | 12 | 9 | 12 | 8 | 3 | 0
INPUTS | 10 | A<4>  | A<2>  | BUF_D_Z2_OUT<3>  | BUF_D_Z2_OUT<0>  | A<3>  | A<1>  | BUF_D_Z2_OUT<2>  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | CP_RD_S.EXP
INPUTMC | 6 | 3 | 6 | 3 | 2 | 3 | 3 | 3 | 8 | 3 | 9 | 3 | 16
INPUTP | 4 | 97 | 101 | 99 | 107
EXPORTS | 1 | 3 | 0
IMPORTS | 1 | 3 | 16
EQ | 10 | 
   $OpTx$FX_DC$77 = ;Imported pterms FB4_17
	  !AS & !AUTO_CONFIG_Z2_DONE<1> & 
	AUTOCONFIG_Z2_ACCESS & !RW & !A<4> & !A<5> & A<6> & A<2> & !A<3> & !A<1> & 
	!$OpTx$FX_DC$46;
    $OpTx$FX_DC$77.EXP  =  A<4> & !A<2> & !BUF_D_Z2_OUT<3>
	# A<4> & BUF_D_Z2_OUT<0> & !BUF_D_Z2_OUT<3>
	# !A<4> & A<3> & !A<1>
	# !A<4> & A<2> & !BUF_D_Z2_OUT<0> & BUF_D_Z2_OUT<2>
	# AUTO_CONFIG_Z2_DONE<0> & AUTO_CONFIG_Z2_DONE<1> & 
	A<4> & A<1> & !BUF_D_Z2_OUT<0>

MACROCELL | 13 | 4 | DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10
INPUTS | 4 | $OpTx$FX_DC$78  | AS  | RW  | CP_CS
INPUTMC | 2 | 9 | 8 | 4 | 1
INPUTP | 2 | 152 | 158
EQ | 2 | 
   DQ_8_IOBUFE/DQ_8_IOBUFE_TRST = $OpTx$FX_DC$78
	# !AS & !RW & !CP_CS;

MACROCELL | 9 | 8 | $OpTx$FX_DC$78
ATTRIBUTES | 133888 | 0
OUTPUTMC | 17 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 13 | 4
INPUTS | 3 | RESET  | Z3_DATA<6>/Z3_DATA<6>_TRST  | $OpTx$FX_DC$59
INPUTMC | 2 | 4 | 8 | 14 | 8
INPUTP | 1 | 263
EQ | 2 | 
   $OpTx$FX_DC$78 = !RESET
	# !Z3_DATA<6>/Z3_DATA<6>_TRST & !$OpTx$FX_DC$59;

MACROCELL | 4 | 8 | Z3_DATA<6>/Z3_DATA<6>_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 31 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 9 | 8 | 4 | 15 | 4 | 10
INPUTS | 2 | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
INPUTMC | 1 | 13 | 0
INPUTP | 1 | 158
EQ | 1 | 
   Z3_DATA<6>/Z3_DATA<6>_TRST = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;

MACROCELL | 14 | 8 | $OpTx$FX_DC$59
ATTRIBUTES | 133888 | 0
OUTPUTMC | 18 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 8 | 0 | 9 | 8
INPUTS | 3 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | $OpTx$FX_DC$46  | $OpTx$FX_DC$49
INPUTMC | 3 | 13 | 0 | 5 | 12 | 2 | 17
EQ | 2 | 
   $OpTx$FX_DC$59 = !ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# $OpTx$FX_DC$46 & $OpTx$FX_DC$49;

MACROCELL | 2 | 17 | $OpTx$FX_DC$49
ATTRIBUTES | 133888 | 0
OUTPUTMC | 5 | 15 | 11 | 15 | 15 | 14 | 8 | 14 | 7 | 15 | 14
INPUTS | 2 | DS1  | DS0
INPUTP | 2 | 148 | 170
EQ | 1 | 
   $OpTx$FX_DC$49 = DS1 & DS0;

MACROCELL | 4 | 15 | D_9_IOBUFE/D_9_IOBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11
INPUTS | 5 | Z3_DATA<6>/Z3_DATA<6>_TRST  | AS  | RW  | CP_CS  | AUTOCONFIG_Z2_ACCESS
INPUTMC | 3 | 4 | 8 | 4 | 1 | 4 | 17
INPUTP | 2 | 152 | 158
EQ | 3 | 
   D_9_IOBUFE/D_9_IOBUFE_TRST = Z3_DATA<6>/Z3_DATA<6>_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & RW
	# !AS & RW & !CP_CS;

MACROCELL | 4 | 10 | $OpTx$FX_SC$85
ATTRIBUTES | 133888 | 0
OUTPUTMC | 12 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11
INPUTS | 4 | AS  | AUTOCONFIG_Z2_ACCESS  | RW  | Z3_DATA<6>/Z3_DATA<6>_TRST
INPUTMC | 2 | 4 | 17 | 4 | 8
INPUTP | 2 | 152 | 158
EQ | 2 | 
   $OpTx$FX_SC$85 = !AS & AUTOCONFIG_Z2_ACCESS & RW & 
	!Z3_DATA<6>/Z3_DATA<6>_TRST;

MACROCELL | 4 | 12 | $OpTx$FX_DC$86
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11
INPUTS | 4 | RW  | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST  | AS  | AUTOCONFIG_Z2_ACCESS
INPUTMC | 2 | 13 | 0 | 4 | 17
INPUTP | 2 | 158 | 152
EQ | 2 | 
   $OpTx$FX_DC$86 = RW & ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
	# !AS & AUTOCONFIG_Z2_ACCESS & RW;

MACROCELL | 5 | 16 | Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 0 | 15 | 12 | 5
INPUTS | 8 | D<9>.PIN  | LAN_BASEADR<9>  | D<8>.PIN  | LAN_BASEADR<8>  | D<11>.PIN  | LAN_BASEADR<11>  | EXP29_.EXP  | EXP30_.EXP
INPUTMC | 5 | 12 | 8 | 12 | 9 | 7 | 16 | 5 | 15 | 5 | 17
INPUTP | 3 | 73 | 32 | 77
IMPORTS | 2 | 5 | 15 | 5 | 17
EQ | 38 | 
   Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2 = D<8>.PIN & !LAN_BASEADR<8>
	# !D<8>.PIN & LAN_BASEADR<8>
	# D<9>.PIN & !LAN_BASEADR<9>
	# !D<9>.PIN & LAN_BASEADR<9>
	# !D<11>.PIN & LAN_BASEADR<11>
;Imported pterms FB6_16
	# D<10>.PIN & !LAN_BASEADR<10>
	# !D<10>.PIN & LAN_BASEADR<10>
	# D<11>.PIN & !LAN_BASEADR<11>
	# D<15>.PIN & !LAN_BASEADR<15>
	# !D<15>.PIN & LAN_BASEADR<15>
;Imported pterms FB6_15
	# D<12>.PIN & !LAN_BASEADR<12>
	# LAN_BASEADR<6> & !A<22>.PIN
	# !LAN_BASEADR<6> & A<22>.PIN
	# LAN_BASEADR<7> & !A<23>.PIN
	# !LAN_BASEADR<7> & A<23>.PIN
;Imported pterms FB6_14
	# LAN_BASEADR<1> & !A<17>.PIN
	# LAN_BASEADR<2> & !A<18>.PIN
	# !LAN_BASEADR<2> & A<18>.PIN
	# !LAN_BASEADR<3> & A<19>.PIN
;Imported pterms FB6_18
	# !D<12>.PIN & LAN_BASEADR<12>
	# D<13>.PIN & !LAN_BASEADR<13>
	# !D<13>.PIN & LAN_BASEADR<13>
	# D<14>.PIN & !LAN_BASEADR<14>
	# !D<14>.PIN & LAN_BASEADR<14>
;Imported pterms FB6_1
	# LAN_BASEADR<3> & !A<19>.PIN
	# LAN_BASEADR<4> & !A<20>.PIN
	# !LAN_BASEADR<4> & A<20>.PIN
	# LAN_BASEADR<5> & !A<21>.PIN
	# !LAN_BASEADR<5> & A<21>.PIN
;Imported pterms FB6_2
	# LAN_BASEADR<0> & !A<16>.PIN
	# !LAN_BASEADR<0> & A<16>.PIN
	# !LAN_BASEADR<1> & A<17>.PIN;

MACROCELL | 14 | 6 | BUF_LAN_READY
ATTRIBUTES | 133888 | 0
OUTPUTMC | 7 | 15 | 16 | 10 | 15 | 8 | 1 | 15 | 13 | 15 | 12 | 15 | 17 | 14 | 5
INPUTS | 11 | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd1  | DQ_SWAP  | A<22>.PIN  | $OpTx$FX_SC$67  | D<14>.PIN  | $OpTx$FX_DC$46  | D<6>.PIN  | LAN_WRH_S.EXP
INPUTMC | 8 | 15 | 15 | 10 | 15 | 15 | 12 | 15 | 16 | 0 | 15 | 9 | 6 | 5 | 12 | 14 | 7
INPUTP | 3 | 162 | 81 | 26
EXPORTS | 1 | 14 | 5
IMPORTS | 1 | 14 | 7
EQ | 13 | 
   BUF_LAN_READY = LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1
;Imported pterms FB15_8
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!$OpTx$FX_DC$49
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & 
	!LAN_SM_FSM_FFd3;
    BUF_LAN_READY.EXP  =  DQ_SWAP & A<22>.PIN & $OpTx$FX_SC$67
	# D<14>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# !DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<6>.PIN & !$OpTx$FX_DC$46

MACROCELL | 9 | 3 | $OpTx$FX_DC$65
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 9 | 17 | 9 | 15 | 15 | 14 | 14 | 0 | 14 | 1 | 14 | 2 | 11 | 17 | 11 | 16 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 4 | 14 | 5 | 11 | 14 | 9 | 12 | 11 | 13
INPUTS | 3 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1
INPUTMC | 3 | 15 | 12 | 15 | 15 | 15 | 16
EQ | 2 | 
   $OpTx$FX_DC$65 = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1;

MACROCELL | 9 | 6 | $OpTx$FX_SC$67
ATTRIBUTES | 133888 | 0
OUTPUTMC | 19 | 9 | 17 | 9 | 15 | 15 | 14 | 14 | 0 | 14 | 1 | 14 | 2 | 11 | 17 | 11 | 16 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 4 | 14 | 5 | 11 | 14 | 9 | 12 | 11 | 13 | 11 | 0 | 14 | 6 | 14 | 17
INPUTS | 5 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46
INPUTMC | 5 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 5 | 12
EQ | 4 | 
   $OpTx$FX_SC$67 = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & LAN_SM_FSM_FFd3
	# !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & $OpTx$FX_DC$46;

MACROCELL | 14 | 9 | $OpTx$FX_DC$106
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 11 | 12 | 11 | 11
INPUTS | 6 | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | RW  | LAN_SM_RST
INPUTMC | 5 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 8 | 0
INPUTP | 1 | 158
EQ | 2 | 
   $OpTx$FX_DC$106 = LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3 & !RW & !LAN_SM_RST;

MACROCELL | 14 | 10 | $OpTx$FX_DC$99
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 10 | 17
INPUTS | 3 | LAN_SM_FSM_FFd1  | LAN_SM_FSM_FFd3  | RW
INPUTMC | 2 | 15 | 16 | 10 | 15
INPUTP | 1 | 158
EQ | 1 | 
   $OpTx$FX_DC$99 = !LAN_SM_FSM_FFd1 & !LAN_SM_FSM_FFd3 & RW;

MACROCELL | 3 | 3 | BUF_D_Z2_OUT<2>
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 3 | 0 | 13 | 17 | 3 | 17 | 3 | 2
INPUTS | 10 | $OpTx$FX_DC$95  | BUF_D_Z2_OUT<0>  | BUF_D_Z2_OUT<3>  | A<5>  | AUTO_CONFIG_Z2_DONE<1>  | A<4>  | A<3>  | A<1>  | A<2>  | A_LAN_1_OBUF.EXP
INPUTMC | 5 | 13 | 1 | 3 | 2 | 3 | 6 | 3 | 9 | 3 | 4
INPUTP | 5 | 91 | 97 | 99 | 107 | 101
EXPORTS | 1 | 3 | 2
IMPORTS | 1 | 3 | 4
EQ | 13 | 
   BUF_D_Z2_OUT<2> = !$OpTx$FX_DC$95
	# A<5> & !BUF_D_Z2_OUT<0>
	# BUF_D_Z2_OUT<0> & BUF_D_Z2_OUT<3>
;Imported pterms FB4_5
	# A<4> & !A<2>
	# !A<4> & A<3>
	# AUTO_CONFIG_Z2_DONE<0> & !A<2> & !BUF_D_Z2_OUT<3>
	# A<4> & !A<3> & !BUF_D_Z2_OUT<3>
	# !A<3> & !A<1> & !BUF_D_Z2_OUT<0>;
    BUF_D_Z2_OUT<2>.EXP  =  !AUTO_CONFIG_Z2_DONE<1> & !A<4> & !A<5> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95
	# !AUTO_CONFIG_Z2_DONE<1> & !A<5> & A<2> & !A<3> & 
	!A<1> & $OpTx$FX_DC$95

MACROCELL | 3 | 6 | BUF_D_Z2_OUT<3>
ATTRIBUTES | 133888 | 0
OUTPUTMC | 5 | 3 | 0 | 12 | 6 | 3 | 3 | 3 | 4 | 3 | 17
INPUTS | 9 | A<4>  | A<5>  | A<2>  | A<1>  | $OpTx$FX_DC$95  | A<3>  | AUTO_CONFIG_Z2_DONE<0>  | AUTO_CONFIG_Z2_DONE<1>  | A_LAN_3_OBUF.EXP
INPUTMC | 4 | 13 | 1 | 3 | 8 | 3 | 9 | 3 | 7
INPUTP | 5 | 97 | 91 | 101 | 107 | 99
IMPORTS | 1 | 3 | 7
EQ | 11 | 
   BUF_D_Z2_OUT<3> = !AUTO_CONFIG_Z2_DONE<0> & !A<5> & !A<3> & A<1> & 
	$OpTx$FX_DC$95
	# !AUTO_CONFIG_Z2_DONE<1> & !A<5> & !A<3> & A<1> & 
	$OpTx$FX_DC$95
	# A<4> & !A<5> & A<2> & A<1> & $OpTx$FX_DC$95
	# !A<5> & !A<2> & !A<3> & A<1> & $OpTx$FX_DC$95
	# A<4> & !A<5> & !A<2> & A<3> & !A<1> & 
	$OpTx$FX_DC$95
;Imported pterms FB4_8
	# !A<4> & A<5> & A<2> & !A<3> & !A<1> & 
	$OpTx$FX_DC$95;

MACROCELL | 8 | 7 | BUF_LAN_D_INIT<1>
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 8 | 5 | 8 | 4 | 8 | 3
INPUTS | 3 | LAN_RST_SM_FSM_FFd3  | LAN_RST_SM_FSM_FFd2  | LAN_RST_SM_FSM_FFd1
INPUTMC | 3 | 8 | 9 | 8 | 11 | 8 | 12
EQ | 2 | 
   BUF_LAN_D_INIT<1> = LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd1
	# !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2;

MACROCELL | 12 | 3 | $OpTx$FX_DC$114
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 7 | 4 | 12 | 13 | 7 | 9
INPUTS | 2 | RESET  | FCS
INPUTP | 2 | 263 | 147
EQ | 1 | 
   $OpTx$FX_DC$114 = RESET & !FCS;

MACROCELL | 0 | 0 | EXP22_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 17
INPUTS | 7 | IDE_BASEADR<0>  | A<16>.PIN  | IDE_BASEADR<6>  | A<22>.PIN  | IDE_BASEADR<7>  | A<23>.PIN  | EXP23_.EXP
INPUTMC | 4 | 6 | 8 | 12 | 16 | 12 | 15 | 0 | 1
INPUTP | 3 | 175 | 162 | 161
EXPORTS | 1 | 0 | 17
IMPORTS | 1 | 0 | 1
EQ | 10 | 
       EXP22_.EXP  =  !IDE_BASEADR<0> & A<16>.PIN
	# IDE_BASEADR<6> & !A<22>.PIN
	# !IDE_BASEADR<6> & A<22>.PIN
	# IDE_BASEADR<7> & !A<23>.PIN
	# !IDE_BASEADR<7> & A<23>.PIN
;Imported pterms FB1_2
	# IDE_BASEADR<4> & !A<20>.PIN
	# !IDE_BASEADR<4> & A<20>.PIN
	# IDE_BASEADR<5> & !A<21>.PIN
	# !IDE_BASEADR<5> & A<21>.PIN

MACROCELL | 0 | 1 | EXP23_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 0
INPUTS | 4 | IDE_BASEADR<4>  | A<20>.PIN  | IDE_BASEADR<5>  | A<21>.PIN
INPUTMC | 2 | 6 | 3 | 12 | 17
INPUTP | 2 | 167 | 163
EXPORTS | 1 | 0 | 0
EQ | 4 | 
       EXP23_.EXP  =  IDE_BASEADR<4> & !A<20>.PIN
	# !IDE_BASEADR<4> & A<20>.PIN
	# IDE_BASEADR<5> & !A<21>.PIN
	# !IDE_BASEADR<5> & A<21>.PIN

MACROCELL | 4 | 0 | EXP24_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 1
INPUTS | 6 | CP_BASEADR<4>  | A<20>.PIN  | CP_BASEADR<5>  | A<21>.PIN  | CP_BASEADR<6>  | A<22>.PIN
INPUTMC | 3 | 6 | 13 | 6 | 12 | 6 | 10
INPUTP | 3 | 167 | 163 | 162
EXPORTS | 1 | 4 | 1
EQ | 5 | 
       EXP24_.EXP  =  CP_BASEADR<4> & !A<20>.PIN
	# CP_BASEADR<5> & !A<21>.PIN
	# !CP_BASEADR<5> & A<21>.PIN
	# CP_BASEADR<6> & !A<22>.PIN
	# !CP_BASEADR<6> & A<22>.PIN

MACROCELL | 4 | 2 | EXP25_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 1
INPUTS | 7 | CP_BASEADR<2>  | A<18>.PIN  | CP_BASEADR<3>  | A<19>.PIN  | CP_BASEADR<4>  | A<20>.PIN  | EXP26_.EXP
INPUTMC | 4 | 6 | 15 | 6 | 14 | 6 | 13 | 4 | 3
INPUTP | 3 | 171 | 169 | 167
EXPORTS | 1 | 4 | 1
IMPORTS | 1 | 4 | 3
EQ | 10 | 
       EXP25_.EXP  =  CP_BASEADR<2> & !A<18>.PIN
	# !CP_BASEADR<2> & A<18>.PIN
	# CP_BASEADR<3> & !A<19>.PIN
	# !CP_BASEADR<3> & A<19>.PIN
	# !CP_BASEADR<4> & A<20>.PIN
;Imported pterms FB5_4
	# CP_BASEADR<0> & !A<16>.PIN
	# !CP_BASEADR<0> & A<16>.PIN
	# CP_BASEADR<1> & !A<17>.PIN
	# !CP_BASEADR<1> & A<17>.PIN

MACROCELL | 4 | 3 | EXP26_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 2
INPUTS | 4 | CP_BASEADR<0>  | A<16>.PIN  | CP_BASEADR<1>  | A<17>.PIN
INPUTMC | 2 | 6 | 17 | 6 | 16
INPUTP | 2 | 175 | 172
EXPORTS | 1 | 4 | 2
EQ | 4 | 
       EXP26_.EXP  =  CP_BASEADR<0> & !A<16>.PIN
	# !CP_BASEADR<0> & A<16>.PIN
	# CP_BASEADR<1> & !A<17>.PIN
	# !CP_BASEADR<1> & A<17>.PIN

MACROCELL | 5 | 0 | EXP27_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 17
INPUTS | 7 | LAN_BASEADR<3>  | A<19>.PIN  | LAN_BASEADR<4>  | A<20>.PIN  | LAN_BASEADR<5>  | A<21>.PIN  | ROM_B_0_OBUF$BUF6.EXP
INPUTMC | 4 | 7 | 11 | 7 | 10 | 7 | 8 | 5 | 1
INPUTP | 3 | 169 | 167 | 163
EXPORTS | 1 | 5 | 17
IMPORTS | 1 | 5 | 1
EQ | 9 | 
       EXP27_.EXP  =  LAN_BASEADR<3> & !A<19>.PIN
	# LAN_BASEADR<4> & !A<20>.PIN
	# !LAN_BASEADR<4> & A<20>.PIN
	# LAN_BASEADR<5> & !A<21>.PIN
	# !LAN_BASEADR<5> & A<21>.PIN
;Imported pterms FB6_2
	# LAN_BASEADR<0> & !A<16>.PIN
	# !LAN_BASEADR<0> & A<16>.PIN
	# !LAN_BASEADR<1> & A<17>.PIN

MACROCELL | 5 | 14 | EXP28_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 15
INPUTS | 7 | D<12>.PIN  | LAN_BASEADR<12>  | LAN_BASEADR<6>  | A<22>.PIN  | LAN_BASEADR<7>  | A<23>.PIN  | A_LAN_9_OBUF.EXP
INPUTMC | 4 | 12 | 12 | 7 | 6 | 12 | 10 | 5 | 13
INPUTP | 3 | 78 | 162 | 161
EXPORTS | 1 | 5 | 15
IMPORTS | 1 | 5 | 13
EQ | 10 | 
       EXP28_.EXP  =  D<12>.PIN & !LAN_BASEADR<12>
	# LAN_BASEADR<6> & !A<22>.PIN
	# !LAN_BASEADR<6> & A<22>.PIN
	# LAN_BASEADR<7> & !A<23>.PIN
	# !LAN_BASEADR<7> & A<23>.PIN
;Imported pterms FB6_14
	# LAN_BASEADR<1> & !A<17>.PIN
	# LAN_BASEADR<2> & !A<18>.PIN
	# !LAN_BASEADR<2> & A<18>.PIN
	# !LAN_BASEADR<3> & A<19>.PIN

MACROCELL | 5 | 15 | EXP29_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 16
INPUTS | 7 | D<10>.PIN  | LAN_BASEADR<10>  | D<11>.PIN  | LAN_BASEADR<11>  | D<15>.PIN  | LAN_BASEADR<15>  | EXP28_.EXP
INPUTMC | 4 | 7 | 17 | 7 | 16 | 7 | 13 | 5 | 14
INPUTP | 3 | 74 | 77 | 89
EXPORTS | 1 | 5 | 16
IMPORTS | 1 | 5 | 14
EQ | 16 | 
       EXP29_.EXP  =  D<10>.PIN & !LAN_BASEADR<10>
	# !D<10>.PIN & LAN_BASEADR<10>
	# D<11>.PIN & !LAN_BASEADR<11>
	# D<15>.PIN & !LAN_BASEADR<15>
	# !D<15>.PIN & LAN_BASEADR<15>
;Imported pterms FB6_15
	# D<12>.PIN & !LAN_BASEADR<12>
	# LAN_BASEADR<6> & !A<22>.PIN
	# !LAN_BASEADR<6> & A<22>.PIN
	# LAN_BASEADR<7> & !A<23>.PIN
	# !LAN_BASEADR<7> & A<23>.PIN
;Imported pterms FB6_14
	# LAN_BASEADR<1> & !A<17>.PIN
	# LAN_BASEADR<2> & !A<18>.PIN
	# !LAN_BASEADR<2> & A<18>.PIN
	# !LAN_BASEADR<3> & A<19>.PIN

MACROCELL | 5 | 17 | EXP30_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 16
INPUTS | 7 | D<12>.PIN  | LAN_BASEADR<12>  | D<13>.PIN  | LAN_BASEADR<13>  | D<14>.PIN  | LAN_BASEADR<14>  | EXP27_.EXP
INPUTMC | 4 | 12 | 12 | 7 | 15 | 7 | 14 | 5 | 0
INPUTP | 3 | 78 | 80 | 81
EXPORTS | 1 | 5 | 16
IMPORTS | 1 | 5 | 0
EQ | 15 | 
       EXP30_.EXP  =  !D<12>.PIN & LAN_BASEADR<12>
	# D<13>.PIN & !LAN_BASEADR<13>
	# !D<13>.PIN & LAN_BASEADR<13>
	# D<14>.PIN & !LAN_BASEADR<14>
	# !D<14>.PIN & LAN_BASEADR<14>
;Imported pterms FB6_1
	# LAN_BASEADR<3> & !A<19>.PIN
	# LAN_BASEADR<4> & !A<20>.PIN
	# !LAN_BASEADR<4> & A<20>.PIN
	# LAN_BASEADR<5> & !A<21>.PIN
	# !LAN_BASEADR<5> & A<21>.PIN
;Imported pterms FB6_2
	# LAN_BASEADR<0> & !A<16>.PIN
	# !LAN_BASEADR<0> & A<16>.PIN
	# !LAN_BASEADR<1> & A<17>.PIN

MACROCELL | 14 | 17 | EXP31_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 14 | 0
INPUTS | 9 | DQ_SWAP  | A<12>.PIN  | $OpTx$FX_SC$67  | D<12>.PIN  | LAN_SM_FSM_FFd2  | LAN_SM_FSM_FFd4  | LAN_SM_FSM_FFd3  | $OpTx$FX_DC$46  | D<4>.PIN
INPUTMC | 6 | 0 | 15 | 9 | 6 | 15 | 12 | 15 | 15 | 10 | 15 | 5 | 12
INPUTP | 3 | 115 | 78 | 38
EXPORTS | 1 | 14 | 0
EQ | 5 | 
       EXP31_.EXP  =  DQ_SWAP & A<12>.PIN & $OpTx$FX_SC$67
	# D<12>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd2 & 
	!LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$46
	# DQ_SWAP & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd4 & 
	!LAN_SM_FSM_FFd3 & D<4>.PIN & !$OpTx$FX_DC$46

PIN | CLK_EXT | 4096 | 0 | N/A | 57 | 70 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 8 | 14 | 15 | 17 | 15 | 8 | 15 | 6 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 15 | 12 | 15 | 15 | 15 | 16 | 10 | 15 | 8 | 9 | 8 | 11 | 8 | 12 | 9 | 17 | 9 | 15 | 15 | 14 | 14 | 0 | 14 | 1 | 14 | 2 | 11 | 17 | 11 | 16 | 9 | 14 | 11 | 15 | 14 | 3 | 14 | 4 | 14 | 5 | 11 | 14 | 9 | 12 | 11 | 13 | 11 | 12 | 8 | 8 | 10 | 17 | 8 | 5 | 8 | 15 | 8 | 4 | 8 | 3 | 8 | 2 | 15 | 11 | 8 | 1 | 14 | 7 | 11 | 0 | 15 | 13 | 9 | 0 | 8 | 0
PIN | RW | 64 | 0 | N/A | 158 | 44 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 1 | 17 | 1 | 15 | 1 | 12 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 4 | 12 | 10 | 15 | 3 | 10 | 10 | 16 | 1 | 10 | 1 | 8 | 3 | 12 | 3 | 14 | 3 | 15 | 14 | 9 | 8 | 6 | 3 | 16 | 1 | 0 | 1 | 3 | 1 | 6 | 14 | 10 | 13 | 4 | 4 | 8 | 4 | 15 | 4 | 10 | 15 | 17
PIN | AS | 64 | 0 | N/A | 152 | 34 | 3 | 8 | 3 | 9 | 8 | 17 | 1 | 17 | 1 | 15 | 1 | 12 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 4 | 17 | 0 | 17 | 3 | 10 | 1 | 10 | 1 | 8 | 3 | 12 | 3 | 14 | 3 | 15 | 12 | 1 | 10 | 16 | 0 | 15 | 2 | 1 | 4 | 4 | 13 | 13 | 4 | 1 | 1 | 0 | 13 | 1 | 1 | 3 | 1 | 6 | 3 | 16 | 13 | 4 | 4 | 15 | 4 | 10 | 4 | 12
PIN | RESET | 64 | 0 | N/A | 263 | 112 | 3 | 8 | 3 | 9 | 8 | 17 | 1 | 17 | 1 | 15 | 1 | 12 | 6 | 17 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 6 | 9 | 6 | 8 | 6 | 7 | 6 | 6 | 6 | 5 | 6 | 3 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 7 | 17 | 7 | 16 | 12 | 12 | 7 | 15 | 7 | 14 | 7 | 13 | 12 | 11 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 12 | 10 | 12 | 9 | 12 | 8 | 8 | 14 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 0 | 15 | 8 | 9 | 4 | 17 | 8 | 11 | 8 | 12 | 0 | 17 | 12 | 5 | 13 | 16 | 3 | 10 | 8 | 8 | 12 | 4 | 1 | 10 | 1 | 8 | 6 | 1 | 3 | 0 | 13 | 17 | 12 | 6 | 3 | 12 | 3 | 14 | 3 | 15 | 0 | 12 | 0 | 10 | 0 | 8 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 9 | 13 | 8 | 0 | 6 | 0 | 3 | 0 | 2 | 13 | 7 | 13 | 6 | 8 | 5 | 8 | 15 | 8 | 4 | 8 | 3 | 8 | 2 | 3 | 11 | 1 | 1 | 3 | 13 | 8 | 0 | 9 | 0 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 12 | 3 | 3 | 7 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 7 | 7 | 4 | 1 | 9 | 8
PIN | A<4> | 64 | 0 | N/A | 97 | 18 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 6 | 13 | 15 | 1 | 1 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 16 | 3 | 1 | 3 | 3 | 3 | 4 | 3 | 7 | 3 | 17
PIN | A<3> | 64 | 0 | N/A | 99 | 17 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 6 | 13 | 6 | 3 | 7 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 16 | 3 | 1 | 3 | 3 | 3 | 4 | 3 | 17
PIN | A<1> | 64 | 0 | N/A | 107 | 16 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 6 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 16 | 3 | 1 | 3 | 3 | 3 | 4 | 3 | 7 | 3 | 17
PIN | A<5> | 64 | 0 | N/A | 91 | 17 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 3 | 0 | 13 | 12 | 3 | 13 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 16 | 3 | 3 | 3 | 6 | 3 | 1 | 3 | 7
PIN | A<6> | 64 | 0 | N/A | 98 | 9 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 13 | 11 | 13 | 1 | 1 | 6 | 3 | 16
PIN | LAN_INT | 64 | 0 | N/A | 201 | 2 | 8 | 14 | 8 | 2
PIN | UDS | 64 | 0 | N/A | 155 | 4 | 11 | 12 | 5 | 12 | 11 | 1 | 11 | 11
PIN | LDS | 64 | 0 | N/A | 157 | 2 | 14 | 7 | 5 | 12
PIN | DS1 | 64 | 0 | N/A | 148 | 4 | 11 | 12 | 11 | 0 | 2 | 17 | 11 | 11
PIN | DS0 | 64 | 0 | N/A | 170 | 2 | 14 | 7 | 2 | 17
PIN | FCS | 64 | 0 | N/A | 147 | 20 | 0 | 15 | 12 | 5 | 13 | 16 | 0 | 12 | 0 | 10 | 0 | 8 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 9 | 13 | 8 | 0 | 6 | 0 | 3 | 0 | 2 | 13 | 7 | 13 | 6 | 14 | 11 | 13 | 2 | 13 | 0 | 12 | 3
PIN | Z3 | 64 | 0 | N/A | 151 | 2 | 0 | 15 | 12 | 5
PIN | CFIN | 64 | 0 | N/A | 190 | 1 | 4 | 17
PIN | A<2> | 64 | 0 | N/A | 101 | 16 | 1 | 10 | 1 | 8 | 3 | 0 | 13 | 7 | 3 | 11 | 1 | 0 | 3 | 2 | 1 | 3 | 1 | 6 | 3 | 16 | 3 | 1 | 3 | 6 | 3 | 3 | 3 | 4 | 3 | 7 | 3 | 17
PIN | A<7> | 64 | 0 | N/A | 100 | 1 | 13 | 9
PIN | BERR | 64 | 0 | N/A | 176 | 1 | 8 | 0
PIN | C3 | 64 | 0 | N/A | 187 | 1 | 13 | 3
PIN | C1 | 64 | 0 | N/A | 188 | 1 | 13 | 3
PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 142 | 1 | 4 | 4
PIN | CP_IRQ | 64 | 0 | N/A | 59 | 1 | 10 | 11
PIN | A_LAN<2> | 536871040 | 0 | N/A | 12
PIN | A_LAN<4> | 536871040 | 0 | N/A | 20
PIN | A_LAN<5> | 536871040 | 0 | N/A | 13
PIN | A_LAN<0> | 536871040 | 0 | N/A | 7
PIN | A_LAN<10> | 536871040 | 0 | N/A | 255
PIN | A_LAN<11> | 536871040 | 0 | N/A | 256
PIN | A_LAN<12> | 536871040 | 0 | N/A | 253
PIN | A_LAN<13> | 536871040 | 0 | N/A | 254
PIN | A_LAN<1> | 536871040 | 0 | N/A | 6
PIN | A_LAN<3> | 536871040 | 0 | N/A | 8
PIN | A_LAN<6> | 536871040 | 0 | N/A | 22
PIN | A_LAN<7> | 536871040 | 0 | N/A | 21
PIN | A_LAN<8> | 536871040 | 0 | N/A | 258
PIN | A_LAN<9> | 536871040 | 0 | N/A | 262
PIN | CP_RD | 536871040 | 0 | N/A | 132
PIN | CP_WE | 536871040 | 0 | N/A | 131
PIN | IDE_R | 536871040 | 0 | N/A | 46
PIN | IDE_W | 536871040 | 0 | N/A | 47
PIN | LAN_CS | 536871040 | 0 | N/A | 240
PIN | LAN_WRH | 536871040 | 0 | N/A | 237
PIN | LAN_WRL | 536871040 | 0 | N/A | 145
PIN | ROM_OE | 536871040 | 0 | N/A | 65
PIN | LAN_RD | 536871040 | 0 | N/A | 242
PIN | SLAVE | 536871040 | 0 | N/A | 193
PIN | DTACK | 536871040 | 0 | N/A | 160
PIN | OVR | 536871040 | 0 | N/A | 185
PIN | INT_OUT | 536871040 | 0 | N/A | 60
PIN | INT_CP_OUT | 536871040 | 0 | N/A | 127
PIN | CFOUT | 536871040 | 0 | N/A | 191
PIN | CP_CS | 536871040 | 0 | N/A | 63
PIN | IDE_A<0> | 536871040 | 0 | N/A | 43
PIN | IDE_A<1> | 536871040 | 0 | N/A | 45
PIN | IDE_A<2> | 536871040 | 0 | N/A | 44
PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39
PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41
PIN | OWN | 536871040 | 0 | N/A | 195
PIN | MTACK | 536871040 | 0 | N/A | 174
PIN | LAN_CFG<4> | 536871040 | 0 | N/A | 199
PIN | LAN_CFG<3> | 536871040 | 0 | N/A | 24
PIN | LAN_CFG<2> | 536871040 | 0 | N/A | 251
PIN | LAN_CFG<1> | 536871040 | 0 | N/A | 23
PIN | ROM_B<1> | 536871040 | 0 | N/A | 129
PIN | ROM_B<0> | 536871040 | 0 | N/A | 61
PIN | A<8> | 536870976 | 0 | N/A | 106 | 3 | 9 | 17 | 9 | 12 | 13 | 8
PIN | A<18> | 536870976 | 0 | N/A | 171 | 6 | 4 | 17 | 0 | 16 | 9 | 15 | 9 | 14 | 5 | 13 | 4 | 2
PIN | A<19> | 536870976 | 0 | N/A | 169 | 7 | 4 | 17 | 0 | 17 | 15 | 14 | 11 | 15 | 5 | 13 | 4 | 2 | 5 | 0
PIN | A<20> | 536870976 | 0 | N/A | 167 | 7 | 4 | 17 | 0 | 1 | 14 | 0 | 14 | 3 | 4 | 0 | 5 | 0 | 4 | 2
PIN | A<21> | 536870976 | 0 | N/A | 163 | 6 | 4 | 17 | 0 | 1 | 14 | 1 | 14 | 4 | 4 | 0 | 5 | 0
PIN | A<22> | 536870976 | 0 | N/A | 162 | 6 | 4 | 17 | 0 | 0 | 14 | 2 | 5 | 14 | 4 | 0 | 14 | 6
PIN | A<23> | 536870976 | 0 | N/A | 161 | 7 | 4 | 17 | 0 | 0 | 11 | 17 | 11 | 14 | 11 | 11 | 4 | 1 | 5 | 14
PIN | A<9> | 536870976 | 0 | N/A | 108 | 4 | 11 | 16 | 11 | 13 | 0 | 6 | 0 | 11
PIN | A<10> | 536870976 | 0 | N/A | 112 | 4 | 9 | 15 | 9 | 14 | 0 | 3 | 0 | 14
PIN | A<11> | 536870976 | 0 | N/A | 114 | 4 | 15 | 14 | 11 | 15 | 0 | 2 | 0 | 13
PIN | A<12> | 536870976 | 0 | N/A | 115 | 4 | 0 | 7 | 14 | 3 | 0 | 12 | 14 | 17
PIN | A<13> | 536870976 | 0 | N/A | 123 | 5 | 0 | 15 | 14 | 1 | 14 | 4 | 0 | 10 | 0 | 9
PIN | A<14> | 536870976 | 0 | N/A | 125 | 4 | 0 | 15 | 14 | 2 | 14 | 5 | 0 | 8
PIN | A<15> | 536870976 | 0 | N/A | 139 | 3 | 13 | 16 | 11 | 0 | 11 | 14
PIN | A<16> | 536870976 | 0 | N/A | 175 | 7 | 4 | 17 | 0 | 16 | 9 | 17 | 9 | 12 | 0 | 0 | 5 | 1 | 4 | 3
PIN | A<17> | 536870976 | 0 | N/A | 172 | 7 | 4 | 17 | 0 | 16 | 11 | 16 | 11 | 13 | 5 | 13 | 4 | 3 | 5 | 1
PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 4 | 15 | 5 | 8 | 16 | 15 | 6 | 15 | 1
PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 4 | 10 | 5 | 10 | 2 | 10 | 14 | 15 | 3
PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 6 | 8 | 13 | 15 | 7 | 15 | 8 | 15 | 3 | 1 | 14 | 4 | 11
PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 6 | 15 | 1 | 10 | 4 | 10 | 12 | 10 | 3 | 4 | 16 | 0 | 5
PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 4 | 8 | 10 | 15 | 9 | 15 | 0 | 15 | 4
PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 4 | 8 | 13 | 15 | 7 | 15 | 8 | 15 | 3
PIN | D<0> | 536870976 | 0 | N/A | 4 | 3 | 9 | 2 | 9 | 0 | 9 | 12
PIN | D<10> | 536870976 | 0 | N/A | 74 | 7 | 6 | 15 | 6 | 6 | 7 | 17 | 7 | 12 | 9 | 16 | 5 | 15 | 9 | 14
PIN | D<11> | 536870976 | 0 | N/A | 77 | 9 | 6 | 14 | 6 | 5 | 7 | 16 | 7 | 11 | 11 | 9 | 15 | 13 | 11 | 15 | 5 | 16 | 5 | 15
PIN | D<12> | 536870976 | 0 | N/A | 78 | 9 | 6 | 13 | 6 | 3 | 12 | 12 | 7 | 10 | 7 | 1 | 5 | 17 | 14 | 3 | 5 | 14 | 14 | 17
PIN | D<13> | 536870976 | 0 | N/A | 80 | 8 | 6 | 12 | 12 | 17 | 7 | 15 | 7 | 8 | 11 | 7 | 14 | 0 | 5 | 17 | 14 | 5
PIN | D<14> | 536870976 | 0 | N/A | 81 | 8 | 6 | 10 | 12 | 16 | 7 | 14 | 7 | 6 | 7 | 2 | 14 | 1 | 5 | 17 | 14 | 6
PIN | D<15> | 536870976 | 0 | N/A | 89 | 9 | 6 | 9 | 12 | 15 | 7 | 13 | 12 | 10 | 11 | 4 | 11 | 0 | 11 | 14 | 11 | 12 | 5 | 15
PIN | D<1> | 536870976 | 0 | N/A | 30 | 3 | 9 | 1 | 11 | 12 | 11 | 17
PIN | D<2> | 536870976 | 0 | N/A | 71 | 3 | 9 | 5 | 9 | 15 | 9 | 13
PIN | D<3> | 536870976 | 0 | N/A | 28 | 3 | 9 | 4 | 15 | 13 | 11 | 16
PIN | D<4> | 536870976 | 0 | N/A | 38 | 3 | 9 | 9 | 14 | 4 | 14 | 17
PIN | D<5> | 536870976 | 0 | N/A | 37 | 3 | 9 | 7 | 14 | 0 | 14 | 5
PIN | D<6> | 536870976 | 0 | N/A | 26 | 3 | 9 | 11 | 14 | 2 | 14 | 6
PIN | D<7> | 536870976 | 0 | N/A | 29 | 3 | 9 | 10 | 11 | 0 | 11 | 13
PIN | D<8> | 536870976 | 0 | N/A | 32 | 8 | 6 | 17 | 6 | 8 | 12 | 14 | 12 | 9 | 9 | 13 | 9 | 17 | 9 | 11 | 5 | 16
PIN | D<9> | 536870976 | 0 | N/A | 73 | 8 | 6 | 16 | 6 | 7 | 12 | 11 | 12 | 8 | 11 | 11 | 5 | 16 | 11 | 12 | 11 | 17
PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 6 | 8 | 10 | 15 | 9 | 15 | 0 | 15 | 4 | 3 | 1 | 1 | 16
PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 4 | 10 | 3 | 10 | 4 | 10 | 12 | 15 | 2
PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 4 | 14 | 16 | 10 | 9 | 10 | 8 | 10 | 1
PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 4 | 14 | 14 | 10 | 10 | 10 | 7 | 10 | 0
PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 4 | 14 | 13 | 12 | 7 | 10 | 6 | 10 | 16
PIN | DQ<2> | 536870976 | 0 | N/A | 220 | 6 | 15 | 5 | 8 | 16 | 15 | 6 | 15 | 0 | 4 | 13 | 4 | 9
PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 6 | 15 | 2 | 10 | 2 | 10 | 14 | 10 | 5 | 4 | 14 | 1 | 11
PIN | DQ<5> | 536870976 | 0 | N/A | 221 | 6 | 14 | 16 | 10 | 9 | 10 | 8 | 10 | 1 | 6 | 2 | 0 | 4
PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 6 | 14 | 14 | 10 | 10 | 10 | 7 | 10 | 0 | 6 | 4 | 1 | 9
PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 6 | 14 | 13 | 12 | 7 | 10 | 6 | 6 | 11 | 1 | 13 | 10 | 16