cpldfit: version P.68d Xilinx Inc. No Fit Report Design Name: LAN_IDE_CP Date: 12-28-2016, 8:53PM Device Used: XC95144XL-10-TQ144 Fitting Status: Design Rule Checking Failed ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be deleted. WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will be deleted. WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation. ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 157 but only 144 left after allocating other resources. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ************************* Mapped Resource Summary ************************** No logic has been mapped. Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 72 /144 ( 50%) 147 /720 ( 20%) 120/432 ( 28%) 4 /144 ( 3%) 106/117 ( 91%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 13/18 21/54 26/90 14/15 FB2 14/18 17/54 18/90 15/15* FB3 10/18 37/54 56/90 13/15 FB4 15/18 15/54 19/90 15/15* FB5 3/18 5/54 2/90 14/14* FB6 12/18 16/54 22/90 13/13* FB7 3/18 5/54 2/90 11/15 FB8 2/18 4/54 2/90 11/15 ----- ----- ----- ----- 72/144 120/432 147/720 106/117 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 33 33 | I/O : 100 109 Output : 40 40 | GCK/IO : 1 3 Bidirectional : 32 32 | GTS/IO : 4 4 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 106 106 End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 72 Outputs ** Signal Total Total Loc Pin Pin Pin Name Pts Inps No. Type Use IDE_CS<1> 1 1 FB1_1 23 I/O O D<7> 3 6 FB1_2 16 I/O I/O D<1> 3 6 FB1_3 17 I/O I/O IDE_A<2> 1 1 FB1_4 25 I/O O D<8> 3 6 FB1_5 19 I/O I/O D<5> 3 6 FB1_6 20 I/O I/O D<4> 3 6 FB1_8 21 I/O I/O IDE_CS<0> 1 1 FB1_9 22 I/O O IDE_A<0> 1 1 FB1_11 24 I/O O IDE_A<1> 1 1 FB1_12 26 I/O O IDE_R 2 6 FB1_14 27 I/O O IDE_W 2 5 FB1_15 28 I/O O ROM_OE 2 6 FB1_16 35 I/O O A_LAN<9> 1 1 FB2_1 142 I/O O A_LAN<0> 1 1 FB2_4 4 I/O O D<0> 3 6 FB2_5 2 GTS/I/O I/O A_LAN<1> 1 1 FB2_6 3 GTS/I/O O A_LAN<3> 1 1 FB2_8 5 GTS/I/O O A_LAN<2> 1 1 FB2_9 6 GTS/I/O O A_LAN<5> 1 1 FB2_10 7 I/O O A_LAN<4> 1 1 FB2_11 9 I/O O A_LAN<7> 1 1 FB2_12 10 I/O O LAN_CFG<1> 0 0 FB2_13 12 I/O O A_LAN<6> 1 1 FB2_14 11 I/O O LAN_CFG<3> 0 0 FB2_15 13 I/O O D<6> 3 6 FB2_16 14 I/O I/O D<3> 3 6 FB2_17 15 I/O I/O D<2> 3 6 FB3_1 39 I/O I/O INT_OUT 1 1 FB3_2 32 GCK/I/O O D<10> 3 6 FB3_3 41 I/O I/O D<12> 6 7 FB3_4 44 I/O I/O CP_CS 19 19 FB3_6 34 I/O O D<14> 6 7 FB3_7 46 I/O I/O D<9> 3 6 FB3_9 40 I/O I/O D<15> 6 7 FB3_10 48 I/O I/O D<11> 3 6 FB3_11 43 I/O I/O D<13> 6 7 FB3_12 45 I/O I/O DQ<0> 2 3 FB4_1 118 I/O I/O DQ<6> 2 3 FB4_2 126 I/O I/O LAN_CS 0 0 FB4_3 133 I/O O Signal Total Total Loc Pin Pin Pin Name Pts Inps No. Type Use DQ<8> 2 3 FB4_5 128 I/O I/O DQ<10> 2 3 FB4_6 129 I/O I/O DQ<12> 2 3 FB4_8 130 I/O I/O DQ<14> 2 3 FB4_9 131 I/O I/O LAN_CFG<2> 0 0 FB4_10 135 I/O O LAN_WRH 1 4 FB4_11 132 I/O O LAN_RD 1 3 FB4_12 134 I/O O A_LAN<12> 1 1 FB4_13 137 I/O O A_LAN<13> 1 1 FB4_14 136 I/O O A_LAN<10> 1 1 FB4_15 138 I/O O A_LAN<11> 1 1 FB4_16 139 I/O O A_LAN<8> 1 1 FB4_17 140 I/O O ROM_B<0> 0 0 FB5_10 68 I/O O CP_WE 2 5 FB5_13 70 I/O O ROM_B<1> 0 0 FB5_17 69 I/O O SLAVE 2 5 FB6_2 106 I/O O LAN_CFG<4> 0 0 FB6_5 110 I/O O DQ<15> 2 3 FB6_6 112 I/O I/O DQ<13> 2 3 FB6_8 113 I/O I/O DQ<9> 2 3 FB6_9 116 I/O I/O DQ<11> 2 3 FB6_10 115 I/O I/O DQ<3> 2 3 FB6_11 119 I/O I/O DQ<2> 2 3 FB6_12 120 I/O I/O DQ<5> 2 3 FB6_14 121 I/O I/O DQ<4> 2 3 FB6_15 124 I/O I/O DQ<1> 2 3 FB6_16 117 I/O I/O DQ<7> 2 3 FB6_17 125 I/O I/O CP_RD 1 3 FB7_2 71 I/O O LAN_WRL 1 4 FB7_6 76 I/O O DTACK 0 0 FB7_12 85 I/O O OWN 1 1 FB8_16 107 I/O O CFOUT 1 3 FB8_17 105 I/O O ** 34 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CP_IRQ FB1_10 31 I/O I RESET FB2_2 143 GSR/I/O GSR/I A<5> FB3_14 49 I/O I A<4> FB3_15 50 I/O I A<6> FB3_17 51 I/O I A<3> FB5_2 52 I/O I A<10> FB5_3 59 I/O I A<7> FB5_5 53 I/O I A<2> FB5_6 54 I/O I A<14> FB5_7 66 I/O I A<8> FB5_8 56 I/O I A<1> FB5_9 57 I/O I A<9> FB5_11 58 I/O I A<11> FB5_12 60 I/O I A<12> FB5_14 61 I/O I A<13> FB5_15 64 I/O I LAN_INT FB6_4 111 I/O I AUTOBOOT_OFF FB7_3 75 I/O I AS FB7_9 80 I/O I LDS FB7_11 82 I/O I UDS FB7_13 81 I/O I A<23> FB7_14 86 I/O I A<22> FB7_15 87 I/O I RW FB7_16 83 I/O I A<21> FB7_17 88 I/O I A<20> FB8_2 91 I/O I A<17> FB8_3 95 I/O I A<16> FB8_4 97 I/O I A<19> FB8_5 92 I/O I A<18> FB8_8 94 I/O I BERR FB8_11 98 I/O I C1 FB8_13 103 I/O I C3 FB8_14 102 I/O I CFIN FB8_15 104 I/O I Legend: Pin No. - ~ - User Assigned ************************* Summary of UnMapped Logic ************************ ** 85 Buried Nodes ** Signal Total Total User Name Pts Inps Assignment $OpTx$INV$124__$INT 3 5 AUTO_CONFIG_DONE<0> 2 2 AUTO_CONFIG_DONE<1> 2 2 AUTO_CONFIG_DONE<2> 2 2 AUTO_CONFIG_DONE_CYCLE<0>/AUTO_CONFIG_DONE_CYCLE<0>_CLKF 2 2 AUTO_CONFIG_DONE_CYCLE<0> 3 13 AUTO_CONFIG_DONE_CYCLE<1>/AUTO_CONFIG_DONE_CYCLE<1>_CLKF 2 2 AUTO_CONFIG_DONE_CYCLE<1> 3 13 AUTO_CONFIG_DONE_CYCLE<2> 3 13 AUTO_CONFIG_DONE_CYCLE<2>/AUTO_CONFIG_DONE_CYCLE<2>_CLKF 2 2 CP_BASEADR<0> 4 15 CP_BASEADR<0>/CP_BASEADR<0>_CLKF 2 2 CP_BASEADR<1> 4 15 CP_BASEADR<1>/CP_BASEADR<1>_CLKF 2 2 CP_BASEADR<2>/CP_BASEADR<2>_CLKF 2 2 CP_BASEADR<2> 4 15 CP_BASEADR<3>/CP_BASEADR<3>_CLKF 2 2 CP_BASEADR<3> 4 15 CP_BASEADR<4> 4 15 CP_BASEADR<4>/CP_BASEADR<4>_CLKF 2 2 CP_BASEADR<5>/CP_BASEADR<5>_CLKF 2 2 CP_BASEADR<5> 4 15 CP_BASEADR<6> 4 15 CP_BASEADR<6>/CP_BASEADR<6>_CLKF 2 2 CP_BASEADR<7>/CP_BASEADR<7>_CLKF 2 2 CP_BASEADR<7> 4 15 Dout1<0> 19 16 Dout1<0>/Dout1<0>_CLKF 2 2 Dout1<1> 17 15 Dout1<1>/Dout1<1>_CLKF 2 2 Dout1<2>/Dout1<2>_CLKF 2 2 Dout1<2> 18 15 Dout1<3>/Dout1<3>_CLKF 2 2 Dout1<3> 14 15 IDE_BASEADR<0> 4 15 IDE_BASEADR<0>/IDE_BASEADR<0>_CLKF 2 2 IDE_BASEADR<1>/IDE_BASEADR<1>_CLKF 2 2 IDE_BASEADR<1> 4 15 IDE_BASEADR<2> 4 15 IDE_BASEADR<2>/IDE_BASEADR<2>_CLKF 2 2 Signal Total Total User Name Pts Inps Assignment IDE_BASEADR<3>/IDE_BASEADR<3>_CLKF 2 2 IDE_BASEADR<3> 4 15 IDE_BASEADR<4>/IDE_BASEADR<4>_CLKF 2 2 IDE_BASEADR<4> 4 15 IDE_BASEADR<5> 4 15 IDE_BASEADR<5>/IDE_BASEADR<5>_CLKF 2 2 IDE_BASEADR<6> 4 15 IDE_BASEADR<6>/IDE_BASEADR<6>_CLKF 2 2 IDE_BASEADR<7>/IDE_BASEADR<7>_CLKF 2 2 IDE_BASEADR<7> 4 15 IDE_ENABLE 3 6 IDE_ENABLE/IDE_ENABLE_CLKF 2 2 IDE_R_S/IDE_R_S_CLKF 2 2 IDE_W_S/IDE_W_S_CLKF 2 2 LAN_BASEADR<0>/LAN_BASEADR<0>_CLKF 2 2 LAN_BASEADR<0> 4 15 LAN_BASEADR<1>/LAN_BASEADR<1>_CLKF 2 2 LAN_BASEADR<1> 4 15 LAN_BASEADR<2> 4 15 LAN_BASEADR<2>/LAN_BASEADR<2>_CLKF 2 2 LAN_BASEADR<3> 4 15 LAN_BASEADR<3>/LAN_BASEADR<3>_CLKF 2 2 LAN_BASEADR<4>/LAN_BASEADR<4>_CLKF 2 2 LAN_BASEADR<4> 4 15 LAN_BASEADR<5> 4 15 LAN_BASEADR<5>/LAN_BASEADR<5>_CLKF 2 2 LAN_BASEADR<6>/LAN_BASEADR<6>_CLKF 2 2 LAN_BASEADR<6> 4 15 LAN_BASEADR<7>/LAN_BASEADR<7>_CLKF 2 2 LAN_BASEADR<7> 4 15 LAN_INT_ENABLE 1 1 ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST 2 3 ROM_OE_S/ROM_OE_S_CLKF 2 2 SHUT_UP<0>/SHUT_UP<0>_CLKF 2 2 SHUT_UP<0> 3 14 SHUT_UP<1>/SHUT_UP<1>_CLKF 2 2 SHUT_UP<1> 3 14 SHUT_UP<2> 3 14 SHUT_UP<2>/SHUT_UP<2>_CLKF 2 2 SLAVE_OBUF__$INT 2 5 Signal Total Total User Name Pts Inps Assignment autoconfig 5 14 ide 19 19 ide/ide_RSTF__$INT 1 2 lan 19 19 lan/lan_CLKF 2 2 ******************************* Equations ******************************** ********** Mapped Logic ********** A_LAN(0) <= A(1); A_LAN(1) <= A(2); A_LAN(2) <= A(3); A_LAN(3) <= A(4); A_LAN(4) <= A(5); A_LAN(5) <= A(6); A_LAN(6) <= A(7); A_LAN(7) <= A(8); A_LAN(8) <= A(9); A_LAN(9) <= A(10); A_LAN(10) <= A(11); A_LAN(11) <= A(12); A_LAN(12) <= A(13); A_LAN(13) <= A(14); CFOUT <= NOT ((AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))); FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,lan/lan_CLKF,NOT ide/ide_RSTF__$INT,'0'); CP_CS_D <= ((SHUT_UP(2)) OR (CP_BASEADR(7) AND NOT A(23)) OR (NOT CP_BASEADR(7) AND A(23)) OR (CP_BASEADR(3) AND NOT A(19)) OR (NOT CP_BASEADR(3) AND A(19)) OR (CP_BASEADR(6) AND NOT A(22)) OR (NOT CP_BASEADR(6) AND A(22)) OR (CP_BASEADR(4) AND NOT A(20)) OR (NOT CP_BASEADR(4) AND A(20)) OR (CP_BASEADR(5) AND NOT A(21)) OR (NOT CP_BASEADR(5) AND A(21)) OR (CP_BASEADR(1) AND NOT A(17)) OR (NOT CP_BASEADR(1) AND A(17)) OR (CP_BASEADR(2) AND NOT A(18)) OR (NOT CP_BASEADR(2) AND A(18)) OR (CP_BASEADR(0) AND NOT A(16)) OR (NOT CP_BASEADR(0) AND A(16))); CP_RD <= NOT ((CP_CS AND NOT AS AND RW)); CP_WE <= NOT (((CP_CS AND NOT AS AND NOT RW AND NOT UDS) OR (CP_CS AND NOT AS AND NOT RW AND NOT LDS))); D_I(0) <= NOT (((CP_CS AND NOT DQ(0).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(0).PIN AND NOT AS AND RW))); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= NOT $OpTx$INV$124__$INT; D_I(1) <= NOT (((CP_CS AND NOT DQ(1).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(1).PIN AND NOT AS AND RW))); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= NOT $OpTx$INV$124__$INT; D_I(2) <= NOT (((CP_CS AND NOT DQ(2).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(2).PIN AND NOT AS AND RW))); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= NOT $OpTx$INV$124__$INT; D_I(3) <= NOT (((CP_CS AND NOT DQ(3).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(3).PIN AND NOT AS AND RW))); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= NOT $OpTx$INV$124__$INT; D_I(4) <= NOT (((CP_CS AND NOT DQ(4).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(4).PIN AND NOT AS AND RW))); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= NOT $OpTx$INV$124__$INT; D_I(5) <= NOT (((CP_CS AND NOT DQ(5).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(5).PIN AND NOT AS AND RW))); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= NOT $OpTx$INV$124__$INT; D_I(6) <= NOT (((CP_CS AND NOT DQ(6).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(6).PIN AND NOT AS AND RW))); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= NOT $OpTx$INV$124__$INT; D_I(7) <= NOT (((CP_CS AND NOT DQ(7).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(7).PIN AND NOT AS AND RW))); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= NOT $OpTx$INV$124__$INT; D_I(8) <= NOT (((CP_CS AND NOT DQ(8).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(8).PIN AND NOT AS AND RW))); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= NOT $OpTx$INV$124__$INT; D_I(9) <= NOT (((CP_CS AND NOT DQ(9).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(9).PIN AND NOT AS AND RW))); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= NOT $OpTx$INV$124__$INT; D_I(10) <= NOT (((CP_CS AND NOT DQ(10).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(10).PIN AND NOT AS AND RW))); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= NOT $OpTx$INV$124__$INT; D_I(11) <= NOT (((CP_CS AND NOT DQ(11).PIN AND NOT AS AND RW) OR (lan AND NOT DQ(11).PIN AND NOT AS AND RW))); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= NOT $OpTx$INV$124__$INT; D_I(12) <= ((Dout1(0) AND AS) OR (Dout1(0) AND NOT RW) OR (NOT CP_CS AND NOT lan AND Dout1(0)) OR (CP_CS AND DQ(12).PIN AND NOT AS AND RW) OR (lan AND DQ(12).PIN AND NOT AS AND RW)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= NOT $OpTx$INV$124__$INT; D_I(13) <= ((Dout1(1) AND AS) OR (Dout1(1) AND NOT RW) OR (NOT CP_CS AND NOT lan AND Dout1(1)) OR (CP_CS AND DQ(13).PIN AND NOT AS AND RW) OR (lan AND DQ(13).PIN AND NOT AS AND RW)); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= NOT $OpTx$INV$124__$INT; D_I(14) <= ((Dout1(2) AND AS) OR (Dout1(2) AND NOT RW) OR (NOT CP_CS AND NOT lan AND Dout1(2)) OR (CP_CS AND DQ(14).PIN AND NOT AS AND RW) OR (lan AND DQ(14).PIN AND NOT AS AND RW)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= NOT $OpTx$INV$124__$INT; D_I(15) <= ((Dout1(3) AND AS) OR (Dout1(3) AND NOT RW) OR (NOT CP_CS AND NOT lan AND Dout1(3)) OR (CP_CS AND DQ(15).PIN AND NOT AS AND RW) OR (lan AND DQ(15).PIN AND NOT AS AND RW)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= NOT $OpTx$INV$124__$INT; DQ_I(0) <= D(0).PIN; DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z'; DQ_OE(0) <= (NOT AS AND NOT RW); DQ_I(1) <= D(1).PIN; DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z'; DQ_OE(1) <= (NOT AS AND NOT RW); DQ_I(2) <= D(2).PIN; DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z'; DQ_OE(2) <= (NOT AS AND NOT RW); DQ_I(3) <= D(3).PIN; DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z'; DQ_OE(3) <= (NOT AS AND NOT RW); DQ_I(4) <= D(4).PIN; DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z'; DQ_OE(4) <= (NOT AS AND NOT RW); DQ_I(5) <= D(5).PIN; DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z'; DQ_OE(5) <= (NOT AS AND NOT RW); DQ_I(6) <= D(6).PIN; DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z'; DQ_OE(6) <= (NOT AS AND NOT RW); DQ_I(7) <= D(7).PIN; DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z'; DQ_OE(7) <= (NOT AS AND NOT RW); DQ_I(8) <= D(8).PIN; DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z'; DQ_OE(8) <= (NOT AS AND NOT RW); DQ_I(9) <= D(9).PIN; DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z'; DQ_OE(9) <= (NOT AS AND NOT RW); DQ_I(10) <= D(10).PIN; DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z'; DQ_OE(10) <= (NOT AS AND NOT RW); DQ_I(11) <= D(11).PIN; DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z'; DQ_OE(11) <= (NOT AS AND NOT RW); DQ_I(12) <= D(12).PIN; DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z'; DQ_OE(12) <= (NOT AS AND NOT RW); DQ_I(13) <= D(13).PIN; DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z'; DQ_OE(13) <= (NOT AS AND NOT RW); DQ_I(14) <= D(14).PIN; DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z'; DQ_OE(14) <= (NOT AS AND NOT RW); DQ_I(15) <= D(15).PIN; DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z'; DQ_OE(15) <= (NOT AS AND NOT RW); DTACK_I <= '0'; DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; DTACK_OE <= '0'; IDE_A(0) <= A(9); IDE_A(1) <= A(10); IDE_A(2) <= A(11); IDE_CS(0) <= NOT A(12); IDE_CS(1) <= NOT A(13); FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,IDE_R_S/IDE_R_S_CLKF,'0','0'); IDE_R_D <= (ide AND NOT IDE_ENABLE AND RESET AND NOT AS AND RW); FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,IDE_W_S/IDE_W_S_CLKF,'0','0'); IDE_W_D <= (ide AND RESET AND NOT AS AND NOT RW); INT_OUT_I <= '0'; INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z'; INT_OUT_OE <= ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST; LAN_CFG(1) <= '0'; LAN_CFG(2) <= '1'; LAN_CFG(3) <= '0'; LAN_CFG(4) <= '0'; LAN_CS <= '1'; LAN_RD <= (lan AND NOT AS AND RW); LAN_WRH <= (lan AND NOT AS AND NOT RW AND NOT UDS); LAN_WRL <= (lan AND NOT AS AND NOT RW AND NOT LDS); OWN_I <= '0'; OWN <= OWN_I when OWN_OE = '1' else 'Z'; OWN_OE <= NOT SLAVE_OBUF__$INT; ROM_B(0) <= '0'; ROM_B(1) <= '0'; FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ROM_OE_S/ROM_OE_S_CLKF,'0','0'); ROM_OE_D <= (ide AND IDE_ENABLE AND RESET AND NOT AS AND RW); SLAVE <= ((AS) OR (NOT CP_CS AND NOT ide AND NOT lan AND NOT autoconfig)); ********** UnMapped Logic ********** ** Buried Nodes ** $OpTx$INV$124__$INT <= ((AS) OR (NOT RW) OR (NOT CP_CS AND NOT lan AND NOT autoconfig)); FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0'); FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0'); FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0'); AUTO_CONFIG_DONE_CYCLE(0)/AUTO_CONFIG_DONE_CYCLE(0)_CLKF <= NOT (C1 XOR AUTO_CONFIG_DONE_CYCLE(0)/AUTO_CONFIG_DONE_CYCLE(0)_CLKF <= NOT (C3); FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),AUTO_CONFIG_DONE_CYCLE(0)/AUTO_CONFIG_DONE_CYCLE(0)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(0) <= ((AUTO_CONFIG_DONE_CYCLE(0) AND RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); AUTO_CONFIG_DONE_CYCLE(1)/AUTO_CONFIG_DONE_CYCLE(1)_CLKF <= NOT (C1 XOR AUTO_CONFIG_DONE_CYCLE(1)/AUTO_CONFIG_DONE_CYCLE(1)_CLKF <= NOT (C3); FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),AUTO_CONFIG_DONE_CYCLE(1)/AUTO_CONFIG_DONE_CYCLE(1)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(1) <= ((AUTO_CONFIG_DONE_CYCLE(1) AND RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),AUTO_CONFIG_DONE_CYCLE(2)/AUTO_CONFIG_DONE_CYCLE(2)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(2) <= ((AUTO_CONFIG_DONE_CYCLE(2) AND RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); AUTO_CONFIG_DONE_CYCLE(2)/AUTO_CONFIG_DONE_CYCLE(2)_CLKF <= NOT (C1 XOR AUTO_CONFIG_DONE_CYCLE(2)/AUTO_CONFIG_DONE_CYCLE(2)_CLKF <= NOT (C3); FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),CP_BASEADR(0)/CP_BASEADR(0)_CLKF,'0','0'); CP_BASEADR_T(0) <= ((NOT CP_BASEADR(0) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(0) AND D(8).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(0) AND NOT D(8).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(0)/CP_BASEADR(0)_CLKF <= NOT (C1 XOR CP_BASEADR(0)/CP_BASEADR(0)_CLKF <= NOT (C3); FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),CP_BASEADR(1)/CP_BASEADR(1)_CLKF,'0','0'); CP_BASEADR_T(1) <= ((NOT CP_BASEADR(1) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(1) AND D(9).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(1) AND NOT D(9).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(1)/CP_BASEADR(1)_CLKF <= NOT (C1 XOR CP_BASEADR(1)/CP_BASEADR(1)_CLKF <= NOT (C3); FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),CP_BASEADR(2)/CP_BASEADR(2)_CLKF,'0','0'); CP_BASEADR_T(2) <= ((NOT CP_BASEADR(2) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(2) AND D(10).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(2) AND NOT D(10).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(2)/CP_BASEADR(2)_CLKF <= NOT (C1 XOR CP_BASEADR(2)/CP_BASEADR(2)_CLKF <= NOT (C3); CP_BASEADR(3)/CP_BASEADR(3)_CLKF <= NOT (C1 XOR CP_BASEADR(3)/CP_BASEADR(3)_CLKF <= NOT (C3); FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),CP_BASEADR(3)/CP_BASEADR(3)_CLKF,'0','0'); CP_BASEADR_T(3) <= ((NOT CP_BASEADR(3) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(3) AND D(11).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(3) AND NOT D(11).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),CP_BASEADR(4)/CP_BASEADR(4)_CLKF,'0','0'); CP_BASEADR_T(4) <= ((NOT CP_BASEADR(4) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(4) AND D(12).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(4) AND NOT D(12).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(4)/CP_BASEADR(4)_CLKF <= NOT (C1 XOR CP_BASEADR(4)/CP_BASEADR(4)_CLKF <= NOT (C3); FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),CP_BASEADR(5)/CP_BASEADR(5)_CLKF,'0','0'); CP_BASEADR_T(5) <= ((NOT CP_BASEADR(5) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(5) AND D(13).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(5) AND NOT D(13).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(5)/CP_BASEADR(5)_CLKF <= NOT (C1 XOR CP_BASEADR(5)/CP_BASEADR(5)_CLKF <= NOT (C3); FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),CP_BASEADR(6)/CP_BASEADR(6)_CLKF,'0','0'); CP_BASEADR_T(6) <= ((NOT CP_BASEADR(6) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(6) AND D(14).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(6) AND NOT D(14).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(6)/CP_BASEADR(6)_CLKF <= NOT (C1 XOR CP_BASEADR(6)/CP_BASEADR(6)_CLKF <= NOT (C3); FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),CP_BASEADR(7)/CP_BASEADR(7)_CLKF,'0','0'); CP_BASEADR_T(7) <= ((NOT CP_BASEADR(7) AND NOT RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT CP_BASEADR(7) AND D(15).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND CP_BASEADR(7) AND NOT D(15).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); CP_BASEADR(7)/CP_BASEADR(7)_CLKF <= NOT (C1 XOR CP_BASEADR(7)/CP_BASEADR(7)_CLKF <= NOT (C3); Dout1(0)/Dout1(0)_CLKF <= NOT (C1 XOR Dout1(0)/Dout1(0)_CLKF <= NOT (C3); FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),Dout1(0)/Dout1(0)_CLKF,'0','0'); Dout1_D(0) <= ((AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT Dout1(0) AND RESET AND AS) OR (NOT Dout1(0) AND RESET AND NOT RW) OR (NOT autoconfig AND NOT Dout1(0) AND RESET) OR (AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2) AND NOT Dout1(0) AND RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND A(5) AND A(1) AND A(2) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND A(5) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND A(5) AND A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW AND AUTOBOOT_OFF)); Dout1(1)/Dout1(1)_CLKF <= NOT (C1 XOR Dout1(1)/Dout1(1)_CLKF <= NOT (C3); FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),Dout1(1)/Dout1(1)_CLKF,'0','0'); Dout1_D(1) <= ((AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND A(1) AND NOT A(2) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT Dout1(1) AND RESET AND AS) OR (NOT Dout1(1) AND RESET AND NOT RW) OR (NOT autoconfig AND NOT Dout1(1) AND RESET) OR (AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2) AND NOT Dout1(1) AND RESET) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(2) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(2) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW)); FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),Dout1(2)/Dout1(2)_CLKF,'0','0'); Dout1_D(2) <= ((NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND A(2) AND NOT A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND A(1) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND A(1) AND A(2) AND NOT A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND A(2) AND NOT A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (NOT Dout1(2) AND RESET AND AS) OR (NOT Dout1(2) AND RESET AND NOT RW) OR (NOT autoconfig AND NOT Dout1(2) AND RESET) OR (AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2) AND NOT Dout1(2) AND RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND A(2) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW)); Dout1(2)/Dout1(2)_CLKF <= NOT (C1 XOR Dout1(2)/Dout1(2)_CLKF <= NOT (C3); Dout1(3)/Dout1(3)_CLKF <= NOT (C1 XOR Dout1(3)/Dout1(3)_CLKF <= NOT (C3); FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),Dout1(3)/Dout1(3)_CLKF,'0','0'); Dout1_D(3) <= ((NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(2) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT Dout1(3) AND RESET AND AS) OR (NOT Dout1(3) AND RESET AND NOT RW) OR (NOT autoconfig AND NOT Dout1(3) AND RESET) OR (AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2) AND NOT Dout1(3) AND RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND NOT A(2) AND NOT A(3) AND NOT A(4) AND A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND NOT AUTO_CONFIG_DONE(2) AND RESET AND NOT A(5) AND A(1) AND NOT A(3) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND A(1) AND A(2) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND A(4) AND NOT A(6) AND NOT AS AND RW) OR (AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND A(5) AND NOT A(1) AND A(2) AND NOT A(3) AND NOT A(4) AND NOT A(6) AND NOT AS AND RW)); FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),IDE_BASEADR(0)/IDE_BASEADR(0)_CLKF,'0','0'); IDE_BASEADR_T(0) <= ((NOT IDE_BASEADR(0) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(0) AND D(8).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(0) AND NOT D(8).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(0)/IDE_BASEADR(0)_CLKF <= NOT (C1 XOR IDE_BASEADR(0)/IDE_BASEADR(0)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),IDE_BASEADR(1)/IDE_BASEADR(1)_CLKF,'0','0'); IDE_BASEADR_T(1) <= ((NOT IDE_BASEADR(1) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(1) AND D(9).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(1) AND NOT D(9).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(1)/IDE_BASEADR(1)_CLKF <= NOT (C1 XOR IDE_BASEADR(1)/IDE_BASEADR(1)_CLKF <= NOT (C3); IDE_BASEADR(2)/IDE_BASEADR(2)_CLKF <= NOT (C1 XOR IDE_BASEADR(2)/IDE_BASEADR(2)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),IDE_BASEADR(2)/IDE_BASEADR(2)_CLKF,'0','0'); IDE_BASEADR_T(2) <= ((NOT IDE_BASEADR(2) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(2) AND D(10).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(2) AND NOT D(10).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(3)/IDE_BASEADR(3)_CLKF <= NOT (C1 XOR IDE_BASEADR(3)/IDE_BASEADR(3)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),IDE_BASEADR(3)/IDE_BASEADR(3)_CLKF,'0','0'); IDE_BASEADR_T(3) <= ((NOT IDE_BASEADR(3) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(3) AND D(11).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(3) AND NOT D(11).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(4)/IDE_BASEADR(4)_CLKF <= NOT (C1 XOR IDE_BASEADR(4)/IDE_BASEADR(4)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),IDE_BASEADR(4)/IDE_BASEADR(4)_CLKF,'0','0'); IDE_BASEADR_T(4) <= ((NOT IDE_BASEADR(4) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(4) AND D(12).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(4) AND NOT D(12).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(5)/IDE_BASEADR(5)_CLKF <= NOT (C1 XOR IDE_BASEADR(5)/IDE_BASEADR(5)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),IDE_BASEADR(5)/IDE_BASEADR(5)_CLKF,'0','0'); IDE_BASEADR_T(5) <= ((NOT IDE_BASEADR(5) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(5) AND D(13).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(5) AND NOT D(13).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(6)/IDE_BASEADR(6)_CLKF <= NOT (C1 XOR IDE_BASEADR(6)/IDE_BASEADR(6)_CLKF <= NOT (C3); FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),IDE_BASEADR(6)/IDE_BASEADR(6)_CLKF,'0','0'); IDE_BASEADR_T(6) <= ((NOT IDE_BASEADR(6) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(6) AND D(14).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(6) AND NOT D(14).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),IDE_BASEADR(7)/IDE_BASEADR(7)_CLKF,'0','0'); IDE_BASEADR_T(7) <= ((NOT IDE_BASEADR(7) AND NOT RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND NOT IDE_BASEADR(7) AND D(15).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND IDE_BASEADR(7) AND NOT D(15).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); IDE_BASEADR(7)/IDE_BASEADR(7)_CLKF <= NOT (C1 XOR IDE_BASEADR(7)/IDE_BASEADR(7)_CLKF <= NOT (C3); FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,IDE_ENABLE/IDE_ENABLE_CLKF,'0','0'); IDE_ENABLE_D <= ((NOT IDE_ENABLE AND RESET) OR (ide AND RESET AND NOT AS AND NOT RW)); IDE_ENABLE/IDE_ENABLE_CLKF <= NOT (C1 XOR IDE_ENABLE/IDE_ENABLE_CLKF <= NOT (C3); IDE_R_S/IDE_R_S_CLKF <= NOT (C1 XOR IDE_R_S/IDE_R_S_CLKF <= NOT (C3); IDE_W_S/IDE_W_S_CLKF <= NOT (C1 XOR IDE_W_S/IDE_W_S_CLKF <= NOT (C3); FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),LAN_BASEADR(0)/LAN_BASEADR(0)_CLKF,'0','0'); LAN_BASEADR_T(0) <= ((NOT LAN_BASEADR(0) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(0) AND D(8).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(0) AND NOT D(8).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(0)/LAN_BASEADR(0)_CLKF <= NOT (C1 XOR LAN_BASEADR(0)/LAN_BASEADR(0)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),LAN_BASEADR(1)/LAN_BASEADR(1)_CLKF,'0','0'); LAN_BASEADR_T(1) <= ((NOT LAN_BASEADR(1) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(1) AND D(9).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(1) AND NOT D(9).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(1)/LAN_BASEADR(1)_CLKF <= NOT (C1 XOR LAN_BASEADR(1)/LAN_BASEADR(1)_CLKF <= NOT (C3); LAN_BASEADR(2)/LAN_BASEADR(2)_CLKF <= NOT (C1 XOR LAN_BASEADR(2)/LAN_BASEADR(2)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),LAN_BASEADR(2)/LAN_BASEADR(2)_CLKF,'0','0'); LAN_BASEADR_T(2) <= ((NOT LAN_BASEADR(2) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(2) AND D(10).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(2) AND NOT D(10).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(3)/LAN_BASEADR(3)_CLKF <= NOT (C1 XOR LAN_BASEADR(3)/LAN_BASEADR(3)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),LAN_BASEADR(3)/LAN_BASEADR(3)_CLKF,'0','0'); LAN_BASEADR_T(3) <= ((NOT LAN_BASEADR(3) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(3) AND D(11).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(3) AND NOT D(11).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(4)/LAN_BASEADR(4)_CLKF <= NOT (C1 XOR LAN_BASEADR(4)/LAN_BASEADR(4)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),LAN_BASEADR(4)/LAN_BASEADR(4)_CLKF,'0','0'); LAN_BASEADR_T(4) <= ((NOT LAN_BASEADR(4) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(4) AND D(12).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(4) AND NOT D(12).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(5)/LAN_BASEADR(5)_CLKF <= NOT (C1 XOR LAN_BASEADR(5)/LAN_BASEADR(5)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),LAN_BASEADR(5)/LAN_BASEADR(5)_CLKF,'0','0'); LAN_BASEADR_T(5) <= ((NOT LAN_BASEADR(5) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(5) AND D(13).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(5) AND NOT D(13).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),LAN_BASEADR(6)/LAN_BASEADR(6)_CLKF,'0','0'); LAN_BASEADR_T(6) <= ((NOT LAN_BASEADR(6) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(6) AND D(14).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(6) AND NOT D(14).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(6)/LAN_BASEADR(6)_CLKF <= NOT (C1 XOR LAN_BASEADR(6)/LAN_BASEADR(6)_CLKF <= NOT (C3); FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),LAN_BASEADR(7)/LAN_BASEADR(7)_CLKF,'0','0'); LAN_BASEADR_T(7) <= ((NOT LAN_BASEADR(7) AND NOT RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(7) AND D(15).PIN AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(7) AND NOT D(15).PIN AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); LAN_BASEADR(7)/LAN_BASEADR(7)_CLKF <= NOT (C1 XOR LAN_BASEADR(7)/LAN_BASEADR(7)_CLKF <= NOT (C3); FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,'1',LAN_INT,NOT RESET,'0'); ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST <= ((NOT CP_IRQ) OR (LAN_INT_ENABLE AND NOT LAN_INT)); ROM_OE_S/ROM_OE_S_CLKF <= NOT (C1 XOR ROM_OE_S/ROM_OE_S_CLKF <= NOT (C3); SHUT_UP(0)/SHUT_UP(0)_CLKF <= NOT (C1 XOR SHUT_UP(0)/SHUT_UP(0)_CLKF <= NOT (C3); FDCPE_SHUT_UP0: FDCPE port map (SHUT_UP(0),SHUT_UP_D(0),SHUT_UP(0)/SHUT_UP(0)_CLKF,'0','0'); SHUT_UP_D(0) <= ((NOT SHUT_UP(0) AND RESET) OR (NOT AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),SHUT_UP(1)/SHUT_UP(1)_CLKF,'0','0'); SHUT_UP_D(1) <= ((NOT SHUT_UP(1) AND RESET) OR (AUTO_CONFIG_DONE(0) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); SHUT_UP(1)/SHUT_UP(1)_CLKF <= NOT (C1 XOR SHUT_UP(1)/SHUT_UP(1)_CLKF <= NOT (C3); SHUT_UP(2)/SHUT_UP(2)_CLKF <= NOT (C1 XOR SHUT_UP(2)/SHUT_UP(2)_CLKF <= NOT (C3); FDCPE_SHUT_UP2: FDCPE port map (SHUT_UP(2),SHUT_UP_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); SHUT_UP_D(2) <= ((NOT SHUT_UP(2) AND RESET) OR (AUTO_CONFIG_DONE(1) AND autoconfig AND RESET AND NOT A(5) AND NOT A(1) AND NOT A(2) AND A(3) AND NOT A(4) AND A(6) AND NOT AS AND NOT RW AND NOT UDS)); SLAVE_OBUF__$INT <= ((AS) OR (NOT CP_CS AND NOT ide AND NOT lan AND NOT autoconfig)); FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,lan/lan_CLKF,NOT ide/ide_RSTF__$INT,'0'); autoconfig_D <= ((NOT AUTO_CONFIG_DONE(0) AND NOT A(16) AND NOT A(17) AND NOT A(18) AND A(19) AND NOT A(20) AND A(21) AND A(22) AND A(23) AND NOT CFIN) OR (NOT AUTO_CONFIG_DONE(1) AND NOT A(16) AND NOT A(17) AND NOT A(18) AND A(19) AND NOT A(20) AND A(21) AND A(22) AND A(23) AND NOT CFIN) OR (NOT AUTO_CONFIG_DONE(2) AND NOT A(16) AND NOT A(17) AND NOT A(18) AND A(19) AND NOT A(20) AND A(21) AND A(22) AND A(23) AND NOT CFIN)); FDCPE_ide: FDCPE port map (ide,ide_D,lan/lan_CLKF,NOT ide/ide_RSTF__$INT,'0'); ide_D <= ((SHUT_UP(1)) OR (IDE_BASEADR(3) AND NOT A(19)) OR (NOT IDE_BASEADR(3) AND A(19)) OR (IDE_BASEADR(6) AND NOT A(22)) OR (NOT IDE_BASEADR(6) AND A(22)) OR (IDE_BASEADR(7) AND NOT A(23)) OR (NOT IDE_BASEADR(7) AND A(23)) OR (IDE_BASEADR(5) AND NOT A(21)) OR (NOT IDE_BASEADR(5) AND A(21)) OR (IDE_BASEADR(4) AND NOT A(20)) OR (NOT IDE_BASEADR(4) AND A(20)) OR (IDE_BASEADR(0) AND NOT A(16)) OR (NOT IDE_BASEADR(0) AND A(16)) OR (IDE_BASEADR(1) AND NOT A(17)) OR (NOT IDE_BASEADR(1) AND A(17)) OR (IDE_BASEADR(2) AND NOT A(18)) OR (NOT IDE_BASEADR(2) AND A(18))); ide/ide_RSTF__$INT <= (RESET AND BERR); FDCPE_lan: FDCPE port map (lan,lan_D,lan/lan_CLKF,NOT ide/ide_RSTF__$INT,'0'); lan_D <= ((SHUT_UP(0)) OR (LAN_BASEADR(3) AND NOT A(19)) OR (NOT LAN_BASEADR(3) AND A(19)) OR (LAN_BASEADR(6) AND NOT A(22)) OR (NOT LAN_BASEADR(6) AND A(22)) OR (LAN_BASEADR(7) AND NOT A(23)) OR (NOT LAN_BASEADR(7) AND A(23)) OR (LAN_BASEADR(4) AND NOT A(20)) OR (NOT LAN_BASEADR(4) AND A(20)) OR (LAN_BASEADR(5) AND NOT A(21)) OR (NOT LAN_BASEADR(5) AND A(21)) OR (LAN_BASEADR(0) AND NOT A(16)) OR (NOT LAN_BASEADR(0) AND A(16)) OR (LAN_BASEADR(1) AND NOT A(17)) OR (NOT LAN_BASEADR(1) AND A(17)) OR (LAN_BASEADR(2) AND NOT A(18)) OR (NOT LAN_BASEADR(2) AND A(18))); lan/lan_CLKF <= C1 XOR lan/lan_CLKF <= C3; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25