Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.16 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.16 secs --> Reading design: LAN_IDE_CP.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "LAN_IDE_CP.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "LAN_IDE_CP" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : LAN_IDE_CP Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. Synthesizing Unit . Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:2565 - Inout > is never assigned. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. INFO:Xst:1799 - State start_read_upper is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 12 | | Transitions | 17 | | Inputs | 3 | | Outputs | 12 | | Clock | CLK_EXT (rising_edge) | | Reset | LAN_SM_RST (positive) | | Reset type | asynchronous | | Reset State | nop | | Power Up State | nop | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 8 | | Inputs | 0 | | Outputs | 30 | | Clock | CLK_EXT (rising_edge) | | Reset | RESET (positive) | | Reset type | asynchronous | | Reset State | nop | | Power Up State | nop | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 16x8-bit ROM for signal . Found 16-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 4-bit tristate buffer for signal . Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 4-bit comparator less for signal created at line 533. Found 16-bit register for signal . Found 1-bit register for signal . Found 2-bit comparator less for signal created at line 249. Found 14-bit register for signal . Found 1-bit register for signal . Found 16-bit comparator equal for signal created at line 248. Found 16-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit comparator less for signal created at line 367. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 14-bit register for signal . Found 32-bit register for signal . Summary: inferred 2 Finite State Machine(s). inferred 1 ROM(s). inferred 49 D-type flip-flop(s). inferred 4 Comparator(s). inferred 57 Tristate(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 1 16x8-bit ROM : 1 # Registers : 56 1-bit register : 50 14-bit register : 2 16-bit register : 3 8-bit register : 1 # Comparators : 4 16-bit comparator equal : 1 2-bit comparator less : 2 4-bit comparator less : 1 # Tristates : 27 1-bit tristate buffer : 25 16-bit tristate buffer : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------------ State | Encoding ------------------------ nop | 000 wait0 | 001 clr | 011 clr_commit | 010 wait1 | 110 set | 111 set_commit | 101 done | 100 ------------------------ Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. ----------------------------------- State | Encoding ----------------------------------- nop | 000000000001 start_read_upper | unreached wait_read_upper | 000000000010 end_read_upper | 000000100000 start_read_lower | 000001000000 wait_read_lower | 000000000100 end_read_lower | 000010000000 start_write_upper | 000000001000 wait_write_upper | 000100000000 end_write_upper | 001000000000 start_write_lower | 000000010000 wait_write_lower | 010000000000 end_write_lower | 100000000000 ----------------------------------- WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <11>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <10>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <9>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <8>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <7>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <5>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <4>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <2>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <1>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <0>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <15>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <14>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <13>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <12>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 2 # ROMs : 1 16x8-bit ROM : 1 # Registers : 49 Flip-Flops : 49 # Comparators : 1 16-bit comparator equal : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : Optimizing unit ... implementation constraint: INIT=s : LAN_SM_FSM_FFd12 implementation constraint: INIT=s : D_OUT_7 implementation constraint: INIT=s : D_OUT_6 implementation constraint: INIT=s : D_OUT_5 implementation constraint: INIT=s : LAN_A_INIT_3 implementation constraint: INIT=s : D_OUT_4 implementation constraint: INIT=s : D_OUT_3 implementation constraint: INIT=s : LAN_A_INIT_6 implementation constraint: INIT=s : D_OUT_2 implementation constraint: INIT=s : D_OUT_1 implementation constraint: INIT=s : D_OUT_0 implementation constraint: INIT=r : LAN_D_INIT_1 implementation constraint: INIT=r : LAN_D_INIT_8 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3 implementation constraint: INIT=r : LAN_SM_FSM_FFd1 implementation constraint: INIT=r : LAN_SM_FSM_FFd2 implementation constraint: INIT=r : LAN_SM_FSM_FFd3 implementation constraint: INIT=r : LAN_SM_FSM_FFd4 implementation constraint: INIT=r : LAN_SM_FSM_FFd5 implementation constraint: INIT=r : LAN_SM_FSM_FFd6 implementation constraint: INIT=r : LAN_SM_FSM_FFd7 implementation constraint: INIT=r : LAN_SM_FSM_FFd8 implementation constraint: INIT=r : LAN_SM_FSM_FFd9 implementation constraint: INIT=r : LAN_SM_FSM_FFd10 implementation constraint: INIT=r : LAN_SM_FSM_FFd11 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : LAN_IDE_CP.ngr Top Level Output File Name : LAN_IDE_CP Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 116 Cell Usage : # BELS : 759 # AND2 : 249 # AND3 : 28 # AND4 : 5 # AND8 : 4 # GND : 1 # INV : 220 # OR2 : 190 # OR3 : 25 # OR4 : 3 # OR8 : 16 # VCC : 1 # XOR2 : 17 # FlipFlops/Latches : 123 # FD : 1 # FDC : 24 # FDCE : 4 # FDP : 44 # FDPE : 50 # IO Buffers : 109 # IBUF : 19 # IOBUFE : 48 # OBUF : 33 # OBUFE : 9 ========================================================================= Total REAL time to Xst completion: 9.00 secs Total CPU time to Xst completion: 9.22 secs --> Total memory usage is 4534788 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 51 ( 0 filtered) Number of infos : 10 ( 0 filtered)