cpldfit: version P.68d Xilinx Inc. Fitter Report Design Name: LAN_IDE_CP Date: 12-28-2016, 11:45PM Device Used: XC95144XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 111/144 ( 77%) 321 /720 ( 45%) 230/432 ( 53%) 35 /144 ( 24%) 105/117 ( 90%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 34/54 51/90 14/15 FB2 18/18* 29/54 42/90 15/15* FB3 12/18 30/54 63/90 13/15 FB4 18/18* 29/54 31/90 15/15* FB5 4/18 19/54 20/90 14/14* FB6 18/18* 33/54 46/90 12/13 FB7 18/18* 29/54 38/90 11/15 FB8 6/18 27/54 30/90 11/15 ----- ----- ----- ----- 111/144 230/432 321/720 105/117 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Signal 'RESET' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 32 32 | I/O : 99 109 Output : 40 40 | GCK/IO : 1 3 Bidirectional : 32 32 | GTS/IO : 4 4 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 105 105 ** Power Data ** There are 111 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be deleted. WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will be deleted. WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 72 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State IDE_CS<1> 1 1 FB1_1 23 I/O O STD FAST D<7> 2 5 FB1_2 16 I/O I/O STD FAST D<1> 2 5 FB1_3 17 I/O I/O STD FAST IDE_A<2> 1 1 FB1_4 25 I/O O STD FAST D<8> 2 5 FB1_5 19 I/O I/O STD FAST D<5> 2 5 FB1_6 20 I/O I/O STD FAST D<4> 2 5 FB1_8 21 I/O I/O STD FAST IDE_CS<0> 1 1 FB1_9 22 I/O O STD FAST IDE_A<0> 1 1 FB1_11 24 I/O O STD FAST IDE_A<1> 1 1 FB1_12 26 I/O O STD FAST IDE_R 2 6 FB1_14 27 I/O O STD FAST RESET IDE_W 2 5 FB1_15 28 I/O O STD FAST RESET ROM_OE 2 6 FB1_16 35 I/O O STD FAST RESET A_LAN<9> 1 1 FB2_1 142 I/O O STD FAST A_LAN<0> 1 1 FB2_4 4 I/O O STD FAST D<0> 2 5 FB2_5 2 GTS/I/O I/O STD FAST A_LAN<1> 1 1 FB2_6 3 GTS/I/O O STD FAST A_LAN<3> 1 1 FB2_8 5 GTS/I/O O STD FAST A_LAN<2> 1 1 FB2_9 6 GTS/I/O O STD FAST A_LAN<5> 1 1 FB2_10 7 I/O O STD FAST A_LAN<4> 1 1 FB2_11 9 I/O O STD FAST A_LAN<7> 1 1 FB2_12 10 I/O O STD FAST LAN_CFG<1> 0 0 FB2_13 12 I/O O STD FAST A_LAN<6> 1 1 FB2_14 11 I/O O STD FAST LAN_CFG<3> 0 0 FB2_15 13 I/O O STD FAST D<6> 2 5 FB2_16 14 I/O I/O STD FAST D<3> 2 5 FB2_17 15 I/O I/O STD FAST D<2> 2 5 FB3_1 39 I/O I/O STD FAST INT_OUT 1 1 FB3_2 32 GCK/I/O O STD FAST D<10> 2 5 FB3_3 41 I/O I/O STD FAST D<12> 5 6 FB3_4 44 I/O I/O STD FAST CP_CS 0 0 FB3_6 34 I/O O STD FAST D<14> 5 6 FB3_7 46 I/O I/O STD FAST D<9> 2 5 FB3_9 40 I/O I/O STD FAST D<15> 5 6 FB3_10 48 I/O I/O STD FAST D<11> 2 5 FB3_11 43 I/O I/O STD FAST D<13> 5 6 FB3_12 45 I/O I/O STD FAST DQ<0> 2 3 FB4_1 118 I/O I/O STD FAST DQ<6> 2 3 FB4_2 126 I/O I/O STD FAST LAN_CS 0 0 FB4_3 133 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DQ<8> 2 3 FB4_5 128 I/O I/O STD FAST DQ<10> 2 3 FB4_6 129 I/O I/O STD FAST DQ<12> 2 3 FB4_8 130 I/O I/O STD FAST DQ<14> 2 3 FB4_9 131 I/O I/O STD FAST LAN_CFG<2> 0 0 FB4_10 135 I/O O STD FAST LAN_WRH 1 4 FB4_11 132 I/O O STD FAST LAN_RD 1 3 FB4_12 134 I/O O STD FAST A_LAN<12> 1 1 FB4_13 137 I/O O STD FAST A_LAN<13> 1 1 FB4_14 136 I/O O STD FAST A_LAN<10> 1 1 FB4_15 138 I/O O STD FAST A_LAN<11> 1 1 FB4_16 139 I/O O STD FAST A_LAN<8> 1 1 FB4_17 140 I/O O STD FAST ROM_B<0> 0 0 FB5_10 68 I/O O STD FAST CP_WE 0 0 FB5_13 70 I/O O STD FAST ROM_B<1> 1 0 FB5_17 69 I/O O STD FAST SLAVE 2 4 FB6_2 106 I/O O STD FAST LAN_CFG<4> 0 0 FB6_5 110 I/O O STD FAST DQ<15> 2 3 FB6_6 112 I/O I/O STD FAST DQ<13> 2 3 FB6_8 113 I/O I/O STD FAST DQ<9> 2 3 FB6_9 116 I/O I/O STD FAST DQ<11> 2 3 FB6_10 115 I/O I/O STD FAST DQ<3> 2 3 FB6_11 119 I/O I/O STD FAST DQ<2> 2 3 FB6_12 120 I/O I/O STD FAST DQ<5> 2 3 FB6_14 121 I/O I/O STD FAST DQ<4> 2 3 FB6_15 124 I/O I/O STD FAST DQ<1> 2 3 FB6_16 117 I/O I/O STD FAST DQ<7> 2 3 FB6_17 125 I/O I/O STD FAST CP_RD 0 0 FB7_2 71 I/O O STD FAST LAN_WRL 1 4 FB7_6 76 I/O O STD FAST DTACK 0 0 FB7_12 85 I/O O STD FAST OWN 1 1 FB8_16 107 I/O O STD FAST CFOUT 1 3 FB8_17 105 I/O O STD FAST ** 39 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State SHUT_UP<0> 3 14 FB1_7 STD RESET LAN_BASEADR<0> 4 15 FB1_10 STD RESET IDE_BASEADR<0> 4 15 FB1_13 STD RESET Dout1<1> 19 15 FB1_18 STD RESET LAN_BASEADR<1> 4 15 FB2_2 STD RESET IDE_BASEADR<2> 4 15 FB2_3 STD RESET Dout1<3> 15 15 FB2_7 STD RESET IDE_BASEADR<1> 4 15 FB2_18 STD RESET Dout1<0> 18 16 FB3_14 STD RESET Dout1<2> 16 15 FB3_17 STD RESET IDE_BASEADR<6> 4 15 FB4_4 STD RESET IDE_BASEADR<4> 4 15 FB4_7 STD RESET IDE_BASEADR<3> 4 15 FB4_18 STD RESET lan 19 19 FB5_18 STD RESET LAN_BASEADR<7> 4 15 FB6_1 STD RESET LAN_BASEADR<5> 4 15 FB6_3 STD RESET LAN_BASEADR<3> 4 15 FB6_4 STD RESET LAN_BASEADR<2> 4 15 FB6_7 STD RESET IDE_BASEADR<7> 4 15 FB6_13 STD RESET IDE_BASEADR<5> 4 15 FB6_18 STD RESET lan/lan_RSTF__$INT 1 2 FB7_1 STD $OpTx$$OpTx$FX_DC$84_INV$97 1 2 FB7_3 STD autoconfig/autoconfig_CLKF 2 2 FB7_4 STD SLAVE_OBUF__$INT 2 4 FB7_5 STD SHUT_UP<2>/SHUT_UP<2>_CLKF 2 2 FB7_7 STD AUTO_CONFIG_DONE<2> 2 2 FB7_8 STD RESET AUTO_CONFIG_DONE<1> 2 2 FB7_9 STD RESET AUTO_CONFIG_DONE<0> 2 2 FB7_10 STD RESET SHUT_UP<2> 3 14 FB7_11 STD RESET IDE_ENABLE 3 6 FB7_13 STD RESET AUTO_CONFIG_DONE_CYCLE<2> 3 13 FB7_14 STD RESET AUTO_CONFIG_DONE_CYCLE<1> 3 13 FB7_15 STD RESET AUTO_CONFIG_DONE_CYCLE<0> 3 13 FB7_16 STD RESET LAN_BASEADR<6> 4 15 FB7_17 STD RESET LAN_BASEADR<4> 4 15 FB7_18 STD RESET lan/lan_CLKF 2 2 FB8_13 STD ide/ide_CLKF 2 2 FB8_14 STD autoconfig 5 14 FB8_15 STD RESET ide 19 19 FB8_18 STD RESET ** 33 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CP_IRQ FB1_10 31 I/O I RESET FB2_2 143 GSR/I/O GSR/I A<5> FB3_14 49 I/O I A<4> FB3_15 50 I/O I A<6> FB3_17 51 I/O I A<3> FB5_2 52 I/O I A<10> FB5_3 59 I/O I A<7> FB5_5 53 I/O I A<2> FB5_6 54 I/O I A<14> FB5_7 66 I/O I A<8> FB5_8 56 I/O I A<1> FB5_9 57 I/O I A<9> FB5_11 58 I/O I A<11> FB5_12 60 I/O I A<12> FB5_14 61 I/O I A<13> FB5_15 64 I/O I AUTOBOOT_OFF FB7_3 75 I/O I AS FB7_9 80 I/O I LDS FB7_11 82 I/O I UDS FB7_13 81 I/O I A<23> FB7_14 86 I/O I A<22> FB7_15 87 I/O I RW FB7_16 83 I/O I A<21> FB7_17 88 I/O I A<20> FB8_2 91 I/O I A<17> FB8_3 95 I/O I A<16> FB8_4 97 I/O I A<19> FB8_5 92 I/O I A<18> FB8_8 94 I/O I BERR FB8_11 98 I/O I C1 FB8_13 103 I/O I C3 FB8_14 102 I/O I CFIN FB8_15 104 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 34/20 Number of signals used by logic mapping into function block: 34 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use IDE_CS<1> 1 1<- /\5 0 FB1_1 23 I/O O D<7> 2 0 /\1 2 FB1_2 16 I/O I/O D<1> 2 0 0 3 FB1_3 17 I/O I/O IDE_A<2> 1 0 0 4 FB1_4 25 I/O O D<8> 2 0 0 3 FB1_5 19 I/O I/O D<5> 2 0 0 3 FB1_6 20 I/O I/O SHUT_UP<0> 3 0 0 2 FB1_7 (b) (b) D<4> 2 0 0 3 FB1_8 21 I/O I/O IDE_CS<0> 1 0 0 4 FB1_9 22 I/O O LAN_BASEADR<0> 4 0 0 1 FB1_10 31 I/O I IDE_A<0> 1 0 0 4 FB1_11 24 I/O O IDE_A<1> 1 0 0 4 FB1_12 26 I/O O IDE_BASEADR<0> 4 0 0 1 FB1_13 (b) (b) IDE_R 2 0 0 3 FB1_14 27 I/O O IDE_W 2 0 \/1 2 FB1_15 28 I/O O ROM_OE 2 1<- \/4 0 FB1_16 35 I/O O (unused) 0 0 \/5 0 FB1_17 30 GCK/I/O (b) Dout1<1> 19 14<- 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$84_INV$97 13: A<5> 24: DQ<5>.PIN 2: AS 14: A<6> 25: DQ<4>.PIN 3: AUTO_CONFIG_DONE<0> 15: A<9> 26: DQ<1>.PIN 4: AUTO_CONFIG_DONE<1> 16: A<10> 27: RESET 5: AUTO_CONFIG_DONE<2> 17: D<8>.PIN 28: RW 6: A<1> 18: Dout1<1> 29: SHUT_UP<0> 7: A<11> 19: IDE_BASEADR<0> 30: SHUT_UP<2>/SHUT_UP<2>_CLKF 8: A<12> 20: IDE_ENABLE 31: UDS 9: A<13> 21: LAN_BASEADR<0> 32: autoconfig 10: A<2> 22: DQ<8>.PIN 33: ide 11: A<3> 23: DQ<7>.PIN 34: lan 12: A<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs IDE_CS<1> ........X............................... 1 D<7> XX....................X....X.....X...... 5 D<1> XX.......................X.X.....X...... 5 IDE_A<2> ......X................................. 1 D<8> XX...................X.....X.....X...... 5 D<5> XX.....................X...X.....X...... 5 SHUT_UP<0> .XX..X...XXXXX............XXXXXX........ 14 D<4> XX......................X..X.....X...... 5 IDE_CS<0> .......X................................ 1 LAN_BASEADR<0> .XX..X...XXXXX..X...X.....XX.XXX........ 15 IDE_A<0> ..............X......................... 1 IDE_A<1> ...............X........................ 1 IDE_BASEADR<0> .X.X.X...XXXXX..X.X.......XX.XXX........ 15 IDE_R .X.................X......XX.X..X....... 6 IDE_W .X........................XX.X..X....... 5 ROM_OE .X.................X......XX.X..X....... 6 Dout1<1> .XXXXX...XXXXX...X........XX.X.X........ 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use A_LAN<9> 1 0 0 4 FB2_1 142 I/O O LAN_BASEADR<1> 4 0 0 1 FB2_2 143 GSR/I/O GSR/I IDE_BASEADR<2> 4 0 0 1 FB2_3 (b) (b) A_LAN<0> 1 0 0 4 FB2_4 4 I/O O D<0> 2 0 \/1 2 FB2_5 2 GTS/I/O I/O A_LAN<1> 1 1<- \/5 0 FB2_6 3 GTS/I/O O Dout1<3> 15 10<- 0 0 FB2_7 (b) (b) A_LAN<3> 1 1<- /\5 0 FB2_8 5 GTS/I/O O A_LAN<2> 1 0 /\1 3 FB2_9 6 GTS/I/O O A_LAN<5> 1 0 0 4 FB2_10 7 I/O O A_LAN<4> 1 0 0 4 FB2_11 9 I/O O A_LAN<7> 1 0 0 4 FB2_12 10 I/O O LAN_CFG<1> 0 0 0 5 FB2_13 12 I/O O A_LAN<6> 1 0 0 4 FB2_14 11 I/O O LAN_CFG<3> 0 0 0 5 FB2_15 13 I/O O D<6> 2 0 0 3 FB2_16 14 I/O I/O D<3> 2 0 0 3 FB2_17 15 I/O I/O IDE_BASEADR<1> 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$84_INV$97 11: A<6> 21: DQ<6>.PIN 2: AS 12: A<7> 22: DQ<3>.PIN 3: AUTO_CONFIG_DONE<0> 13: A<8> 23: DQ<0>.PIN 4: AUTO_CONFIG_DONE<1> 14: A<10> 24: RESET 5: AUTO_CONFIG_DONE<2> 15: D<10>.PIN 25: RW 6: A<1> 16: D<9>.PIN 26: SHUT_UP<2>/SHUT_UP<2>_CLKF 7: A<2> 17: Dout1<3> 27: UDS 8: A<3> 18: IDE_BASEADR<1> 28: autoconfig 9: A<4> 19: IDE_BASEADR<2> 29: lan 10: A<5> 20: LAN_BASEADR<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs A_LAN<9> .............X.......................... 1 LAN_BASEADR<1> .XX..XXXXXX....X...X...XXXXX............ 15 IDE_BASEADR<2> .X.X.XXXXXX...X...X....XXXXX............ 15 A_LAN<0> .....X.................................. 1 D<0> XX....................X.X...X........... 5 A_LAN<1> ......X................................. 1 Dout1<3> .XXXXXXXXXX.....X......XXX.X............ 15 A_LAN<3> ........X............................... 1 A_LAN<2> .......X................................ 1 A_LAN<5> ..........X............................. 1 A_LAN<4> .........X.............................. 1 A_LAN<7> ............X........................... 1 LAN_CFG<1> ........................................ 0 A_LAN<6> ...........X............................ 1 LAN_CFG<3> ........................................ 0 D<6> XX..................X...X...X........... 5 D<3> XX...................X..X...X........... 5 IDE_BASEADR<1> .X.X.XXXXXX....X.X.....XXXXX............ 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 30/24 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use D<2> 2 0 /\1 2 FB3_1 39 I/O I/O INT_OUT 1 0 0 4 FB3_2 32 GCK/I/O O D<10> 2 0 0 3 FB3_3 41 I/O I/O D<12> 5 0 0 0 FB3_4 44 I/O I/O (unused) 0 0 0 5 FB3_5 33 I/O CP_CS 0 0 0 5 FB3_6 34 I/O O D<14> 5 0 0 0 FB3_7 46 I/O I/O (unused) 0 0 0 5 FB3_8 38 GCK/I/O D<9> 2 0 0 3 FB3_9 40 I/O I/O D<15> 5 0 0 0 FB3_10 48 I/O I/O D<11> 2 0 \/3 0 FB3_11 43 I/O I/O D<13> 5 3<- \/3 0 FB3_12 45 I/O I/O (unused) 0 0 \/5 0 FB3_13 (b) (b) Dout1<0> 18 13<- 0 0 FB3_14 49 I/O I (unused) 0 0 /\5 0 FB3_15 50 I/O I (unused) 0 0 \/5 0 FB3_16 (b) (b) Dout1<2> 16 11<- 0 0 FB3_17 51 I/O I (unused) 0 0 /\5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$84_INV$97 11: A<5> 21: DQ<12>.PIN 2: AS 12: A<6> 22: DQ<11>.PIN 3: AUTOBOOT_OFF 13: CP_IRQ 23: DQ<10>.PIN 4: AUTO_CONFIG_DONE<0> 14: Dout1<0> 24: DQ<9>.PIN 5: AUTO_CONFIG_DONE<1> 15: Dout1<1> 25: DQ<2>.PIN 6: AUTO_CONFIG_DONE<2> 16: Dout1<2> 26: RESET 7: A<1> 17: Dout1<3> 27: RW 8: A<2> 18: DQ<15>.PIN 28: SHUT_UP<2>/SHUT_UP<2>_CLKF 9: A<3> 19: DQ<14>.PIN 29: autoconfig 10: A<4> 20: DQ<13>.PIN 30: lan Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D<2> XX......................X.X..X.......... 5 INT_OUT ............X........................... 1 D<10> XX....................X...X..X.......... 5 D<12> XX...........X......X.....X..X.......... 6 CP_CS ........................................ 0 D<14> XX.............X..X.......X..X.......... 6 D<9> XX.....................X..X..X.......... 5 D<15> XX..............XX........X..X.......... 6 D<11> XX...................X....X..X.......... 5 D<13> XX............X....X......X..X.......... 6 Dout1<0> .XXXXXXXXXXX.X...........XXXX........... 16 Dout1<2> .X.XXXXXXXXX...X.........XXXX........... 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ<0> 2 0 0 3 FB4_1 118 I/O I/O DQ<6> 2 0 0 3 FB4_2 126 I/O I/O LAN_CS 0 0 0 5 FB4_3 133 I/O O IDE_BASEADR<6> 4 0 0 1 FB4_4 (b) (b) DQ<8> 2 0 0 3 FB4_5 128 I/O I/O DQ<10> 2 0 0 3 FB4_6 129 I/O I/O IDE_BASEADR<4> 4 0 0 1 FB4_7 (b) (b) DQ<12> 2 0 0 3 FB4_8 130 I/O I/O DQ<14> 2 0 0 3 FB4_9 131 I/O I/O LAN_CFG<2> 0 0 0 5 FB4_10 135 I/O O LAN_WRH 1 0 0 4 FB4_11 132 I/O O LAN_RD 1 0 0 4 FB4_12 134 I/O O A_LAN<12> 1 0 0 4 FB4_13 137 I/O O A_LAN<13> 1 0 0 4 FB4_14 136 I/O O A_LAN<10> 1 0 0 4 FB4_15 138 I/O O A_LAN<11> 1 0 0 4 FB4_16 139 I/O O A_LAN<8> 1 0 0 4 FB4_17 140 I/O O IDE_BASEADR<3> 4 0 0 1 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: AS 11: A<5> 21: IDE_BASEADR<3> 2: AUTO_CONFIG_DONE<1> 12: A<6> 22: IDE_BASEADR<4> 3: A<1> 13: A<9> 23: IDE_BASEADR<6> 4: A<11> 14: D<0>.PIN 24: RESET 5: A<12> 15: D<10>.PIN 25: RW 6: A<13> 16: D<11>.PIN 26: SHUT_UP<2>/SHUT_UP<2>_CLKF 7: A<14> 17: D<12>.PIN 27: UDS 8: A<2> 18: D<14>.PIN 28: autoconfig 9: A<3> 19: D<6>.PIN 29: lan 10: A<4> 20: D<8>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ<0> X............X..........X............... 3 DQ<6> X.................X.....X............... 3 LAN_CS ........................................ 0 IDE_BASEADR<6> XXX....XXXXX.....X....XXXXXX............ 15 DQ<8> X..................X....X............... 3 DQ<10> X.............X.........X............... 3 IDE_BASEADR<4> XXX....XXXXX....X....X.XXXXX............ 15 DQ<12> X...............X.......X............... 3 DQ<14> X................X......X............... 3 LAN_CFG<2> ........................................ 0 LAN_WRH X.......................X.X.X........... 4 LAN_RD X.......................X...X........... 3 A_LAN<12> .....X.................................. 1 A_LAN<13> ......X................................. 1 A_LAN<10> ...X.................................... 1 A_LAN<11> ....X................................... 1 A_LAN<8> ............X........................... 1 IDE_BASEADR<3> XXX....XXXXX...X....X..XXXXX............ 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB5_1 (b) (b) (unused) 0 0 /\4 1 FB5_2 52 I/O I (unused) 0 0 0 5 FB5_3 59 I/O I (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 53 I/O I (unused) 0 0 0 5 FB5_6 54 I/O I (unused) 0 0 0 5 FB5_7 66 I/O I (unused) 0 0 0 5 FB5_8 56 I/O I (unused) 0 0 0 5 FB5_9 57 I/O I ROM_B<0> 0 0 0 5 FB5_10 68 I/O O (unused) 0 0 0 5 FB5_11 58 I/O I (unused) 0 0 0 5 FB5_12 60 I/O I CP_WE 0 0 0 5 FB5_13 70 I/O O (unused) 0 0 0 5 FB5_14 61 I/O I (unused) 0 0 0 5 FB5_15 64 I/O I (unused) 0 0 0 5 FB5_16 (b) (b) ROM_B<1> 1 1<- \/5 0 FB5_17 69 I/O O lan 19 14<- 0 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: A<16> 8: A<23> 14: LAN_BASEADR<5> 2: A<17> 9: LAN_BASEADR<0> 15: LAN_BASEADR<6> 3: A<18> 10: LAN_BASEADR<1> 16: LAN_BASEADR<7> 4: A<19> 11: LAN_BASEADR<2> 17: SHUT_UP<0> 5: A<20> 12: LAN_BASEADR<3> 18: lan/lan_CLKF 6: A<21> 13: LAN_BASEADR<4> 19: lan/lan_RSTF__$INT 7: A<22> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ROM_B<0> ........................................ 0 CP_WE ........................................ 0 ROM_B<1> ........................................ 0 lan XXXXXXXXXXXXXXXXXXX..................... 19 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 33/21 Number of signals used by logic mapping into function block: 33 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_BASEADR<7> 4 0 0 1 FB6_1 (b) (b) SLAVE 2 0 0 3 FB6_2 106 I/O O LAN_BASEADR<5> 4 0 0 1 FB6_3 (b) (b) LAN_BASEADR<3> 4 0 0 1 FB6_4 111 I/O (b) LAN_CFG<4> 0 0 0 5 FB6_5 110 I/O O DQ<15> 2 0 0 3 FB6_6 112 I/O I/O LAN_BASEADR<2> 4 0 0 1 FB6_7 (b) (b) DQ<13> 2 0 0 3 FB6_8 113 I/O I/O DQ<9> 2 0 0 3 FB6_9 116 I/O I/O DQ<11> 2 0 0 3 FB6_10 115 I/O I/O DQ<3> 2 0 0 3 FB6_11 119 I/O I/O DQ<2> 2 0 0 3 FB6_12 120 I/O I/O IDE_BASEADR<7> 4 0 0 1 FB6_13 (b) (b) DQ<5> 2 0 0 3 FB6_14 121 I/O I/O DQ<4> 2 0 0 3 FB6_15 124 I/O I/O DQ<1> 2 0 0 3 FB6_16 117 I/O I/O DQ<7> 2 0 0 3 FB6_17 125 I/O I/O IDE_BASEADR<5> 4 0 0 1 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: AS 12: D<13>.PIN 23: LAN_BASEADR<2> 2: AUTO_CONFIG_DONE<0> 13: D<15>.PIN 24: LAN_BASEADR<3> 3: AUTO_CONFIG_DONE<1> 14: D<1>.PIN 25: LAN_BASEADR<5> 4: A<1> 15: D<2>.PIN 26: LAN_BASEADR<7> 5: A<2> 16: D<3>.PIN 27: RESET 6: A<3> 17: D<4>.PIN 28: RW 7: A<4> 18: D<5>.PIN 29: SHUT_UP<2>/SHUT_UP<2>_CLKF 8: A<5> 19: D<7>.PIN 30: UDS 9: A<6> 20: D<9>.PIN 31: autoconfig 10: D<10>.PIN 21: IDE_BASEADR<5> 32: ide 11: D<11>.PIN 22: IDE_BASEADR<7> 33: lan Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_BASEADR<7> XX.XXXXXX...X............XXXXXX......... 15 SLAVE X.............................XXX....... 4 LAN_BASEADR<5> XX.XXXXXX..X............X.XXXXX......... 15 LAN_BASEADR<3> XX.XXXXXX.X............X..XXXXX......... 15 LAN_CFG<4> ........................................ 0 DQ<15> X...........X..............X............ 3 LAN_BASEADR<2> XX.XXXXXXX............X...XXXXX......... 15 DQ<13> X..........X...............X............ 3 DQ<9> X..................X.......X............ 3 DQ<11> X.........X................X............ 3 DQ<3> X..............X...........X............ 3 DQ<2> X.............X............X............ 3 IDE_BASEADR<7> X.XXXXXXX...X........X....XXXXX......... 15 DQ<5> X................X.........X............ 3 DQ<4> X...............X..........X............ 3 DQ<1> X............X.............X............ 3 DQ<7> X.................X........X............ 3 IDE_BASEADR<5> X.XXXXXXX..X........X.....XXXXX......... 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use lan/lan_RSTF__$INT 1 0 0 4 FB7_1 (b) (b) CP_RD 0 0 0 5 FB7_2 71 I/O O $OpTx$$OpTx$FX_DC$84_INV$97 1 0 0 4 FB7_3 75 I/O I autoconfig/autoconfig_CLKF 2 0 0 3 FB7_4 (b) (b) SLAVE_OBUF__$INT 2 0 0 3 FB7_5 74 I/O (b) LAN_WRL 1 0 0 4 FB7_6 76 I/O O SHUT_UP<2>/SHUT_UP<2>_CLKF 2 0 0 3 FB7_7 77 I/O (b) AUTO_CONFIG_DONE<2> 2 0 0 3 FB7_8 78 I/O (b) AUTO_CONFIG_DONE<1> 2 0 0 3 FB7_9 80 I/O I AUTO_CONFIG_DONE<0> 2 0 0 3 FB7_10 79 I/O (b) SHUT_UP<2> 3 0 0 2 FB7_11 82 I/O I DTACK 0 0 0 5 FB7_12 85 I/O O IDE_ENABLE 3 0 0 2 FB7_13 81 I/O I AUTO_CONFIG_DONE_CYCLE<2> 3 0 0 2 FB7_14 86 I/O I AUTO_CONFIG_DONE_CYCLE<1> 3 0 0 2 FB7_15 87 I/O I AUTO_CONFIG_DONE_CYCLE<0> 3 0 0 2 FB7_16 83 I/O I LAN_BASEADR<6> 4 0 0 1 FB7_17 88 I/O I LAN_BASEADR<4> 4 0 0 1 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: AS 11: A<5> 21: LDS 2: AUTO_CONFIG_DONE<0> 12: A<6> 22: RESET 3: AUTO_CONFIG_DONE<1> 13: BERR 23: RW 4: AUTO_CONFIG_DONE_CYCLE<0> 14: C1 24: SHUT_UP<2> 5: AUTO_CONFIG_DONE_CYCLE<1> 15: C3 25: SHUT_UP<2>/SHUT_UP<2>_CLKF 6: AUTO_CONFIG_DONE_CYCLE<2> 16: D<12>.PIN 26: UDS 7: A<1> 17: D<14>.PIN 27: autoconfig 8: A<2> 18: IDE_ENABLE 28: ide 9: A<3> 19: LAN_BASEADR<4> 29: lan 10: A<4> 20: LAN_BASEADR<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs lan/lan_RSTF__$INT ............X........X.................. 2 CP_RD ........................................ 0 $OpTx$$OpTx$FX_DC$84_INV$97 ..........................X.X........... 2 autoconfig/autoconfig_CLKF .............XX......................... 2 SLAVE_OBUF__$INT X.........................XXX........... 4 LAN_WRL X...................X.X.....X........... 4 SHUT_UP<2>/SHUT_UP<2>_CLKF .............XX......................... 2 AUTO_CONFIG_DONE<2> X....X.................................. 2 AUTO_CONFIG_DONE<1> X...X................................... 2 AUTO_CONFIG_DONE<0> X..X.................................... 2 SHUT_UP<2> X.X...XXXXXX.........XXXXXX............. 14 DTACK ........................................ 0 IDE_ENABLE X................X...XX.X..X............ 6 AUTO_CONFIG_DONE_CYCLE<2> X.X..XX.XXXX.........XX.XXX............. 13 AUTO_CONFIG_DONE_CYCLE<1> XX..X.X.XXXX.........XX.XXX............. 13 AUTO_CONFIG_DONE_CYCLE<0> XX.X..X.XXXX.........XX.XXX............. 13 LAN_BASEADR<6> XX....XXXXXX....X..X.XX.XXX............. 15 LAN_BASEADR<4> XX....XXXXXX...X..X..XX.XXX............. 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 27/27 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB8_1 (b) (b) (unused) 0 0 /\4 1 FB8_2 91 I/O I (unused) 0 0 0 5 FB8_3 95 I/O I (unused) 0 0 0 5 FB8_4 97 I/O I (unused) 0 0 0 5 FB8_5 92 I/O I (unused) 0 0 0 5 FB8_6 93 I/O (unused) 0 0 0 5 FB8_7 (b) (unused) 0 0 0 5 FB8_8 94 I/O I (unused) 0 0 0 5 FB8_9 96 I/O (unused) 0 0 0 5 FB8_10 101 I/O (unused) 0 0 0 5 FB8_11 98 I/O I (unused) 0 0 0 5 FB8_12 100 I/O lan/lan_CLKF 2 0 0 3 FB8_13 103 I/O I ide/ide_CLKF 2 0 0 3 FB8_14 102 I/O I autoconfig 5 0 0 0 FB8_15 104 I/O I OWN 1 0 \/1 3 FB8_16 107 I/O O CFOUT 1 1<- \/5 0 FB8_17 105 I/O O ide 19 14<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: AUTO_CONFIG_DONE<0> 10: A<22> 19: IDE_BASEADR<4> 2: AUTO_CONFIG_DONE<1> 11: A<23> 20: IDE_BASEADR<5> 3: AUTO_CONFIG_DONE<2> 12: C1 21: IDE_BASEADR<6> 4: A<16> 13: C3 22: IDE_BASEADR<7> 5: A<17> 14: CFIN 23: SHUT_UP<2> 6: A<18> 15: IDE_BASEADR<0> 24: SLAVE_OBUF__$INT 7: A<19> 16: IDE_BASEADR<1> 25: autoconfig/autoconfig_CLKF 8: A<20> 17: IDE_BASEADR<2> 26: ide/ide_CLKF 9: A<21> 18: IDE_BASEADR<3> 27: lan/lan_RSTF__$INT Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs lan/lan_CLKF ...........XX........................... 2 ide/ide_CLKF ...........XX........................... 2 autoconfig XXXXXXXXXXX..X..........X.X............. 14 OWN .......................X................ 1 CFOUT XXX..................................... 3 ide ...XXXXXXXX...XXXXXXXXX..XX............. 19 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$$OpTx$FX_DC$84_INV$97 <= (NOT autoconfig AND NOT lan); FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0'); FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0'); FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0'); FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0)) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT UDS)); FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1)) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT UDS)); FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2)) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT UDS)); A_LAN(0) <= A(1); A_LAN(1) <= A(2); A_LAN(2) <= A(3); A_LAN(3) <= A(4); A_LAN(4) <= A(5); A_LAN(5) <= A(6); A_LAN(6) <= A(7); A_LAN(7) <= A(8); A_LAN(8) <= A(9); A_LAN(9) <= A(10); A_LAN(10) <= A(11); A_LAN(11) <= A(12); A_LAN(12) <= A(13); A_LAN(13) <= A(14); CFOUT <= NOT ((AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1))); CP_CS <= '0'; CP_RD <= '1'; CP_WE <= '1'; D_I(0) <= NOT ((NOT AS AND RW AND NOT DQ(0).PIN AND lan)); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(1) <= NOT ((NOT AS AND RW AND NOT DQ(1).PIN AND lan)); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(2) <= NOT ((NOT AS AND RW AND NOT DQ(2).PIN AND lan)); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(3) <= NOT ((NOT AS AND RW AND NOT DQ(3).PIN AND lan)); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(4) <= NOT ((NOT AS AND RW AND NOT DQ(4).PIN AND lan)); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(5) <= NOT ((NOT AS AND RW AND NOT DQ(5).PIN AND lan)); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(6) <= NOT ((NOT AS AND RW AND NOT DQ(6).PIN AND lan)); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(7) <= NOT ((NOT AS AND RW AND NOT DQ(7).PIN AND lan)); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(8) <= NOT ((NOT AS AND RW AND NOT DQ(8).PIN AND lan)); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(9) <= NOT ((NOT AS AND RW AND NOT DQ(9).PIN AND lan)); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(10) <= NOT ((NOT AS AND RW AND NOT DQ(10).PIN AND lan)); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(11) <= NOT ((NOT AS AND RW AND NOT DQ(11).PIN AND lan)); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(12) <= ((AS AND Dout1(0)) OR (NOT RW AND Dout1(0)) OR (Dout1(0) AND NOT lan) OR (NOT AS AND RW AND lan AND DQ(12).PIN)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(13) <= ((NOT RW AND Dout1(1)) OR (NOT lan AND Dout1(1)) OR (NOT AS AND RW AND lan AND DQ(13).PIN) OR (AS AND Dout1(1))); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(14) <= ((AS AND Dout1(2)) OR (NOT RW AND Dout1(2)) OR (Dout1(2) AND NOT lan) OR (NOT AS AND RW AND lan AND DQ(14).PIN)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); D_I(15) <= ((AS AND Dout1(3)) OR (NOT RW AND Dout1(3)) OR (Dout1(3) AND NOT lan) OR (NOT AS AND RW AND lan AND DQ(15).PIN)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= (NOT AS AND RW AND NOT $OpTx$$OpTx$FX_DC$84_INV$97); DQ_I(0) <= D(0).PIN; DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z'; DQ_OE(0) <= (NOT AS AND NOT RW); DQ_I(1) <= D(1).PIN; DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z'; DQ_OE(1) <= (NOT AS AND NOT RW); DQ_I(2) <= D(2).PIN; DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z'; DQ_OE(2) <= (NOT AS AND NOT RW); DQ_I(3) <= D(3).PIN; DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z'; DQ_OE(3) <= (NOT AS AND NOT RW); DQ_I(4) <= D(4).PIN; DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z'; DQ_OE(4) <= (NOT AS AND NOT RW); DQ_I(5) <= D(5).PIN; DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z'; DQ_OE(5) <= (NOT AS AND NOT RW); DQ_I(6) <= D(6).PIN; DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z'; DQ_OE(6) <= (NOT AS AND NOT RW); DQ_I(7) <= D(7).PIN; DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z'; DQ_OE(7) <= (NOT AS AND NOT RW); DQ_I(8) <= D(8).PIN; DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z'; DQ_OE(8) <= (NOT AS AND NOT RW); DQ_I(9) <= D(9).PIN; DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z'; DQ_OE(9) <= (NOT AS AND NOT RW); DQ_I(10) <= D(10).PIN; DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z'; DQ_OE(10) <= (NOT AS AND NOT RW); DQ_I(11) <= D(11).PIN; DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z'; DQ_OE(11) <= (NOT AS AND NOT RW); DQ_I(12) <= D(12).PIN; DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z'; DQ_OE(12) <= (NOT AS AND NOT RW); DQ_I(13) <= D(13).PIN; DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z'; DQ_OE(13) <= (NOT AS AND NOT RW); DQ_I(14) <= D(14).PIN; DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z'; DQ_OE(14) <= (NOT AS AND NOT RW); DQ_I(15) <= D(15).PIN; DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z'; DQ_OE(15) <= (NOT AS AND NOT RW); DTACK_I <= '0'; DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; DTACK_OE <= '0'; FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); Dout1_D(0) <= ((D_13_IOBUFE.EXP) OR (AS AND RESET AND NOT Dout1(0)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND A(2) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND A(2) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (NOT RW AND RESET AND NOT Dout1(0)) OR (RESET AND NOT Dout1(0) AND NOT autoconfig) OR (NOT AS AND RW AND RESET AND A(6) AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND A(2) AND NOT A(4) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND NOT A(4) AND A(5) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND NOT Dout1(0) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(0) AND A(2) AND NOT A(5) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(0) AND A(2) AND NOT A(4) AND A(5) AND A(1)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND autoconfig AND A(2) AND NOT A(4) AND A(5) AND A(1))); FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); Dout1_D(1) <= ((RESET AND NOT autoconfig AND NOT Dout1(1)) OR (NOT AS AND RW AND RESET AND A(6) AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND A(4) AND NOT A(5) AND A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(4) AND NOT A(5) AND NOT A(1) AND A(3)) OR (NOT AS AND RW AND RESET AND NOT AUTO_CONFIG_DONE(2) AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (ROM_OE_S.EXP) OR (AS AND RESET AND NOT Dout1(1)) OR (NOT RW AND RESET AND NOT Dout1(1)) OR (RESET AND NOT Dout1(1) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(2) AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND NOT A(2) AND NOT A(5) AND A(1) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(1) AND A(2) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND autoconfig AND NOT A(2) AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND NOT A(4) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(1) AND A(2) AND NOT A(4) AND A(5) AND A(1) AND A(3))); FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); Dout1_D(2) <= ((AS AND RESET AND NOT Dout1(2)) OR (NOT RW AND RESET AND NOT Dout1(2)) OR (RESET AND NOT Dout1(2) AND NOT autoconfig) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND autoconfig AND A(2) AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND NOT A(3)) OR (D_2_IOBUFE.EXP) OR (NOT AS AND RW AND RESET AND A(6) AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND A(4) AND NOT A(5) AND NOT A(1) AND A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND NOT A(4) AND A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND A(2) AND A(4) AND NOT A(5) AND A(1) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(2) AND A(2) AND NOT A(5) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(2) AND A(2) AND NOT A(4) AND A(5) AND A(1)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND A(2) AND NOT A(5) AND A(1) AND NOT A(3))); FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); Dout1_D(3) <= ((NOT AS AND RW AND RESET AND A(6) AND autoconfig AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND NOT A(2) AND NOT A(5) AND A(1) AND NOT A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(3) AND A(2) AND NOT A(5) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig AND A(4) AND NOT A(5) AND A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND A(4) AND NOT A(5) AND A(1) AND A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND A(2) AND NOT A(4) AND A(5) AND NOT A(1) AND NOT A(3)) OR (NOT AS AND RW AND RESET AND NOT A(6) AND autoconfig AND NOT A(2) AND A(4) AND NOT A(5) AND NOT A(1) AND A(3)) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(3) AND A(2) AND NOT A(4) AND A(5) AND A(1) AND A(3)) OR (AS AND RESET AND NOT Dout1(3)) OR (NOT RW AND RESET AND NOT Dout1(3)) OR (RESET AND NOT Dout1(3) AND NOT autoconfig) OR (RESET AND NOT A(6) AND AUTO_CONFIG_DONE(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND NOT Dout1(3) AND NOT A(4) AND NOT A(5) AND NOT A(3))); IDE_A(0) <= A(9); IDE_A(1) <= A(10); IDE_A(2) <= A(11); FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(0) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(8).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(0) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(8).PIN AND NOT UDS)); FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(1) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(9).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(1) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(9).PIN AND NOT UDS)); FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(2) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(10).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(2) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(10).PIN AND NOT UDS)); FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(3) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(11).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(3) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(11).PIN AND NOT UDS)); FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(4) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(12).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(4) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(12).PIN AND NOT UDS)); FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(5) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(13).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(5) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(13).PIN AND NOT UDS)); FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(6) <= ((NOT RESET AND NOT IDE_BASEADR(6)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(6) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(14).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(6) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(14).PIN AND NOT UDS)); FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_BASEADR_T(7) <= ((NOT RESET AND NOT IDE_BASEADR(7)) OR (NOT AS AND NOT RW AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND NOT IDE_BASEADR(7) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(15).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND AUTO_CONFIG_DONE(1) AND autoconfig AND IDE_BASEADR(7) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(15).PIN AND NOT UDS)); IDE_CS(0) <= NOT A(12); IDE_CS(1) <= NOT A(13); FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE) OR (NOT AS AND NOT RW AND RESET AND ide)); FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_R_D <= (NOT AS AND RW AND RESET AND ide AND NOT IDE_ENABLE); FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); IDE_W_D <= (NOT AS AND NOT RW AND RESET AND ide); INT_OUT_I <= '0'; INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z'; INT_OUT_OE <= NOT CP_IRQ; FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(0) <= ((NOT RESET AND NOT LAN_BASEADR(0)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(0) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(8).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(0) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(8).PIN AND NOT UDS)); FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(1) <= ((NOT RESET AND NOT LAN_BASEADR(1)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(1) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(9).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(1) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(9).PIN AND NOT UDS)); FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(2) <= ((NOT RESET AND NOT LAN_BASEADR(2)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(2) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(10).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(2) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(10).PIN AND NOT UDS)); FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(3) <= ((NOT RESET AND NOT LAN_BASEADR(3)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(3) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(11).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(3) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(11).PIN AND NOT UDS)); FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(4) <= ((NOT RESET AND NOT LAN_BASEADR(4)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(4) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(12).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(4) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(12).PIN AND NOT UDS)); FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(5) <= ((NOT RESET AND NOT LAN_BASEADR(5)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(5) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(13).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(5) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(13).PIN AND NOT UDS)); FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(6) <= ((NOT RESET AND NOT LAN_BASEADR(6)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(6) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(14).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(6) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(14).PIN AND NOT UDS)); FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0'); LAN_BASEADR_T(7) <= ((NOT RESET AND NOT LAN_BASEADR(7)) OR (NOT AS AND NOT RW AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND NOT LAN_BASEADR(7) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND D(15).PIN AND NOT UDS) OR (NOT AS AND NOT RW AND RESET AND A(6) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND LAN_BASEADR(7) AND NOT A(2) AND NOT A(4) AND NOT A(5) AND NOT A(1) AND A(3) AND NOT D(15).PIN AND NOT UDS)); LAN_CFG(1) <= '0'; LAN_CFG(2) <= '1'; LAN_CFG(3) <= '0'; LAN_CFG(4) <= '0'; LAN_CS <= '1'; LAN_RD <= (NOT AS AND RW AND lan); LAN_WRH <= (NOT AS AND NOT RW AND lan AND NOT UDS); LAN_WRL <= (NOT AS AND NOT RW AND lan AND NOT LDS); OWN_I <= '0'; OWN <= OWN_I when OWN_OE = '1' else 'Z'; OWN_OE <= NOT SLAVE_OBUF__$INT; ROM_B(0) <= '0';