12 Commits

Include renames

Author	SHA1	Message	Date
MHeinrichs	a7e6f9a3a3	Cleaned up firmware	2017-12-22 11:32:26 +01:00
MHeinrichs	8e2723cc99	CP timing fixed and Bytemirror for CP	2017-01-27 23:47:04 +01:00
MHeinrichs	c5e1b0debd	OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...	2017-01-26 22:24:01 +01:00
MHeinrichs	9d64477682	Reset in hardware and clock set to 33mhz	2017-01-26 22:03:20 +01:00
MHeinrichs	69ed2e6ebd	Fixed an error in the debug-output and switched to "faulty xilinx"-pinout	2017-01-18 23:21:45 +01:00
MHeinrichs	a1b4c891be	fixcing the init-routines!	2017-01-18 07:16:05 +01:00
MHeinrichs	55f79f1b26	Testbench added	2017-01-16 00:47:11 +01:00
MHeinrichs	0a5cadccdc	Still no success	2017-01-15 00:14:51 +01:00
MHeinrichs	f7b79faf13	AC very smart&slim but its not working! WHY????	2017-01-07 23:34:34 +01:00
MHeinrichs	53aacaf617	to much logic!	2016-12-28 20:57:10 +01:00
MHeinrichs	4a0794d0f9	Starting the init routiune	2016-12-28 01:32:54 +01:00
MHeinrichs	1440afbeeb	Structure ready	2016-12-14 21:36:52 +01:00