Commit Graph
43 Commits
Author SHA1 Message Date
MHeinrichs 01f5ae13ff New compile with 25MHz 2018-12-19 22:28:14 +01:00
MHeinrichs 00f475fed5 No swap of upper/lower word 2018-12-19 19:01:29 +01:00
MHeinrichs d0da391575 Cacheinhibit must be asserted! 2018-12-19 18:49:12 +01:00
MHeinrichs 20aff1a84f Busspeed tweaked: 6-7MB/s Zorro3-Speed 2018-12-18 22:57:37 +01:00
MHeinrichs a28f930027 Set driver init to 25MHz 2018-12-18 22:30:20 +01:00
MHeinrichs 1f390a5b9e Swapping enabled but freeze lock during driver 2018-12-18 12:13:12 +01:00
MHeinrichs 118d024b37 AC working and swapping disabled
use fit.bat 54 35
2018-12-18 11:59:02 +01:00
MHeinrichs 11a6adca8a Byteswap working 2018-12-18 00:00:58 +01:00
MHeinrichs 8cbd5c7cef Datata access works for fixed base address 2018-12-17 23:56:57 +01:00
MHeinrichs deb69da927 sm cleaned up 2018-12-17 23:03:12 +01:00
MHeinrichs 73899442dc z3 ac is working 2018-12-14 01:28:28 +01:00
MHeinrichs eec9e31a7a Auto stash before merge of "master" and "origin/driverupdate" 2018-11-26 20:34:01 +01:00
MHeinrichs 95bc477444 Switched Driver to baxnet-structure 2018-06-09 21:41:07 +02:00
MHeinrichs b714ded89e Working on Rev2 2018-06-09 12:47:10 +02:00
MHeinrichs 16f86601d9 Tweaked the driver a bit 2018-02-09 00:41:02 +01:00
MHeinrichs 0646520752 A12/13 fix Driver improvement git-ignore cleaned 2018-02-03 17:38:48 +01:00
MHeinrichs f848e6be7a Fixed Autoconfig-Bug, improved interrupthandling multiple package support 2018-02-01 02:17:20 +01:00
MHeinrichs 70f403c28e Added IDE-Disable option 2018-01-24 21:58:18 +01:00
MHeinrichs 8dfb0353a3 first hit for public 2018-01-21 23:56:13 +01:00
MHeinrichs cb1743d4a2 Byteswap disabled 2017-12-26 10:25:31 +01:00
MHeinrichs eea643c563 LAN-INT-Disable implemented 2017-12-22 11:32:26 +01:00
MHeinrichs a7e6f9a3a3 Cleaned up firmware 2017-12-22 11:32:26 +01:00
MHeinrichs 4e0dfd7654 Address-Swap for A13/12 and Byteswap from $6000-$7FFF 2017-12-21 21:46:51 +01:00
MHeinrichs 8e2723cc99 CP timing fixed and Bytemirror for CP 2017-01-27 23:47:04 +01:00
MHeinrichs c5e1b0debd OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1... 2017-01-26 22:24:01 +01:00
MHeinrichs 9d64477682 Reset in hardware and clock set to 33mhz 2017-01-26 22:03:20 +01:00
MHeinrichs 69ed2e6ebd Fixed an error in the debug-output and switched to "faulty xilinx"-pinout 2017-01-18 23:21:45 +01:00
MHeinrichs cca52926f8 InitLan works and macros put in the ENCX24J-Lib 2017-01-18 22:19:57 +01:00
MHeinrichs a1b4c891be fixcing the init-routines! 2017-01-18 07:16:05 +01:00
MHeinrichs 55f79f1b26 Testbench added 2017-01-16 00:47:11 +01:00
MHeinrichs 0a5cadccdc Still no success 2017-01-15 00:14:51 +01:00
MHeinrichs f7b79faf13 AC very smart&slim but its not working! WHY???? 2017-01-07 23:34:34 +01:00
MHeinrichs cd4fb86c55 Where is the bug? 2017-01-07 22:38:11 +01:00
MHeinrichs 3eb6ab740e ac working 2016-12-29 15:05:50 +01:00
MHeinrichs 357202a1d5 Got it?!? 2016-12-29 00:01:23 +01:00
MHeinrichs 172fc9a0fd new style of autoconfig 2016-12-28 23:47:02 +01:00
MHeinrichs 53aacaf617 to much logic! 2016-12-28 20:57:10 +01:00
MHeinrichs 4a0794d0f9 Starting the init routiune 2016-12-28 01:32:54 +01:00
MHeinrichs e2e8077217 Now the interface mmust be initialized and tested 2016-12-15 22:39:10 +01:00
MHeinrichs aa3747f820 compiled 2016-12-15 22:06:32 +01:00
MHeinrichs e30f1e9583 Autocnfig working 2016-12-15 22:05:42 +01:00
MHeinrichs 508d7a7e5c IDE & Autoconfig working 2016-12-15 20:59:46 +01:00
MHeinrichs 1440afbeeb Structure ready 2016-12-14 21:36:52 +01:00