AC very smart&slim but its not working! WHY????

This commit is contained in:
MHeinrichs
2017-01-07 23:34:34 +01:00
parent cd4fb86c55
commit f7b79faf13
201 changed files with 17617 additions and 32685 deletions
+3 -7
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Jan 07 22:34:21 2017">
<application name="pn" timeStamp="Sat Jan 07 23:30:55 2017">
<section name="Project Information" visible="false">
<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -12,19 +12,16 @@ This means code written to parse this file will need to be revisited each subseq
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthOpt" value="Area" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Xilinx/14.6/ISE_DS/ISE/data/default.xds" type="process"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2016-12-13T21:04:49" type="design"/>
<property name="PROP_intWbtProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
@@ -33,8 +30,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
<property name="PROP_FitterOptimization" value="Density" type="process"/>
<property name="PROP_xcpldFitDesPtermLmt_xc9500" value="10" type="process"/>
<property name="PROP_xcpldFitDesPtermLmt_xc9500" value="35" type="process"/>
<property name="PROP_xstSafeImplement" value="Yes" type="process"/>
<property name="PROP_DevDevice" value="xc95288xl" type="design"/>
<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>