AC very smart&slim but its not working! WHY????

This commit is contained in:
MHeinrichs
2017-01-07 23:34:34 +01:00
parent cd4fb86c55
commit f7b79faf13
201 changed files with 17617 additions and 32685 deletions
+38 -35
View File
@@ -55,7 +55,7 @@ XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Area
Optimization Goal : Speed
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
@@ -76,19 +76,21 @@ wysiwyg : NO
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
Entity <LAN_IDE_CP> compiled.
Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 131: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AS>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -104,15 +106,11 @@ WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and lef
WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <MTACK> is never assigned.
WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <A<15>> is never assigned.
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <LAN_INT_ENABLE> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 16-bit tristate buffer for signal <D>.
Found 16-bit tristate buffer for signal <DQ>.
Found 1-bit tristate buffer for signal <OWN>.
@@ -123,7 +121,7 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 120.
Found 2-bit register for signal <AUTO_CONFIG_DONE>.
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 254.
Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 251.
Found 1-bit register for signal <autoconfig>.
Found 2-bit comparator less for signal <autoconfig$cmp_lt0000> created at line 133.
Found 1-bit register for signal <cp>.
@@ -132,7 +130,8 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <Dout1>.
Found 2-bit comparator less for signal <Dout1$cmp_lt0000> created at line 256.
Found 2-bit comparator less for signal <Dout1$cmp_lt0000> created at line 253.
Found 1-bit register for signal <DS_D>.
Found 1-bit register for signal <ide>.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 152.
Found 8-bit register for signal <IDE_BASEADR>.
@@ -142,19 +141,21 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 1-bit register for signal <lan>.
Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 140.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
Found 1-bit register for signal <ROM_OE_S>.
Found 3-bit register for signal <SHUT_UP>.
Summary:
inferred 4 D-type flip-flop(s).
inferred 6 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 5 Comparator(s).
inferred 1 Xor(s).
inferred 40 Tristate(s).
Unit <LAN_IDE_CP> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
@@ -162,8 +163,8 @@ HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
2-bit adder : 1
# Registers : 22
1-bit register : 16
# Registers : 24
1-bit register : 18
2-bit register : 2
4-bit register : 1
8-bit register : 3
@@ -189,8 +190,8 @@ Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
2-bit adder : 1
# Registers : 4
Flip-Flops : 4
# Registers : 6
Flip-Flops : 6
# Comparators : 3
8-bit comparator equal : 3
@@ -220,7 +221,7 @@ Final Results
RTL Top Level Output File Name : LAN_IDE_CP.ngr
Top Level Output File Name : LAN_IDE_CP
Output Format : NGC
Optimization Goal : Area
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
@@ -232,37 +233,39 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 408
# AND2 : 90
# AND3 : 32
# AND4 : 1
# BELS : 457
# AND2 : 106
# AND3 : 15
# AND4 : 9
# AND5 : 1
# AND8 : 3
# GND : 1
# INV : 169
# OR2 : 82
# OR3 : 4
# OR4 : 2
# INV : 197
# OR2 : 87
# OR3 : 7
# OR4 : 4
# VCC : 1
# XOR2 : 26
# FlipFlops/Latches : 48
# FD : 8
# FlipFlops/Latches : 50
# FD : 9
# FDC : 4
# FDCE : 36
# IO Buffers : 107
# IBUF : 34
# FDCE : 37
# IO Buffers : 109
# IBUF : 36
# IOBUFE : 32
# OBUF : 33
# OBUFE : 8
=========================================================================
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.35 secs
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.25 secs
-->
Total memory usage is 290084 kilobytes
Total memory usage is 290008 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 13 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Number of warnings : 10 ( 0 filtered)
Number of infos : 1 ( 0 filtered)