AC very smart&slim but its not working! WHY????
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@@ -55,7 +55,7 @@ XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Area
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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@@ -76,19 +76,21 @@ wysiwyg : NO
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
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Entity <lan_ide_cp> compiled.
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Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
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Entity <LAN_IDE_CP> compiled.
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Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
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Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
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WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 131: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<AS>
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Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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@@ -104,15 +106,11 @@ WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and lef
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WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1306 - Output <MTACK> is never assigned.
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WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:2565 - Inout <A<15>> is never assigned.
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WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <LAN_INT_ENABLE> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 16-bit tristate buffer for signal <D>.
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Found 16-bit tristate buffer for signal <DQ>.
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Found 1-bit tristate buffer for signal <OWN>.
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@@ -123,7 +121,7 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 120.
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Found 2-bit register for signal <AUTO_CONFIG_DONE>.
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Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 254.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 251.
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Found 1-bit register for signal <autoconfig>.
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Found 2-bit comparator less for signal <autoconfig$cmp_lt0000> created at line 133.
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Found 1-bit register for signal <cp>.
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@@ -132,7 +130,8 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <Dout1>.
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Found 2-bit comparator less for signal <Dout1$cmp_lt0000> created at line 256.
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Found 2-bit comparator less for signal <Dout1$cmp_lt0000> created at line 253.
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Found 1-bit register for signal <DS_D>.
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Found 1-bit register for signal <ide>.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 152.
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Found 8-bit register for signal <IDE_BASEADR>.
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@@ -142,19 +141,21 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
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Found 1-bit register for signal <lan>.
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Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 140.
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Found 8-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 3-bit register for signal <SHUT_UP>.
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Summary:
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inferred 4 D-type flip-flop(s).
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inferred 6 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 5 Comparator(s).
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inferred 1 Xor(s).
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inferred 40 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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=========================================================================
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HDL Synthesis Report
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@@ -162,8 +163,8 @@ HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 22
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1-bit register : 16
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# Registers : 24
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1-bit register : 18
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2-bit register : 2
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4-bit register : 1
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8-bit register : 3
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@@ -189,8 +190,8 @@ Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 4
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Flip-Flops : 4
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# Registers : 6
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Flip-Flops : 6
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# Comparators : 3
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8-bit comparator equal : 3
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@@ -220,7 +221,7 @@ Final Results
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RTL Top Level Output File Name : LAN_IDE_CP.ngr
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Top Level Output File Name : LAN_IDE_CP
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Output Format : NGC
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Optimization Goal : Area
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Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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@@ -232,37 +233,39 @@ Design Statistics
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# IOs : 116
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Cell Usage :
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# BELS : 408
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# AND2 : 90
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# AND3 : 32
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# AND4 : 1
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# BELS : 457
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# AND2 : 106
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# AND3 : 15
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# AND4 : 9
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# AND5 : 1
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# AND8 : 3
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# GND : 1
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# INV : 169
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# OR2 : 82
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# OR3 : 4
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# OR4 : 2
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# INV : 197
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# OR2 : 87
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# OR3 : 7
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# OR4 : 4
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# VCC : 1
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# XOR2 : 26
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# FlipFlops/Latches : 48
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# FD : 8
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# FlipFlops/Latches : 50
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# FD : 9
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# FDC : 4
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# FDCE : 36
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# IO Buffers : 107
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# IBUF : 34
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# FDCE : 37
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# IO Buffers : 109
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# IBUF : 36
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# IOBUFE : 32
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# OBUF : 33
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# OBUFE : 8
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=========================================================================
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Total REAL time to Xst completion: 8.00 secs
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Total CPU time to Xst completion: 8.35 secs
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Total REAL time to Xst completion: 9.00 secs
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Total CPU time to Xst completion: 8.25 secs
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-->
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Total memory usage is 290084 kilobytes
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Total memory usage is 290008 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 13 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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Number of warnings : 10 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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