Merge branch 'v2updates' into 'master'
import new driver into master branch See merge request MHeinrichs/Zorro-LAN-IDE!2
This commit is contained in:
Matthias Heinrichs
@@ -44,6 +44,8 @@ PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/
|
|||||||
note: this switch should not be enabled in normal cases.
|
note: this switch should not be enabled in normal cases.
|
||||||
The module features autoconfiguration that determines
|
The module features autoconfiguration that determines
|
||||||
speed and duplex automatically.
|
speed and duplex automatically.
|
||||||
|
note(2): see miitool for changing speed/duplex
|
||||||
|
settings at runtime.
|
||||||
|
|
||||||
PRIORITY - server task priority (default 1)
|
PRIORITY - server task priority (default 1)
|
||||||
|
|
||||||
@@ -51,8 +53,8 @@ PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/
|
|||||||
|
|
||||||
MTU - maximum transmission unit (default 1500)
|
MTU - maximum transmission unit (default 1500)
|
||||||
|
|
||||||
MULTICAST - obsolete, kept for config file backwards compatibility with
|
MULTICAST - (V2.3+) override fine-grained automatic multicast filtering
|
||||||
old driver
|
and accept all multicast frames (default: off)
|
||||||
|
|
||||||
FLOWCONTROL - enable automatic flow control that throttles incoming
|
FLOWCONTROL - enable automatic flow control that throttles incoming
|
||||||
data when the hardware buffer gets full
|
data when the hardware buffer gets full
|
||||||
@@ -64,6 +66,20 @@ PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/
|
|||||||
Changelog:
|
Changelog:
|
||||||
----------
|
----------
|
||||||
|
|
||||||
|
2.3 - implemented fine grained multicast filter hashes
|
||||||
|
|
||||||
|
2.2 - some more tuning to RX/TX scheduling
|
||||||
|
- added optional debug code to lowlevel routines
|
||||||
|
- removed some obsolete bus transfers
|
||||||
|
- uses DMACopyFromBuffer for IP-stacks supporting
|
||||||
|
this capability
|
||||||
|
- explicit 32 bit alignment for RX/TX to speed up
|
||||||
|
ZIII transfers
|
||||||
|
- added experimental support for MII interface to
|
||||||
|
poll and modify speed and duplex settings on the
|
||||||
|
fly
|
||||||
|
- miitool added (see README.miitool)
|
||||||
|
|
||||||
2.00 - improved RX speed for buffer wraparound cases
|
2.00 - improved RX speed for buffer wraparound cases
|
||||||
- some more safety checks for boards with unresponsive
|
- some more safety checks for boards with unresponsive
|
||||||
ENC chips (explicit card bus clear before verification of
|
ENC chips (explicit card bus clear before verification of
|
||||||
@@ -98,11 +114,12 @@ Changelog:
|
|||||||
Compilation / Development Notes
|
Compilation / Development Notes
|
||||||
-------------------------------
|
-------------------------------
|
||||||
|
|
||||||
Either VBCC or GCC (tested with version 2.95 only) can be used. General
|
Either VBCC or GCC (tested with version 2.95 only) can be used for
|
||||||
options for compiler usage can be found in Common.mk. Also, you might want
|
cross-compiles. General options for compiler usage can be found in
|
||||||
to adapt the paths to your setup (PREFX,SYSINC). In addition to the regular
|
Common.mk. Also, you might want to adapt the paths to your setup
|
||||||
NDK, the sana2.h is expected in the devices/ subdir of the includes. sana2.h
|
(PREFX,SYSINC). In addition to the regular NDK, the sana2.h is expected
|
||||||
may be found in the AmiTCP or Roadshow SDK, respectively.
|
in the devices/ subdir of the includes. sana2.h may be found in the
|
||||||
|
AmiTCP or Roadshow SDK, respectively.
|
||||||
|
|
||||||
Call
|
Call
|
||||||
|
|
||||||
@@ -113,6 +130,15 @@ for building the device.
|
|||||||
VBCC note: When calling the GNU Make port supplied with ADE/GG natively on AmigaOS3,
|
VBCC note: When calling the GNU Make port supplied with ADE/GG natively on AmigaOS3,
|
||||||
please make sure that "vc" is within the search path of "/bin/sh".
|
please make sure that "vc" is within the search path of "/bin/sh".
|
||||||
|
|
||||||
|
Native compilation is also supported for GCC and VBCC. In addition, SAS/C
|
||||||
|
smakefiles are provided for the hardware targets.
|
||||||
|
|
||||||
|
Call
|
||||||
|
|
||||||
|
smake -f smakefile.enc
|
||||||
|
|
||||||
|
for native building with SAS/C.
|
||||||
|
|
||||||
Conceptually, the driver was meant to support multiple hardware targets. Therefore,
|
Conceptually, the driver was meant to support multiple hardware targets. Therefore,
|
||||||
it features a SANA-II frontend (device.c,deviceheader.c,deviceinit.c), a main
|
it features a SANA-II frontend (device.c,deviceheader.c,deviceinit.c), a main
|
||||||
server running in a task (server.c) and several hardware backends. A new hardware
|
server running in a task (server.c) and several hardware backends. A new hardware
|
||||||
|
|||||||
@@ -18,7 +18,11 @@ combination. Please note that fixed parameters must be set at both
|
|||||||
ends of the link. Otherwise the link will work slowly or not at all.
|
ends of the link. Otherwise the link will work slowly or not at all.
|
||||||
|
|
||||||
None of the settings this tool applies is permanent. Changed parameters
|
None of the settings this tool applies is permanent. Changed parameters
|
||||||
are only valid until a reboot of the NIC.
|
are only valid until the next reset of the NIC.
|
||||||
|
|
||||||
|
This utility is able to detect an active Ethernet interface in case that
|
||||||
|
the RoadShow TCP/IP stack is active. Otherwise, the device needs to be
|
||||||
|
passed as commandline option explicitly.
|
||||||
|
|
||||||
Examples for usage are given at the end of this text.
|
Examples for usage are given at the end of this text.
|
||||||
|
|
||||||
@@ -80,6 +84,9 @@ Valid Speed/Duplex combinations (not case sensitive):
|
|||||||
|
|
||||||
Examples:
|
Examples:
|
||||||
|
|
||||||
|
current status (detailed, autodetect)
|
||||||
|
miitool v
|
||||||
|
|
||||||
current status (detailed):
|
current status (detailed):
|
||||||
miitool DEV=enc624j6net.device v
|
miitool DEV=enc624j6net.device v
|
||||||
|
|
||||||
|
|||||||
@@ -1,102 +0,0 @@
|
|||||||
VWiznet - A SANA-II driver for W5500 10/100 ethernet modules
|
|
||||||
|
|
||||||
Copyright (C) 2018-2019 Henryk Richter <henryk.richter@gmx.net>
|
|
||||||
|
|
||||||
This driver is supposed to support W5500 modules hooked up to the expansion
|
|
||||||
port of Vampire 500V2+ cards.
|
|
||||||
|
|
||||||
|
|
||||||
Installation:
|
|
||||||
-------------
|
|
||||||
|
|
||||||
Installation of the driver is straightforward.
|
|
||||||
Just copy vwiznet500ex.device from the bin subdirectory to devs:networks
|
|
||||||
and enable the interface in your favorite TCP/IP stack as usual. So far,
|
|
||||||
successful tests have been done with the free AmiTCP/IP 3.0b2, AmiTCP4.0-4.2,
|
|
||||||
Genesis, MiamiDX and RoadShow.
|
|
||||||
|
|
||||||
The minimum system requirement is the Gold 2.10 release of Apollo Core
|
|
||||||
for Vampire 500V2+.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Vampire500 Expansion port Hardware
|
|
||||||
-----------------------------------
|
|
||||||
|
|
||||||
Please see http://wiki.apollo-accelerators.com/doku.php/expansionport for
|
|
||||||
guidance on pinout of the expansion port.
|
|
||||||
|
|
||||||
The W5500 can be clocked way higher than the ENC28J60 that was used for
|
|
||||||
SDNet. As a consequence of clocks beyond 25 MHz, signal integrity is of
|
|
||||||
some concern. Therefore it is suggested to connect the module is as close
|
|
||||||
as possible to the expansion port and use an Ethernet expansion cable
|
|
||||||
in order to reach the edge of the computer case.
|
|
||||||
|
|
||||||
An adapter PCB is in the making. That PCB plugs directly into the Vampire
|
|
||||||
expansion port, connects readily available W5500 modules on the other
|
|
||||||
side and contains some components to keep signal integrity in a good shape.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Options
|
|
||||||
-------
|
|
||||||
|
|
||||||
Below you find the options accepted by the driver. Please note that no special
|
|
||||||
configuration is necessary for normal operation. What you find documented below
|
|
||||||
is available for tuning purposes.
|
|
||||||
|
|
||||||
The options template for the config files
|
|
||||||
ENVARC:SANA2/vwiznet500ex.config
|
|
||||||
|
|
||||||
is as follows:
|
|
||||||
|
|
||||||
PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,SPISPEED/K/N,TIMER/K/N,NOINTERRUPT/S
|
|
||||||
|
|
||||||
SPISPEED - SPI clock divider (1-10, default 1), controls maximum
|
|
||||||
clock of SPI bus. Actual I/O clock is Core_Clock/(3+SPISPEED).
|
|
||||||
|
|
||||||
PRIORITY - server task priority (default 1)
|
|
||||||
|
|
||||||
BPS - bit per seconds for statistics purposes
|
|
||||||
|
|
||||||
MTU - maximum transmission unit (default 1500)
|
|
||||||
|
|
||||||
NOINTERRUPT - disable hardware interrupt and use polling instead
|
|
||||||
(default: interrupt enabled)
|
|
||||||
|
|
||||||
TIMER - when disabling interrupt you also need to specify
|
|
||||||
a timer interval in microseconds
|
|
||||||
(default: 0, i.e. no timer)
|
|
||||||
|
|
||||||
|
|
||||||
example1 (useful for DSL via PPPoE,
|
|
||||||
higher priority for server task = more speed with AmiTCP
|
|
||||||
at the expense of multitasking friendliness):
|
|
||||||
echo "MTU=1492 SPISPEED=1 PRIORITY=6" >ENVARC:sana2/vwiznet500ex.config
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Changelog:
|
|
||||||
----------
|
|
||||||
|
|
||||||
1.99 - re-enabled 32 Bit Buffer copies (unless Miami is active)
|
|
||||||
- default server task priority for AmiTCP=6 (otherwise 0)
|
|
||||||
- tuned RX/TX balancing to make RoadShow happy
|
|
||||||
- added Packet Filter hook processing (needs testing)
|
|
||||||
|
|
||||||
1.98 - preparations for V2 of the adapter PCB: hardware based reset
|
|
||||||
|
|
||||||
1.97 - added New style device commands
|
|
||||||
- implemented SANA-II Device Query Extension
|
|
||||||
|
|
||||||
1.96 - tuned defaults
|
|
||||||
|
|
||||||
1.95 - initial build, aligned with sdnet/v2expeth version
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyrights / License:
|
|
||||||
---------------------
|
|
||||||
|
|
||||||
Copyright (C) 2018-2019 Henryk Richter <henryk.richter@gmx.net>, all rights reserved.
|
|
||||||
|
|
||||||
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@@ -21,15 +21,15 @@
|
|||||||
# debug = 1 will include string debugging for terminal/sushi/sashimi
|
# debug = 1 will include string debugging for terminal/sushi/sashimi
|
||||||
debug = 0
|
debug = 0
|
||||||
# compiler_vcc = 1 will trigger VBCC, else GCC
|
# compiler_vcc = 1 will trigger VBCC, else GCC
|
||||||
compiler_vcc = 1
|
compiler_vcc = 0
|
||||||
|
|
||||||
###############################################################################
|
###############################################################################
|
||||||
# prefix for system includes (ASM)
|
# prefix for system includes (ASM)
|
||||||
#
|
# native AmigaOS compilation: set PREFX=GG: or PREFX=ADE:, depending on toolchain
|
||||||
###############################################################################
|
###############################################################################
|
||||||
PREFX = c:/Users/Matze/Amiga/development/VBCC/
|
#PREFX = /opt/amigaos-68k/
|
||||||
#PREFX = gg:
|
PREFX = gg:
|
||||||
SYSINC = $(PREFX)NDK39/Include/include_i
|
SYSINC = $(PREFX)os-include
|
||||||
|
|
||||||
###############################################################################
|
###############################################################################
|
||||||
#
|
#
|
||||||
@@ -41,6 +41,7 @@ ifeq ($(compiler_vcc),1)
|
|||||||
# VBCC (use explicit vlink line for LINK= if complaints about R_PC happen)
|
# VBCC (use explicit vlink line for LINK= if complaints about R_PC happen)
|
||||||
CCX = vc
|
CCX = vc
|
||||||
LINK = vlink -bamigahunk -x -s -mrel -Cvbcc -Bstatic -nostdlib #-Rshort
|
LINK = vlink -bamigahunk -x -s -mrel -Cvbcc -Bstatic -nostdlib #-Rshort
|
||||||
|
LINKEXE = vlink -bamigahunk -x -s -mrel -Cvbcc -Bstatic
|
||||||
#LINK = $(CCX) -nostdlib
|
#LINK = $(CCX) -nostdlib
|
||||||
CFLAGS = -Os -+ -sc -c99 -cpu=$(CPU)
|
CFLAGS = -Os -+ -sc -c99 -cpu=$(CPU)
|
||||||
CFLAGS2 = -Os -+ -sc -c99 -cpu=$(CPU2)
|
CFLAGS2 = -Os -+ -sc -c99 -cpu=$(CPU2)
|
||||||
@@ -50,6 +51,7 @@ else
|
|||||||
# GCC
|
# GCC
|
||||||
CCX = m68k-amigaos-gcc
|
CCX = m68k-amigaos-gcc
|
||||||
LINK = $(CCX) -nostartfiles -s
|
LINK = $(CCX) -nostartfiles -s
|
||||||
|
LINKEXE = $(CCX) -s -noixemul
|
||||||
CFLAGS = -O3 -s -m$(CPU) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
|
CFLAGS = -O3 -s -m$(CPU) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
|
||||||
CFLAGS2 = -O3 -s -m$(CPU2) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
|
CFLAGS2 = -O3 -s -m$(CPU2) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
|
||||||
|
|
||||||
@@ -68,7 +70,7 @@ VASMFORMAT2 = -m$(CPU2) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
|
|||||||
#
|
#
|
||||||
###############################################################################
|
###############################################################################
|
||||||
|
|
||||||
IPATH =
|
IPATH =
|
||||||
|
|
||||||
###############################################################################
|
###############################################################################
|
||||||
#
|
#
|
||||||
@@ -77,29 +79,41 @@ IPATH =
|
|||||||
###############################################################################
|
###############################################################################
|
||||||
ifeq ($(compiler_vcc),1)
|
ifeq ($(compiler_vcc),1)
|
||||||
# skip quotes with VCC, the AmigaOS native version doesn't like them
|
# skip quotes with VCC, the AmigaOS native version doesn't like them
|
||||||
DEFINES += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
#DEFINES += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
DEFINES += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME="$(DEVICEID)"
|
#DEFINES += -DDEVICEDATE=$(DEVICEDATE)
|
||||||
DEFINES += -DDEVICEEXTRA=$(DEVICEEXTRA)
|
#DEFINES += -DDEVICEEXTRA=$(DEVICEEXTRA)
|
||||||
ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
DEFINES += -DDEVICENAME="$(DEVICEID)"
|
||||||
|
DEFINES += -DHAVE_VERSION_H=1
|
||||||
|
DEFINES += -DNEWSTYLE
|
||||||
|
#ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
|
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
|
||||||
|
|
||||||
DEFINES2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
#DEFINES2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
DEFINES2 += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME="$(DEVICEID2)"
|
#DEFINES2 += -DDEVICEDATE=$(DEVICEDATE)
|
||||||
DEFINES2 += -DDEVICEEXTRA=$(DEVICEEXTRA)
|
#DEFINES2 += -DDEVICEEXTRA=$(DEVICEEXTRA)
|
||||||
ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
DEFINES2 += -DDEVICENAME="$(DEVICEID2)"
|
||||||
|
DEFINES2 += -DHAVE_VERSION_H=1
|
||||||
|
DEFINES2 += -DNEWSTYLE
|
||||||
|
#ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
|
|
||||||
else
|
else
|
||||||
|
|
||||||
DEFINES += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
|
#DEFINES += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
|
||||||
DEFINES += -D"DEVICEDATE=$(DEVICEDATE)" -D"DEVICENAME="$(DEVICEID)""
|
#DEFINES += -D"DEVICEDATE=$(DEVICEDATE)"
|
||||||
DEFINES += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
|
#DEFINES += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
|
||||||
ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
DEFINES += -D"DEVICENAME="$(DEVICEID)""
|
||||||
|
DEFINES += -DHAVE_VERSION_H=1
|
||||||
|
DEFINES += -DNEWSTYLE
|
||||||
|
#ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
|
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
|
||||||
|
|
||||||
DEFINES2 += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
|
#DEFINES2 += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
|
||||||
DEFINES2 += -D"DEVICEDATE=$(DEVICEDATE)" -D"DEVICENAME="$(DEVICEID2)""
|
#DEFINES2 += -D"DEVICEDATE=$(DEVICEDATE)" -D"DEVICENAME="$(DEVICEID2)""
|
||||||
DEFINES2 += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
|
#DEFINES2 += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
|
||||||
ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
DEFINES2 += -D"DEVICENAME="$(DEVICEID2)""
|
||||||
|
DEFINES2 += -DHAVE_VERSION_H=1
|
||||||
|
DEFINES2 += -DNEWSTYLE
|
||||||
|
#ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
@@ -112,7 +126,7 @@ endif
|
|||||||
ifeq ($(debug),1)
|
ifeq ($(debug),1)
|
||||||
CFLAGS += -DDEBUG -g
|
CFLAGS += -DDEBUG -g
|
||||||
CFLAGS2 += -DDEBUG -g
|
CFLAGS2 += -DDEBUG -g
|
||||||
LINKLIBS = -L$(PREFX)targets/m68k-amigaos/lib -ldebug
|
LINKLIBS = -L$(PREFX)/lib -ldebug
|
||||||
endif
|
endif
|
||||||
|
|
||||||
###############################################################################
|
###############################################################################
|
||||||
@@ -144,11 +158,11 @@ OBJECTS2 = $(patsubst %.o,%.2o,$(OBJECTS))
|
|||||||
#
|
#
|
||||||
###############################################################################
|
###############################################################################
|
||||||
|
|
||||||
all: $(DEVICEID) $(DEVICEID2)
|
all: $(DEVICEID) $(DEVICEID2) $(TESTTOOL) $(TESTTOOL2)
|
||||||
|
|
||||||
clean:
|
clean:
|
||||||
rm -f $(OBJECTS) $(OBJECTS2)
|
rm -f $(OBJECTS) $(OBJECTS2)
|
||||||
rm -f $(DEVICEID) $(DEVICEID2)
|
rm -f $(DEVICEID) $(DEVICEID2) $(EXTRACLEAN)
|
||||||
|
|
||||||
# not for cross compile :-)
|
# not for cross compile :-)
|
||||||
install: $(DEVICEID) $(DEVICEID2)
|
install: $(DEVICEID) $(DEVICEID2)
|
||||||
|
|||||||
@@ -32,7 +32,7 @@ ASMOBJECTS = $(SUBDIR)/enc624j6l.o $(SUBDIR)/intervaltimer.o kprintf.o
|
|||||||
|
|
||||||
DEVICEID=enc624j6net.device
|
DEVICEID=enc624j6net.device
|
||||||
DEFINES = -DHW_DMA_TX # -DPROTO_V2EXPNET
|
DEFINES = -DHW_DMA_TX # -DPROTO_V2EXPNET
|
||||||
ASMDEFS = # -DPROTO_V2EXPNET
|
ASMDEFS = -DHW_DMA_TX # -DPROTO_V2EXPNET
|
||||||
CPU = 68020
|
CPU = 68020
|
||||||
|
|
||||||
DEVICEID2=enc624j6net.device_68000
|
DEVICEID2=enc624j6net.device_68000
|
||||||
|
|||||||
@@ -19,9 +19,10 @@ _LVORawMayGetChar equ -$1fe
|
|||||||
;
|
;
|
||||||
;
|
;
|
||||||
;
|
;
|
||||||
ifd DEBUG
|
ifne DEBUG
|
||||||
|
|
||||||
XREF _KPrintF
|
; XREF _KPrintFa0a1
|
||||||
|
; XREF _KPrintF
|
||||||
|
|
||||||
WRITEDEBUG macro
|
WRITEDEBUG macro
|
||||||
movem.l d0/d1/a0/a1,-(sp)
|
movem.l d0/d1/a0/a1,-(sp)
|
||||||
@@ -51,7 +52,7 @@ WRITEDEBUG macro
|
|||||||
endif
|
endif
|
||||||
lea.l (\1),a0
|
lea.l (\1),a0
|
||||||
move.l sp,a1
|
move.l sp,a1
|
||||||
jsr _KPrintF
|
jsr _KPrintFa0a1
|
||||||
ifnb \2
|
ifnb \2
|
||||||
add.l #4,sp
|
add.l #4,sp
|
||||||
endif
|
endif
|
||||||
@@ -80,7 +81,7 @@ WRITEDEBUG macro
|
|||||||
endm
|
endm
|
||||||
else
|
else
|
||||||
WRITEDEBUG macro
|
WRITEDEBUG macro
|
||||||
nop
|
;
|
||||||
endm
|
endm
|
||||||
endc
|
endc
|
||||||
|
|
||||||
@@ -117,7 +118,7 @@ WRITEOUT macro
|
|||||||
ifd DEBUG
|
ifd DEBUG
|
||||||
move.l \1,a0
|
move.l \1,a0
|
||||||
move.l sp,a1
|
move.l sp,a1
|
||||||
jsr _KPrintF
|
jsr _KPrintFa0a1
|
||||||
endif
|
endif
|
||||||
move.l \1,d1
|
move.l \1,d1
|
||||||
move.l sp,d2
|
move.l sp,d2
|
||||||
|
|||||||
@@ -75,6 +75,12 @@ const struct NSDeviceQueryResult NSDQueryAnswer = {
|
|||||||
#include "hw.h"
|
#include "hw.h"
|
||||||
#include "macros.h"
|
#include "macros.h"
|
||||||
|
|
||||||
|
/* enable heavy debug (D2=beginIO) */
|
||||||
|
#define D2(x)
|
||||||
|
#define D4(x)
|
||||||
|
/* #define D2(x) D(x) */
|
||||||
|
/* #define D4(x) D(x) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -382,7 +388,8 @@ ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
|
|||||||
/*ioreq->ios2_Req.io_Error = S2ERR_NO_ERROR;
|
/*ioreq->ios2_Req.io_Error = S2ERR_NO_ERROR;
|
||||||
ioreq->ios2_WireError = S2WERR_GENERIC_ERROR;*/
|
ioreq->ios2_WireError = S2WERR_GENERIC_ERROR;*/
|
||||||
|
|
||||||
D(("BeginIO command %ld unit %ld\n",(LONG)ioreq->ios2_Req.io_Command,unit));
|
/* heavy debug on beginIO */
|
||||||
|
D2(("BeginIO command %ld unit %ld\n",(LONG)ioreq->ios2_Req.io_Command,unit));
|
||||||
|
|
||||||
switch( ioreq->ios2_Req.io_Command )
|
switch( ioreq->ios2_Req.io_Command )
|
||||||
{
|
{
|
||||||
|
|||||||
Binary file not shown.
Binary file not shown.
@@ -20,19 +20,25 @@
|
|||||||
; - _enc624j6l_RXReset -> won't recover from totally unresponsive chip (but exits gracefully)
|
; - _enc624j6l_RXReset -> won't recover from totally unresponsive chip (but exits gracefully)
|
||||||
;
|
;
|
||||||
; enable debugging code block (comment/uncomment, see below)
|
; enable debugging code block (comment/uncomment, see below)
|
||||||
;DEBUG EQU 1
|
DEBUG EQU 0
|
||||||
|
GLOBALINT_BOARD EQU 1 ;if 1, then toggle board interrupt, else ENC624 INTIE
|
||||||
|
|
||||||
incdir src:baxnet/trunk/source/
|
incdir src:baxnet/trunk/source/
|
||||||
;Temp:Amiga/src/Zorro-LAN-IDE.git/Driver/enc624j6net/
|
;Temp:Amiga/src/Zorro-LAN-IDE.git/Driver/enc624j6net/
|
||||||
include "enc624j6net/registers.i"
|
include "enc624j6net/registers.i"
|
||||||
include "enc624j6net/macros.i"
|
include "enc624j6net/macros.i"
|
||||||
include "debug.i"
|
|
||||||
include "hw.i"
|
|
||||||
|
|
||||||
ifnd DEBUG
|
ifnd DEBUG
|
||||||
DEBUG EQU 0
|
DEBUG EQU 0
|
||||||
endc
|
endc
|
||||||
|
|
||||||
|
ifne 1
|
||||||
|
include "debug.i"
|
||||||
|
else
|
||||||
|
WRITEDEBUG macro
|
||||||
|
nop
|
||||||
|
endm
|
||||||
|
endc
|
||||||
;
|
;
|
||||||
ADD_4RX EQU 1 ;add 4 to valid RX size (fake CRC), fixes shapeshifter RAW treatment
|
ADD_4RX EQU 1 ;add 4 to valid RX size (fake CRC), fixes shapeshifter RAW treatment
|
||||||
_OPT_LONGRESET EQU 0 ;in testing, don't enable
|
_OPT_LONGRESET EQU 0 ;in testing, don't enable
|
||||||
@@ -41,7 +47,7 @@ _OPT_LONGRESET EQU 0 ;in testing, don't enable
|
|||||||
;
|
;
|
||||||
; options for buffer memory configuration, please reserve some space for private variables
|
; options for buffer memory configuration, please reserve some space for private variables
|
||||||
;
|
;
|
||||||
PSTART_INIT EQU $0BF0 ; 16 Bytes private storage for driver
|
PSTART_INIT EQU $0BF8 ; 8 Bytes private storage for driver
|
||||||
PSTOP_INIT EQU $0BFF ; (see below for definitions)
|
PSTOP_INIT EQU $0BFF ; (see below for definitions)
|
||||||
|
|
||||||
RXSTART_INIT EQU $0C00 ; start of RX buffer, room for 14 packets
|
RXSTART_INIT EQU $0C00 ; start of RX buffer, room for 14 packets
|
||||||
@@ -57,10 +63,8 @@ MAX_FRAMELEN EQU 1518
|
|||||||
;------------ driver private storage ------------------------------
|
;------------ driver private storage ------------------------------
|
||||||
PNextPacket EQU PSTART_INIT ;2 Bytes - private "next packet" pointer for RX
|
PNextPacket EQU PSTART_INIT ;2 Bytes - private "next packet" pointer for RX
|
||||||
PNextTX EQU PSTART_INIT+2 ;2 Bytes - private "next packet" pointer for TX (init as 0)
|
PNextTX EQU PSTART_INIT+2 ;2 Bytes - private "next packet" pointer for TX (init as 0)
|
||||||
PSigBit EQU PSTART_INIT+4 ;2 Bytes interrupt bit
|
PLinkChange EQU PSTART_INIT+4 ;2 Bytes Link Change (copy of PHYDPX,PHYLNK bits)
|
||||||
PSigTask EQU PSTART_INIT+6 ;4 Bytes signaled task
|
Punused EQU PSTART_INIT+6 ;
|
||||||
PLinkChange EQU PSTART_INIT+10 ;2 Bytes Link Change (copy of PHYDPX,PHYLNK bits)
|
|
||||||
Punused EQU PSTART_INIT+12 ;
|
|
||||||
|
|
||||||
;------------- TX: double buffering --------------------------------
|
;------------- TX: double buffering --------------------------------
|
||||||
PSwapTX EQU $600 ;swap between two TX buffers (one active, one activated after last TX done)
|
PSwapTX EQU $600 ;swap between two TX buffers (one active, one activated after last TX done)
|
||||||
@@ -137,12 +141,6 @@ _LVOSignal EQU -324
|
|||||||
|
|
||||||
section code,code
|
section code,code
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; -----------------------------------------------------------------------------
|
; -----------------------------------------------------------------------------
|
||||||
; | |
|
; | |
|
||||||
; | Test/Debug code |
|
; | Test/Debug code |
|
||||||
@@ -280,7 +278,13 @@ regtests:
|
|||||||
READREG ESTAT,a0,d0
|
READREG ESTAT,a0,d0
|
||||||
READREG ECON1,a0,d1
|
READREG ECON1,a0,d1
|
||||||
READREG MACON2,a0,d2
|
READREG MACON2,a0,d2
|
||||||
READREG MABBIPG,a0,d3
|
; READREG MABBIPG,a0,d3
|
||||||
|
|
||||||
|
READREG ERXFCON,a0,d3
|
||||||
|
READREG EHT1,a0,d4
|
||||||
|
READREG EHT2,a0,d5
|
||||||
|
READREG EHT3,a0,d6
|
||||||
|
READREG EHT4,a0,d7
|
||||||
rts
|
rts
|
||||||
|
|
||||||
|
|
||||||
@@ -560,6 +564,8 @@ _enc624j6l_Init:
|
|||||||
move.l a0,d0
|
move.l a0,d0
|
||||||
beq .err
|
beq .err
|
||||||
|
|
||||||
|
WRITEDEBUG Init_MSG,a0
|
||||||
|
|
||||||
READREG ESTAT,a0,d0
|
READREG ESTAT,a0,d0
|
||||||
and #(ESTAT_CLKRDY|ESTAT_PHYRDY),d0
|
and #(ESTAT_CLKRDY|ESTAT_PHYRDY),d0
|
||||||
cmp #(ESTAT_CLKRDY|ESTAT_PHYRDY),d0
|
cmp #(ESTAT_CLKRDY|ESTAT_PHYRDY),d0
|
||||||
@@ -588,6 +594,7 @@ _enc624j6l_Init:
|
|||||||
WRITEREG ERXST,a0,d0 ;set RX start pointer (end will be $5fff)
|
WRITEREG ERXST,a0,d0 ;set RX start pointer (end will be $5fff)
|
||||||
WRITEREG PNextPacket,a0,d0 ;set user read pointer
|
WRITEREG PNextPacket,a0,d0 ;set user read pointer
|
||||||
|
|
||||||
|
suba.l a1,a1 ;no multicast hash table (yet)
|
||||||
bsr _enc624j6l_bc_mc_filter ;in: A0/D1, out: D0
|
bsr _enc624j6l_bc_mc_filter ;in: A0/D1, out: D0
|
||||||
|
|
||||||
move #RXSTOP_INIT&$fffe,d0
|
move #RXSTOP_INIT&$fffe,d0
|
||||||
@@ -645,6 +652,7 @@ _enc624j6l_Init:
|
|||||||
;
|
;
|
||||||
; in: A0 - board base
|
; in: A0 - board base
|
||||||
; D1 - init flags
|
; D1 - init flags
|
||||||
|
; A1 - multicast hash table (4x USHORT)
|
||||||
;out: D0 >0 = OK
|
;out: D0 >0 = OK
|
||||||
; <=0 = FAIL
|
; <=0 = FAIL
|
||||||
_enc624j6l_bc_mc_filter:
|
_enc624j6l_bc_mc_filter:
|
||||||
@@ -659,15 +667,32 @@ _enc624j6l_bc_mc_filter:
|
|||||||
move #ERXFCON_NOTMEEN|ERXFCON_MCEN|ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
move #ERXFCON_NOTMEEN|ERXFCON_MCEN|ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
||||||
bra.s .setfilter
|
bra.s .setfilter
|
||||||
.no_promisc:
|
.no_promisc:
|
||||||
moveq #PIO_INIT_MULTI_CAST,d0
|
moveq #PIO_INIT_MULTI_CAST,d0 ;all multicast ?
|
||||||
and d1,d0
|
and d1,d0
|
||||||
beq.s .no_multicast
|
beq.s .no_multicast
|
||||||
move #ERXFCON_MCEN|ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
move #ERXFCON_MCEN|ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
||||||
bra.s .setfilter
|
bra.s .setfilter
|
||||||
.no_multicast:
|
.no_multicast:
|
||||||
move #ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
move #ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
|
||||||
|
|
||||||
|
; did we get a multicast hash table ?
|
||||||
|
move.l a1,d1
|
||||||
|
beq.s .nohashes
|
||||||
|
AND #$ffff-ERXFCON_MCEN,d0 ;don't accept ALL multicast
|
||||||
|
OR #ERXFCON_HTEN,d0 ;enable multicast hash table filter
|
||||||
|
|
||||||
|
move (a1),d1
|
||||||
|
WRITEREG EHT1,a0,d1
|
||||||
|
move 2(a1),d1
|
||||||
|
WRITEREG EHT2,a0,d1
|
||||||
|
move 4(a1),d1
|
||||||
|
WRITEREG EHT3,a0,d1
|
||||||
|
move 6(a1),d1
|
||||||
|
WRITEREG EHT4,a0,d1
|
||||||
|
.nohashes:
|
||||||
|
|
||||||
.setfilter:
|
.setfilter:
|
||||||
WRITEREG ERXFCON,a0,d0 ;set filter TODO: pattern matching stuff
|
WRITEREG ERXFCON,a0,d0 ;set filter
|
||||||
|
|
||||||
moveq #1,d0
|
moveq #1,d0
|
||||||
.rts:
|
.rts:
|
||||||
@@ -787,20 +812,13 @@ _enc624j6l_EnableInterrupt:
|
|||||||
move.l a0,d1
|
move.l a0,d1
|
||||||
beq.s .err
|
beq.s .err
|
||||||
|
|
||||||
WRITEREG PSigBit,a0,d0 ;save signal bit
|
|
||||||
|
|
||||||
move.l a1,d0
|
|
||||||
WRITEREG PSigTask+2,a0,d0 ;lower two bytes
|
|
||||||
swap d0 ;
|
|
||||||
WRITEREG PSigTask,a0,d0 ;upper two bytes
|
|
||||||
|
|
||||||
; enable interrupt for incoming packet
|
; enable interrupt for incoming packet
|
||||||
moveq #-1,d0 ;magic trick: the board enables Interrupts
|
moveq #-1,d0 ;magic trick: the board enables Interrupts
|
||||||
lea $4000(a0),a0
|
lea $4000(a0),a0
|
||||||
move.w d0,($4000,a0)
|
move.w d0,($4000,a0)
|
||||||
lea -$4000(a0),a0
|
lea -$4000(a0),a0
|
||||||
|
|
||||||
move #EIE_PKTIE|EIE_PCFULIE|EIE_INTIE,d0
|
move #EIE_PKTIE|EIE_INTIE|EIE_PCFULIE,d0
|
||||||
SETREG EIE,a0,d0
|
SETREG EIE,a0,d0
|
||||||
|
|
||||||
moveq #1,d0
|
moveq #1,d0
|
||||||
@@ -823,8 +841,20 @@ _enc624j6l_EnableInterrupt:
|
|||||||
; Notes: assumes that init() was called before
|
; Notes: assumes that init() was called before
|
||||||
;
|
;
|
||||||
_enc624j6l_EnableGlobalInterrupt:
|
_enc624j6l_EnableGlobalInterrupt:
|
||||||
move #EIE_PKTIE|EIE_PCFULIE|EIE_INTIE,d0 ; move #EIE_INTIE,d0
|
ifne GLOBALINT_BOARD
|
||||||
SETREG EIE,a0,d0
|
|
||||||
|
moveq #-1,d0 ;magic trick: the board enables Interrupts
|
||||||
|
lea $4000(a0),a0
|
||||||
|
move.w d0,($4000,a0)
|
||||||
|
lea -$4000(a0),a0
|
||||||
|
|
||||||
|
else ;GLOBALINT_BOARD
|
||||||
|
|
||||||
|
move #EIE_PKTIE|EIE_INTIE|EIE_PCFULIE,d0
|
||||||
|
SETREG EIE,a0,d0
|
||||||
|
|
||||||
|
endc ;GLOBALINT_BOARD
|
||||||
|
|
||||||
moveq #1,d0
|
moveq #1,d0
|
||||||
.rts
|
.rts
|
||||||
rts
|
rts
|
||||||
@@ -842,8 +872,21 @@ _enc624j6l_EnableGlobalInterrupt:
|
|||||||
; Notes: assumes that init() was called before
|
; Notes: assumes that init() was called before
|
||||||
;
|
;
|
||||||
_enc624j6l_DisableGlobalInterrupt:
|
_enc624j6l_DisableGlobalInterrupt:
|
||||||
move #EIE_INTIE,d0
|
|
||||||
CLRREG EIE,a0,d0
|
ifne GLOBALINT_BOARD
|
||||||
|
|
||||||
|
moveq #0,d0 ;magic trick: the board enables Interrupts
|
||||||
|
lea $4000(a0),a0
|
||||||
|
move.w d0,($4000,a0)
|
||||||
|
lea -$4000(a0),a0
|
||||||
|
|
||||||
|
else ;GLOBALINT_BOARD
|
||||||
|
|
||||||
|
move #EIE_INTIE,d0
|
||||||
|
CLRREG EIE,a0,d0
|
||||||
|
|
||||||
|
endc ;GLOBALINT_BOARD
|
||||||
|
|
||||||
moveq #1,d0
|
moveq #1,d0
|
||||||
.rts
|
.rts
|
||||||
rts
|
rts
|
||||||
@@ -878,10 +921,6 @@ _enc624j6l_DisableInterrupt:
|
|||||||
move #EIE_INTIE|EIE_PKTIE|EIE_LINKIE|EIE_AESIE|EIE_MODEXIE|EIE_HASHIE|EIE_PRDYIE|EIE_DMAIE|EIE_TXIE|EIE_TXABTIE|EIE_RXABTIE|EIE_PCFULIE,d0
|
move #EIE_INTIE|EIE_PKTIE|EIE_LINKIE|EIE_AESIE|EIE_MODEXIE|EIE_HASHIE|EIE_PRDYIE|EIE_DMAIE|EIE_TXIE|EIE_TXABTIE|EIE_RXABTIE|EIE_PCFULIE,d0
|
||||||
CLRREG EIE,a0,d0
|
CLRREG EIE,a0,d0
|
||||||
|
|
||||||
moveq #0,d0
|
|
||||||
WRITEREG PSigTask+2,a0,d0 ;lower two bytes
|
|
||||||
WRITEREG PSigTask,a0,d0 ;upper two bytes
|
|
||||||
|
|
||||||
moveq #1,d0
|
moveq #1,d0
|
||||||
.err:
|
.err:
|
||||||
rts
|
rts
|
||||||
@@ -905,35 +944,50 @@ _enc624j6l_DisableInterrupt:
|
|||||||
; ULONG sigbit
|
; ULONG sigbit
|
||||||
;
|
;
|
||||||
_enc624j6l_IntServer_List:
|
_enc624j6l_IntServer_List:
|
||||||
|
move.l a6,-(sp)
|
||||||
|
|
||||||
move.l a1,d0 ;no pointer supplied ? -> return
|
move.l a1,d0 ;no pointer supplied ? -> return
|
||||||
beq.s .end
|
beq.s .rts
|
||||||
movem.l d1/A1/a6,-(sp)
|
|
||||||
|
|
||||||
move.l a1,a6
|
move.l a1,a6
|
||||||
|
|
||||||
moveq #0,d1
|
moveq #0,d1
|
||||||
move.l (A6)+,d0 ;read magic word
|
|
||||||
cmp.l #HW_MAGIC_WORD,D0 ; are we in the right structure?
|
|
||||||
bne.s .done
|
|
||||||
|
|
||||||
.boardloop:
|
.boardloop:
|
||||||
move.l (A6)+,d0 ;next entry from list
|
move.l (a1)+,d0 ;next entry from list
|
||||||
beq.s .done ;
|
beq.s .done ;
|
||||||
move.l d0,a1 ;current board
|
move.l d0,a0 ;current board
|
||||||
|
|
||||||
READREG EIR,A1,d0 ;get interrupt status reg
|
READREG EIR,a0,d0 ;get interrupt status reg
|
||||||
and #EIR_PKTIF|EIR_PCFULIF,D0
|
and #EIR_PKTIF|EIR_PCFULIF|EIR_RXABTIF|EIR_PKTIF|EIR_TXABTIF,d0
|
||||||
beq.s .boardloop ;no interrupt here
|
|
||||||
or.l d0,D1 ; save if at least one one board has interrupted
|
or.l d0,d1
|
||||||
move #EIE_INTIE,D0 ;disable board interrupt until someone enables it again
|
bra.s .boardloop
|
||||||
CLRREG EIE,A1,d0
|
|
||||||
BRA.s .boardloop
|
|
||||||
.done:
|
.done:
|
||||||
tst.w d1
|
tst.w d1
|
||||||
beq.s .rts
|
beq.s .rts
|
||||||
|
|
||||||
|
; clear EIE_INTIE in all active boards directly from here
|
||||||
|
.intdis_loop:
|
||||||
|
move.l (a6)+,d0
|
||||||
|
beq.s .boardsdone
|
||||||
|
move.l d0,a1
|
||||||
|
|
||||||
|
ifne GLOBALINT_BOARD
|
||||||
|
|
||||||
|
moveq #0,d0 ;magic trick: the board enables Interrupts
|
||||||
|
lea $4000(a1),a1
|
||||||
|
move.w d0,($4000,a1)
|
||||||
|
|
||||||
|
else ;GLOBALINT_BOARD
|
||||||
|
|
||||||
|
move #EIE_INTIE,D0 ;disable board interrupt until someone enables it again
|
||||||
|
CLRREG EIE,A1,d0
|
||||||
|
|
||||||
|
endc ;GLOBALINT_BOARD
|
||||||
|
|
||||||
|
bra.s .intdis_loop
|
||||||
|
.boardsdone:
|
||||||
|
|
||||||
;faster: get from extended Driver board list instead from ZII/ZIII card
|
;faster: get from extended Driver board list instead from ZII/ZIII card
|
||||||
ifne 1
|
|
||||||
|
|
||||||
move.l (a6)+,d0 ;SigTask
|
move.l (a6)+,d0 ;SigTask
|
||||||
beq.s .rts
|
beq.s .rts
|
||||||
@@ -941,33 +995,16 @@ _enc624j6l_IntServer_List:
|
|||||||
move.l (a6)+,d1 ;SigBit
|
move.l (a6)+,d1 ;SigBit
|
||||||
move.l d0,a1 ;SigTask
|
move.l d0,a1 ;SigTask
|
||||||
|
|
||||||
move.l (a6)+,a6 ;ExecBase
|
move.l (a6)+,a6 ;ExecBase (from FastRAM)
|
||||||
|
;move.l 4.w,a6
|
||||||
moveq #0,d0
|
moveq #0,d0
|
||||||
|
|
||||||
bset d1,d0
|
bset d1,d0
|
||||||
|
|
||||||
else
|
|
||||||
|
|
||||||
READREG PSigTask,a0,d0 ;upper two bytes
|
|
||||||
swap d0 ;
|
|
||||||
READREG PSigTask+2,a0,d0 ;lower two bytes
|
|
||||||
tst.l d0 ; no task ?
|
|
||||||
beq.s .rts
|
|
||||||
move.l d0,a1 ; signaled task
|
|
||||||
|
|
||||||
moveq #0,d0
|
|
||||||
READREG PSigBit,a0,d1 ;get signal bit
|
|
||||||
bset d1,d0 ;signal mask
|
|
||||||
|
|
||||||
move.l 4.w,a6
|
|
||||||
|
|
||||||
endc
|
|
||||||
|
|
||||||
jsr _LVOSignal(a6)
|
jsr _LVOSignal(a6)
|
||||||
|
|
||||||
.rts
|
.rts
|
||||||
movem.l (sp)+,D1/A1/A6
|
move.l (sp)+,a6
|
||||||
.end
|
|
||||||
moveq #0,d0 ;set Z flag
|
moveq #0,d0 ;set Z flag
|
||||||
rts
|
rts
|
||||||
|
|
||||||
@@ -1071,7 +1108,11 @@ _enc624j6l_CheckLinkChange:
|
|||||||
;
|
;
|
||||||
|
|
||||||
ifne DEBUG
|
ifne DEBUG
|
||||||
RXReset_MSG: dc.b "RXReset Head %04lx Tail %04lx NextPacket %04lx ReadPTR %04lx Bytes %04lx",10,0
|
RXReset_MSG: dc.b "RXReset Head %04lx Tail %04lx NextPacket %04lx NextReadPTR %04lx Bytes(maybe) %04lx ESTAT %04lx",13,10,0
|
||||||
|
Init_MSG: dc.b "ENC624j6net init (debug build) board address %lx",13,10,0
|
||||||
|
TXWait_MSG: dc.b "TransmitFrame: waiting",13,10,0
|
||||||
|
TXAbort_MSG: dc.b "TransmitFrame: abort",13,10,0
|
||||||
|
cnop 0,4
|
||||||
endc
|
endc
|
||||||
|
|
||||||
_enc624j6l_RXReset:
|
_enc624j6l_RXReset:
|
||||||
@@ -1084,6 +1125,8 @@ _enc624j6l_RXReset:
|
|||||||
moveq #0,d1
|
moveq #0,d1
|
||||||
moveq #0,d2
|
moveq #0,d2
|
||||||
moveq #0,d3
|
moveq #0,d3
|
||||||
|
moveq #0,d7
|
||||||
|
READREG ESTAT,a0,d7
|
||||||
READREG ERXHEAD,A0,d0
|
READREG ERXHEAD,A0,d0
|
||||||
READREG ERXTAIL,A0,d1
|
READREG ERXTAIL,A0,d1
|
||||||
READREG PNextPacket,a0,d2
|
READREG PNextPacket,a0,d2
|
||||||
@@ -1092,19 +1135,16 @@ _enc624j6l_RXReset:
|
|||||||
rol.w #8,d3 ;swap pointer to Big Endian
|
rol.w #8,d3 ;swap pointer to Big Endian
|
||||||
endc ;d3=next Packet (from receive status vector)
|
endc ;d3=next Packet (from receive status vector)
|
||||||
|
|
||||||
moveq #2,d5
|
moveq #2,d5
|
||||||
add d2,d5 ;increment pointer by one word
|
add d2,d5 ;increment pointer by one word
|
||||||
WRAPINDEX d5 ;wrap D4 if beyond buffer
|
WRAPINDEX d5 ;wrap D4 if beyond buffer
|
||||||
READSRAM a0,d5,d4 ;receive byte count
|
READSRAM a0,d5,d4 ;receive byte count
|
||||||
ifeq _OPT_BUFFER_SWAP
|
ifeq _OPT_BUFFER_SWAP
|
||||||
rol.w #8,d4 ;swap pointer to Big Endian
|
rol.w #8,d4 ;swap pointer to Big Endian
|
||||||
endc
|
endc
|
||||||
|
|
||||||
|
WRITEDEBUG RXReset_MSG,d0,d1,d2,d3,d4,d7
|
||||||
|
|
||||||
|
|
||||||
WRITEDEBUG RXReset_MSG,d0,d1,d2,d3,d4
|
|
||||||
|
|
||||||
movem.l (sp)+,d2-d7
|
movem.l (sp)+,d2-d7
|
||||||
endc
|
endc
|
||||||
|
|
||||||
@@ -1194,16 +1234,18 @@ _enc624j6l_HaveRecv:
|
|||||||
_enc624j6l_RecvFrame: ;
|
_enc624j6l_RecvFrame: ;
|
||||||
movem.l d2-d7/a1-a3,-(sp)
|
movem.l d2-d7/a1-a3,-(sp)
|
||||||
move.l a0,d1
|
move.l a0,d1
|
||||||
beq .err
|
beq .err
|
||||||
|
|
||||||
moveq #0,d0
|
moveq #0,d0
|
||||||
READREG ESTAT,a0,d2 ;number of pending frames
|
READREG ESTAT,a0,d2 ;number of pending frames
|
||||||
move.b d2,d0 ;clear out count (ESTAT_PKTCNT7...ESTAT_PKTCNT0)
|
move.b d2,d0 ;clear out count (ESTAT_PKTCNT7...ESTAT_PKTCNT0)
|
||||||
beq .rts ;nothing in buffer, return sheer emptiness
|
beq .rts ;nothing in buffer, return sheer emptiness
|
||||||
;at least one frame in buffer
|
;at least one frame in buffer
|
||||||
|
|
||||||
|
ifne DEBUG
|
||||||
READREG ERXHEAD,A0,d4
|
READREG ERXHEAD,A0,d4
|
||||||
READREG ERXTAIL,A0,d5
|
READREG ERXTAIL,A0,d5
|
||||||
|
endc
|
||||||
|
|
||||||
;----------- check next packet pointer and verify expected state -----------
|
;----------- check next packet pointer and verify expected state -----------
|
||||||
READREG PNextPacket,a0,d7 ;get user read pointer from private space
|
READREG PNextPacket,a0,d7 ;get user read pointer from private space
|
||||||
@@ -1215,15 +1257,6 @@ _enc624j6l_RecvFrame: ;
|
|||||||
rol.w #8,d0 ;swap pointer to Big Endian
|
rol.w #8,d0 ;swap pointer to Big Endian
|
||||||
endc
|
endc
|
||||||
|
|
||||||
; btst #0,d0
|
|
||||||
; beq.s .nozerobit
|
|
||||||
; nop
|
|
||||||
;.nozerobit
|
|
||||||
; btst #0,d7
|
|
||||||
; beq.s .nozerobit2
|
|
||||||
; nop
|
|
||||||
;.nozerobit2
|
|
||||||
|
|
||||||
;verify next packet pointer, re-initialize recv if this is invalid
|
;verify next packet pointer, re-initialize recv if this is invalid
|
||||||
cmp #RXSTOP_INIT,d0 ;bad pointer (<0 or >end of memory)
|
cmp #RXSTOP_INIT,d0 ;bad pointer (<0 or >end of memory)
|
||||||
bhi.w .recv_err
|
bhi.w .recv_err
|
||||||
@@ -1238,55 +1271,40 @@ _enc624j6l_RecvFrame: ;
|
|||||||
add.w d0,d1 ;next pkt + unwrap distance
|
add.w d0,d1 ;next pkt + unwrap distance
|
||||||
.ptrcheck:
|
.ptrcheck:
|
||||||
sub.w d7,d1 ;length of pkt
|
sub.w d7,d1 ;length of pkt
|
||||||
cmp #MAX_FRAMELEN+2+6,d1 ;must be smaller than max framelen + ptr + status vector
|
cmp #MAX_FRAMELEN+2+6+2,d1 ;must be smaller than max framelen + ptr + status vector + alignment
|
||||||
bhi .recv_err ;-> reinit recv (am I paranoid ? -> try ENC28J60, then you know why...)
|
bhi .recv_err ;-> reinit recv (am I paranoid ? -> try ENC28J60, then you know why...)
|
||||||
|
|
||||||
;debug: collect packet positions
|
|
||||||
;move.l recvptr,a2
|
|
||||||
;move d0,(a2)+
|
|
||||||
;move.l a2,recvptr
|
|
||||||
;addq.l #1,recvcount
|
|
||||||
;cmp.l #65536,recvcount
|
|
||||||
;bgt .recv_err
|
|
||||||
|
|
||||||
WRITEREG PNextPacket,a0,d0 ;write pointer for next packet
|
|
||||||
|
|
||||||
;------------------ check receive status vector -----------------------------
|
;------------------ check receive status vector -----------------------------
|
||||||
addq.w #2,d7 ;increment pointer
|
addq.w #2,d7 ;increment pointer
|
||||||
WRAPINDEX d7 ;wrap D7 if beyond buffer
|
WRAPINDEX d7 ;wrap D7 if beyond buffer
|
||||||
;lea (a0,d7.w),a2 ;read ptr for first control word
|
|
||||||
;READREG 0,a2,d0 ;last control word = length (byte count)
|
ifne 0
|
||||||
READSRAM a0,d7,d0 ;move (a0,d7.w),d0
|
READSRAM a0,d7,d2 ;move (a0,d7.w),d0
|
||||||
ifeq _OPT_BUFFER_SWAP
|
ifeq _OPT_BUFFER_SWAP
|
||||||
rol.w #8,d0 ;swap pointer to Big Endian
|
rol.w #8,d2 ;swap pointer to Big Endian
|
||||||
|
endc
|
||||||
|
and.w #$f800,d2 ;verify (should be all zeros in upper 9 bits)
|
||||||
|
bne .recv_err ;receive buffer is wrong -> re-initialize
|
||||||
endc
|
endc
|
||||||
|
|
||||||
and.w #$f800,d0 ;verify (should be all zeros in upper 9 bits)
|
|
||||||
bne .recv_err ;receive buffer is wrong -> re-initialize
|
|
||||||
|
|
||||||
addq.w #4,d7 ;increment pointer
|
addq.w #4,d7 ;increment pointer
|
||||||
WRAPINDEX d7 ;wrap D7 if beyond buffer
|
WRAPINDEX d7 ;wrap D7 if beyond buffer
|
||||||
;lea (a0,d7.w),a2 ;new read pointer for length
|
|
||||||
;READREG 0,a2,d0 ;last control word = length (byte count)
|
|
||||||
READSRAM a0,d7,d0 ;move (a0,d7.w),d0
|
|
||||||
ifeq _OPT_BUFFER_SWAP
|
|
||||||
rol.w #8,d0 ;swap pointer to Big Endian
|
|
||||||
endc
|
|
||||||
|
|
||||||
ifne 1
|
WRITEREG PNextPacket,a0,d0 ;write pointer for next packet
|
||||||
|
|
||||||
|
ifne 0
|
||||||
|
;lea (a0,d7.w),a2 ;new read pointer for length
|
||||||
|
;READREG 0,a2,d0 ;last control word = length (byte count)
|
||||||
|
READSRAM a0,d7,d2 ;move (a0,d7.w),d0
|
||||||
|
ifeq _OPT_BUFFER_SWAP
|
||||||
|
rol.w #8,d2 ;swap pointer to Big Endian
|
||||||
|
endc ;_OPT_BUFFER_SWAP
|
||||||
|
endc ;0
|
||||||
|
|
||||||
;D1 is the distance to the next frame = stored length + recv vevtor
|
;D1 is the distance to the next frame = stored length + recv vevtor
|
||||||
sub #6+2,d1 ;STATUS VECTOR, Pointer
|
subq #6+2,d1 ;STATUS VECTOR, Pointer
|
||||||
move d1,d0 ;
|
move d1,d0 ;
|
||||||
|
|
||||||
else
|
|
||||||
|
|
||||||
cmp #2,d0
|
|
||||||
blt .recv_err ;can't be: SRC MAC 6 DST MAC 6 LEN/TYPE 2 CRC 4 (discounting variable data)
|
|
||||||
cmp #MAX_FRAMELEN,d0
|
|
||||||
bgt .recv_err
|
|
||||||
|
|
||||||
endc
|
|
||||||
|
|
||||||
subq #4,d0 ;subtract CRC length
|
subq #4,d0 ;subtract CRC length
|
||||||
|
|
||||||
addq.w #2,d7 ;increment pointer (skip status vector length field)
|
addq.w #2,d7 ;increment pointer (skip status vector length field)
|
||||||
@@ -1365,6 +1383,10 @@ _enc624j6l_RecvFrame: ;
|
|||||||
bra.s .end_read
|
bra.s .end_read
|
||||||
|
|
||||||
.nooptrecv:
|
.nooptrecv:
|
||||||
|
;DEBUG ONLY
|
||||||
|
;bra.s .emergency_slow
|
||||||
|
;DEBUG ONLY
|
||||||
|
|
||||||
ifeq _OPT_BUFFER_SWAP ;1
|
ifeq _OPT_BUFFER_SWAP ;1
|
||||||
;
|
;
|
||||||
;wraparound aware loop for big endian buffer
|
;wraparound aware loop for big endian buffer
|
||||||
@@ -1462,7 +1484,13 @@ _enc624j6l_RecvFrame: ;
|
|||||||
rts
|
rts
|
||||||
.err: moveq #-1,d0 ;receive error
|
.err: moveq #-1,d0 ;receive error
|
||||||
bra.s .rts
|
bra.s .rts
|
||||||
|
|
||||||
.recv_err:
|
.recv_err:
|
||||||
|
moveq #0,d0
|
||||||
|
READREG ESTAT,a0,d2 ;number of pending frames
|
||||||
|
move.b d2,d0 ;clear out count (ESTAT_PKTCNT7...ESTAT_PKTCNT0)
|
||||||
|
beq.s .rts ;nothing in buffer, return sheer emptiness
|
||||||
|
|
||||||
;serious problem: we need to re-initialize the recv buffer here
|
;serious problem: we need to re-initialize the recv buffer here
|
||||||
bsr _enc624j6l_RXReset
|
bsr _enc624j6l_RXReset
|
||||||
|
|
||||||
@@ -1613,18 +1641,22 @@ _enc624j6l_TransmitFrame:
|
|||||||
.copydone
|
.copydone
|
||||||
|
|
||||||
;---------------- wait on last frame ----------------------------------
|
;---------------- wait on last frame ----------------------------------
|
||||||
move #200,d3
|
move #600,d3 ;
|
||||||
.txwait:
|
.txwait:
|
||||||
READREG ECON1,a0,d1
|
READREG ECON1,a0,d1
|
||||||
and.w #ECON1_TXRTS,d1
|
and.w #ECON1_TXRTS,d1
|
||||||
beq.s .txrdy
|
beq.s .txrdy
|
||||||
;100 MBit/s frame time is max. 0.12 ms (without inter-frame spacing)
|
;100 MBit/s frame time is max. 0.12 ms (without inter-frame spacing)
|
||||||
|
|
||||||
;wait 20 us via CIA
|
;WRITEDEBUG TXWait_MSG
|
||||||
moveq #20,d0
|
|
||||||
|
;wait 5 us via CIA
|
||||||
|
moveq #5,d0
|
||||||
bsr _enc624j6l_UMinDelay
|
bsr _enc624j6l_UMinDelay
|
||||||
dbf d3,.txwait ;approx. 4ms max. wait
|
dbf d3,.txwait ;approx. 4ms max. wait
|
||||||
|
|
||||||
|
WRITEDEBUG TXAbort_MSG
|
||||||
|
|
||||||
;hmpf. abort last transmission
|
;hmpf. abort last transmission
|
||||||
move #ECON1_TXRTS,d1 ;
|
move #ECON1_TXRTS,d1 ;
|
||||||
CLRREG ECON1,a0,d1 ;
|
CLRREG ECON1,a0,d1 ;
|
||||||
|
|||||||
@@ -239,8 +239,9 @@ ASM SAVEDS int enc624j6l_SetOnline( ASMR(a0) void *board ASMREG(a0) );
|
|||||||
>=0 - OK
|
>=0 - OK
|
||||||
*/
|
*/
|
||||||
ASM SAVEDS int enc624j6l_bc_mc_filter(
|
ASM SAVEDS int enc624j6l_bc_mc_filter(
|
||||||
ASMR(a0) void *board ASMREG(a0),
|
ASMR(a0) void *board ASMREG(a0),
|
||||||
ASMR(d1) unsigned long flags ASMREG(d1) );
|
ASMR(d1) unsigned long flags ASMREG(d1),
|
||||||
|
ASMR(a1) unsigned short *mc_hashes ASMREG(a1));
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|||||||
@@ -30,6 +30,7 @@ extern const BYTE DeviceName[];
|
|||||||
/* use generic board fields in current unit */
|
/* use generic board fields in current unit */
|
||||||
#define duh_online du_hwl0
|
#define duh_online du_hwl0
|
||||||
#define duh_BASE du_hwp0
|
#define duh_BASE du_hwp0
|
||||||
|
#define duh_RefCount du_hwl1
|
||||||
|
|
||||||
#define HW_INTERVALDEF 100000L
|
#define HW_INTERVALDEF 100000L
|
||||||
|
|
||||||
@@ -105,7 +106,7 @@ ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
|
|||||||
|
|
||||||
/* bring board to sane state (i.e. perform soft reset) */
|
/* bring board to sane state (i.e. perform soft reset) */
|
||||||
/* if( boardbase < (APTR)0x40000000 ) */ /* debug only */
|
/* if( boardbase < (APTR)0x40000000 ) */ /* debug only */
|
||||||
enc624j6l_CheckBoard( boardbase );
|
enc624j6l_CheckBoard( boardbase );
|
||||||
}
|
}
|
||||||
ret = i;
|
ret = i;
|
||||||
D(("%ld boards found\n",ret));
|
D(("%ld boards found\n",ret));
|
||||||
@@ -119,7 +120,33 @@ ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
|
|||||||
ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
|
ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
|
||||||
ASMR(d0) ULONG unit ASMREG(d0) )
|
ASMR(d0) ULONG unit ASMREG(d0) )
|
||||||
{
|
{
|
||||||
/* is there a way to lock a ZII Board ? */
|
#if 0
|
||||||
|
LONG i;
|
||||||
|
struct ConfigDev *cfg = (0);
|
||||||
|
|
||||||
|
if( unit > db->db_NBoards )
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
for( i=0 ; i < db->db_NBoards ; i++ )
|
||||||
|
{
|
||||||
|
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
|
||||||
|
if( !cfg )
|
||||||
|
return 0;
|
||||||
|
if( (APTR)cfg->cd_BoardAddr == db->db_Units[unit].duh_BASE )
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if( (APTR)cfg->cd_BoardAddr != db->db_Units[unit].duh_BASE )
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if( db->db_Units[unit].duh_RefCount == 0 )
|
||||||
|
{
|
||||||
|
ObtainConfigBinding();
|
||||||
|
|
||||||
|
ReleaseConfigBinding();
|
||||||
|
}
|
||||||
|
db->db_Units[unit].duh_RefCount++;
|
||||||
|
#endif
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -127,6 +154,20 @@ ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
|
|||||||
ASM SAVEDS LONG hw_ReleaseBoard( ASMR(a0) DEVBASEP ASMREG(a0),
|
ASM SAVEDS LONG hw_ReleaseBoard( ASMR(a0) DEVBASEP ASMREG(a0),
|
||||||
ASMR(d0) ULONG unit ASMREG(d0) )
|
ASMR(d0) ULONG unit ASMREG(d0) )
|
||||||
{
|
{
|
||||||
|
#if 0
|
||||||
|
if( unit > db->db_NBoards )
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
for( i=0 ; i < db->db_NBoards ; i++ )
|
||||||
|
{
|
||||||
|
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
|
||||||
|
if( !cfg )
|
||||||
|
return 0;
|
||||||
|
if( (APTR)cfg->cd_BoardAddr == db->db_Units[unit].duh_BASE )
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -427,27 +468,143 @@ ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(
|
|||||||
return enc624j6l_WritePHY( boardbase, reg, value );
|
return enc624j6l_WritePHY( boardbase, reg, value );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
calculate CRC32 for MAC address hashing
|
||||||
|
slow but relatively short (and can be adapted to other
|
||||||
|
polynoms easily)
|
||||||
|
*/
|
||||||
|
ASM ULONG myhw_CRC32( ASMR(a0) UBYTE *buffer ASMREG(a0),
|
||||||
|
ASMR(d0) ULONG nbytes ASMREG(d0) )
|
||||||
|
{
|
||||||
|
UWORD i,j;
|
||||||
|
ULONG t,crc = 0xffffffff;
|
||||||
|
ULONG poly = 0x04c11db7;
|
||||||
|
|
||||||
|
for( j = 0 ; j < nbytes ; j++ )
|
||||||
|
{
|
||||||
|
for( i = 0 ; i < 8 ; i++ )
|
||||||
|
{
|
||||||
|
t = crc>>31;
|
||||||
|
crc <<= 1;
|
||||||
|
if( ( t ^ ( buffer[j] >> i ) ) & 0x01 )
|
||||||
|
crc ^= poly;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return crc;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
ASM ULONG CMPgeMAC( ASMR(a0) UBYTE *cur ASMREG(a0),
|
||||||
|
ASMR(a1) UBYTE *cmp ASMREG(a1) )
|
||||||
|
{
|
||||||
|
USHORT i;
|
||||||
|
ULONG res = 1;
|
||||||
|
|
||||||
|
for( i = 0 ; i < 6 ; i++ )
|
||||||
|
{
|
||||||
|
if( cur[i] > cmp[i] )
|
||||||
|
break;
|
||||||
|
if( cur[i] < cmp[i] )
|
||||||
|
{
|
||||||
|
res = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASM ULONG CMPleMAC( ASMR(a0) UBYTE *cur ASMREG(a0),
|
||||||
|
ASMR(a1) UBYTE *cmp ASMREG(a1) )
|
||||||
|
{
|
||||||
|
USHORT i;
|
||||||
|
ULONG res = 1;
|
||||||
|
|
||||||
|
for( i = 0 ; i < 6 ; i++ )
|
||||||
|
{
|
||||||
|
if( cur[i] < cmp[i] )
|
||||||
|
break;
|
||||||
|
if( cur[i] > cmp[i] )
|
||||||
|
{
|
||||||
|
res = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
ASM void INCMAC( ASMR(a0) UBYTE *curmc ASMREG(a0) )
|
||||||
|
{
|
||||||
|
SHORT i;
|
||||||
|
for( i=5 ; i >= 0 ; i-- )
|
||||||
|
{
|
||||||
|
curmc[i]++;
|
||||||
|
if( curmc[i] != 0 )
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* TODO: implement Multicast hashing */
|
||||||
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
|
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
|
||||||
ASMR(d0) ULONG unit ASMREG(d0),
|
ASMR(d0) ULONG unit ASMREG(d0),
|
||||||
ASMR(a1) struct List *mcastlist ASMREG(a1) )
|
ASMR(a1) struct List *mcastlist ASMREG(a1) )
|
||||||
{
|
{
|
||||||
/* TODO: implement Multicast hashing */
|
APTR boardbase = db->db_Units[unit].duh_BASE;
|
||||||
APTR boardbase = db->db_Units[unit].duh_BASE;
|
struct HWData *hwd = &db->db_hwdat;
|
||||||
ULONG flags;
|
ULONG flags;
|
||||||
|
ULONG crc,curhash;
|
||||||
|
USHORT mc_hashes[4] = {0,0,0,0}; /* EHT1, EHT2, EHT3, EHT4 */
|
||||||
|
USHORT *hash_tab;
|
||||||
|
struct MCastEntry *mc;
|
||||||
|
UBYTE *curmc;
|
||||||
|
|
||||||
flags = PIO_INIT_BROAD_CAST;
|
flags = PIO_INIT_BROAD_CAST;
|
||||||
|
|
||||||
if( db->db_Units[0].du_Flags & DUF_PROMISC )
|
if( db->db_Units[0].du_Flags & DUF_PROMISC )
|
||||||
flags |= PIO_INIT_PROMISC;
|
flags |= PIO_INIT_PROMISC;
|
||||||
|
|
||||||
/* list non-empty ? (kludge right now, can be done more fine grained) */
|
if( hwd->multicast ) /* accept ALL multicast ? (config option) */
|
||||||
if( mcastlist->lh_Head->ln_Succ )
|
|
||||||
flags |= PIO_INIT_MULTI_CAST;
|
flags |= PIO_INIT_MULTI_CAST;
|
||||||
|
|
||||||
enc624j6l_bc_mc_filter(boardbase, flags );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
|
/* list non-empty ? */
|
||||||
|
hash_tab = NULL;
|
||||||
|
if( mcastlist->lh_Head->ln_Succ )
|
||||||
|
{
|
||||||
|
/* flags |= PIO_INIT_MULTI_CAST; */ /* see above */
|
||||||
|
hash_tab = mc_hashes;
|
||||||
|
|
||||||
|
for( mc = (struct MCastEntry *)mcastlist->lh_Head;
|
||||||
|
mc->mce_Node.mln_Succ ;
|
||||||
|
mc=(struct MCastEntry*)mc->mce_Node.mln_Succ )
|
||||||
|
{
|
||||||
|
curmc = mc->mce_start;
|
||||||
|
while( CMPleMAC( curmc, mc->mce_stop ) )
|
||||||
|
{
|
||||||
|
D(("CMPleMAC %ld %02lx%02lx%02lx%02lx%02lx%02lx - %02lx%02lx%02lx%02lx%02lx%02lx\n",\
|
||||||
|
CMPleMAC( curmc, mc->mce_stop ),\
|
||||||
|
(ULONG)curmc[0],(ULONG)curmc[1],\
|
||||||
|
(ULONG)curmc[2],(ULONG)curmc[3],\
|
||||||
|
(ULONG)curmc[4],(ULONG)curmc[5],\
|
||||||
|
(ULONG)mc->mce_stop[0],(ULONG)mc->mce_stop[1],\
|
||||||
|
(ULONG)mc->mce_stop[2],(ULONG)mc->mce_stop[3],\
|
||||||
|
(ULONG)mc->mce_stop[4],(ULONG)mc->mce_stop[5] \
|
||||||
|
));
|
||||||
|
|
||||||
|
crc = myhw_CRC32( mc->mce_start, 6 );
|
||||||
|
curhash = (crc & 0x1f800000)>>23; /* 2 bit reg, 4 bit hash pos in reg */
|
||||||
|
mc_hashes[ ((curhash >> 4)&3) ] |= 1<<(curhash&0xf);
|
||||||
|
INCMAC( curmc );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
D(("hw_change_multicast board %lx flags %lx hashtab %lx\n",(ULONG)boardbase,(ULONG)flags,(ULONG)hash_tab));
|
||||||
|
|
||||||
|
enc624j6l_bc_mc_filter(boardbase, flags, hash_tab );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
@@ -460,9 +617,7 @@ void myhw_ControlInterrupts( DEVBASEP )
|
|||||||
|
|
||||||
ObtainSemaphore( &hwd->hwd_Sem ); /* redundant here: server is a single task -> but it looks good :-) */
|
ObtainSemaphore( &hwd->hwd_Sem ); /* redundant here: server is a single task -> but it looks good :-) */
|
||||||
|
|
||||||
hwd->hwd_act_boards[0] = HW_MAGIC_WORD;
|
flag = 0;
|
||||||
|
|
||||||
flag = 1;
|
|
||||||
for( i=0 ; i < db->db_NBoards ; i++ )
|
for( i=0 ; i < db->db_NBoards ; i++ )
|
||||||
{
|
{
|
||||||
if( db->db_Units[i].duh_online )
|
if( db->db_Units[i].duh_online )
|
||||||
@@ -476,7 +631,7 @@ void myhw_ControlInterrupts( DEVBASEP )
|
|||||||
hwd->hwd_act_boards[flag+2] = (APTR)hwd->hwd_IntSig; /* append sigbit */
|
hwd->hwd_act_boards[flag+2] = (APTR)hwd->hwd_IntSig; /* append sigbit */
|
||||||
hwd->hwd_act_boards[flag+3] = (APTR)db->db_SysBase; /* append ExecBase *((APTR*)0x4); */
|
hwd->hwd_act_boards[flag+3] = (APTR)db->db_SysBase; /* append ExecBase *((APTR*)0x4); */
|
||||||
|
|
||||||
if( flag>1 ) /* determine on/off switch */
|
if( flag ) /* determine on/off switch */
|
||||||
{
|
{
|
||||||
/* at least 1 board is online */
|
/* at least 1 board is online */
|
||||||
if( hwd->hwd_Interrupt.is_Data )
|
if( hwd->hwd_Interrupt.is_Data )
|
||||||
@@ -496,7 +651,7 @@ void myhw_ControlInterrupts( DEVBASEP )
|
|||||||
hwd->hwd_Interrupt.is_Code = (void(*)())enc624j6l_IntServer_List;
|
hwd->hwd_Interrupt.is_Code = (void(*)())enc624j6l_IntServer_List;
|
||||||
hwd->hwd_Interrupt.is_Data = &hwd->hwd_act_boards[0];
|
hwd->hwd_Interrupt.is_Data = &hwd->hwd_act_boards[0];
|
||||||
hwd->hwd_Interrupt.is_Node.ln_Type = NT_INTERRUPT;
|
hwd->hwd_Interrupt.is_Node.ln_Type = NT_INTERRUPT;
|
||||||
hwd->hwd_Interrupt.is_Node.ln_Pri = 51;
|
hwd->hwd_Interrupt.is_Node.ln_Pri = 126; /* 51; */
|
||||||
hwd->hwd_Interrupt.is_Node.ln_Name = (char*)intname;
|
hwd->hwd_Interrupt.is_Node.ln_Name = (char*)intname;
|
||||||
AddIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
|
AddIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1,6 +1,7 @@
|
|||||||
incdir include:
|
incdir include:
|
||||||
ifnd _LVOSupervisor
|
ifnd _LVOSupervisor
|
||||||
include exec/exec_lib.i
|
include lvo/exec_lib.i
|
||||||
|
;include exec/exec_lib.i
|
||||||
endc
|
endc
|
||||||
include exec/execbase.i
|
include exec/execbase.i
|
||||||
|
|
||||||
@@ -13,12 +14,19 @@ _LVORawIOInit equ -$1f8
|
|||||||
_LVORawMayGetChar equ -$1fe
|
_LVORawMayGetChar equ -$1fe
|
||||||
endc
|
endc
|
||||||
|
|
||||||
XDEF _KPrintF
|
; XDEF _KPrintF
|
||||||
|
XDEF _KPrintFa0a1
|
||||||
|
|
||||||
|
;_KPrintF:
|
||||||
|
rts
|
||||||
|
move.l 4(sp),a0
|
||||||
|
lea 8(sp),a1
|
||||||
|
; fall through
|
||||||
|
|
||||||
;A0 = format
|
;A0 = format
|
||||||
;A1 = arguments
|
;A1 = arguments
|
||||||
_KPrintF:
|
_KPrintFa0a1:
|
||||||
ifd DEBUG
|
; ifd DEBUG
|
||||||
|
|
||||||
movem.l d0-d2/a0-a3/a6,-(sp)
|
movem.l d0-d2/a0-a3/a6,-(sp)
|
||||||
|
|
||||||
@@ -37,7 +45,7 @@ _KPrintF:
|
|||||||
jsr _LVORawPutChar(a6) ; move.b d0,(a3)+
|
jsr _LVORawPutChar(a6) ; move.b d0,(a3)+
|
||||||
movem.l (sp)+,d0/d1/a0/a1/a6
|
movem.l (sp)+,d0/d1/a0/a1/a6
|
||||||
|
|
||||||
endc ;DEBUG
|
; endc ;DEBUG
|
||||||
|
|
||||||
rts
|
rts
|
||||||
|
|
||||||
|
|||||||
+205
-73
@@ -4,7 +4,6 @@
|
|||||||
/** SANA-II extension for access to Ethernet PHY registers over MII interface **/
|
/** SANA-II extension for access to Ethernet PHY registers over MII interface **/
|
||||||
/** **/
|
/** **/
|
||||||
/** Copyright (c) 2019, Henryk Richter, Timm S. Müller **/
|
/** Copyright (c) 2019, Henryk Richter, Timm S. Müller **/
|
||||||
/** All rights reserved. **/
|
|
||||||
/** **/
|
/** **/
|
||||||
/** Redistribution and use in source and binary forms, with or without **/
|
/** Redistribution and use in source and binary forms, with or without **/
|
||||||
/** modification, are permitted provided that the following conditions are met: **/
|
/** modification, are permitted provided that the following conditions are met: **/
|
||||||
@@ -16,9 +15,6 @@
|
|||||||
/** 3. All advertising materials mentioning features or use of this software **/
|
/** 3. All advertising materials mentioning features or use of this software **/
|
||||||
/** must display the following acknowledgement: **/
|
/** must display the following acknowledgement: **/
|
||||||
/** This product includes software developed by Henryk Richter. **/
|
/** This product includes software developed by Henryk Richter. **/
|
||||||
/** 4. Neither the name of the Henryk Richter nor the **/
|
|
||||||
/** names of its contributors may be used to endorse or promote products **/
|
|
||||||
/** derived from this software without specific prior written permission. **/
|
|
||||||
/** **/
|
/** **/
|
||||||
/** THIS SOFTWARE IS PROVIDED BY Henryk Richter ''AS IS'' AND ANY **/
|
/** THIS SOFTWARE IS PROVIDED BY Henryk Richter ''AS IS'' AND ANY **/
|
||||||
/** EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED **/
|
/** EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED **/
|
||||||
@@ -32,15 +28,22 @@
|
|||||||
/** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/
|
/** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/
|
||||||
/** **/
|
/** **/
|
||||||
/*******************************************************************************************/
|
/*******************************************************************************************/
|
||||||
|
/** Acknowledgements: **/
|
||||||
|
/** text and definitions in "media" table and "miitool.h" file originate from mii-tool.c **/
|
||||||
|
/** written/copyright 1997-2000 by Donald Becker **/
|
||||||
|
/*******************************************************************************************/
|
||||||
/*
|
/*
|
||||||
Notes:
|
Notes:
|
||||||
- make sure you have an up-to-date devices/sana2devqueryext.h
|
- make sure you have an up-to-date devices/sana2devqueryext.h
|
||||||
- make sure you have devices/newstyle.h
|
- make sure you have devices/newstyle.h
|
||||||
- compilation
|
- compilation
|
||||||
sc miitool.c link
|
sc miitool.c link INCLUDEDIR=sc:netinclude
|
||||||
|
gcc miitool.c -Igg:netinclude -o miitool
|
||||||
|
- if you don`t have the Roadshow SDK installed, just comment "RSHOW" out to build
|
||||||
|
without auto-detection code
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#define RSHOW
|
||||||
|
|
||||||
#include <proto/exec.h>
|
#include <proto/exec.h>
|
||||||
#include <proto/dos.h>
|
#include <proto/dos.h>
|
||||||
@@ -49,8 +52,17 @@
|
|||||||
#include <devices/sana2.h>
|
#include <devices/sana2.h>
|
||||||
#include <devices/sana2devqueryext.h>
|
#include <devices/sana2devqueryext.h>
|
||||||
#include "miitool.h"
|
#include "miitool.h"
|
||||||
|
#ifdef RSHOW
|
||||||
|
#include <libraries/bsdsocket.h>
|
||||||
|
#include <proto/bsdsocket.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __GNUC__
|
||||||
|
struct UtilityBase *UtilityBase;
|
||||||
|
static USHORT Utility_MY = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
#define OPT_TEMPLATE "DEVICE=DEV/K,UNIT/K/N,VERBOSE=V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG=RESTART/S,RESET/S,VERYVERBOSE=VV/S"
|
#define OPT_TEMPLATE "DEVICE=DEV/K,UNIT/K/N,VERBOSE=V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG=RESTART/S,RESET/S,VERYVERBOSE=VV/S"
|
||||||
const char opt_template[] = OPT_TEMPLATE;
|
const char opt_template[] = OPT_TEMPLATE;
|
||||||
struct progopts {
|
struct progopts {
|
||||||
@@ -70,12 +82,17 @@ struct prgdata {
|
|||||||
struct Device *sana2dev;
|
struct Device *sana2dev;
|
||||||
UBYTE devvalid;
|
UBYTE devvalid;
|
||||||
struct progopts opts;
|
struct progopts opts;
|
||||||
|
BYTE *auto_devname; /* device name, if auto-detected */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
void end_prog( struct prgdata *prg )
|
void end_prog( struct prgdata *prg )
|
||||||
{
|
{
|
||||||
|
if( prg->auto_devname )
|
||||||
|
FreeVec( prg->auto_devname );
|
||||||
|
|
||||||
if( prg->sana2devio )
|
if( prg->sana2devio )
|
||||||
{
|
{
|
||||||
if( prg->devvalid )
|
if( prg->devvalid )
|
||||||
@@ -84,6 +101,16 @@ void end_prog( struct prgdata *prg )
|
|||||||
}
|
}
|
||||||
if( prg->sana2devport )
|
if( prg->sana2devport )
|
||||||
DeleteMsgPort( prg->sana2devport );
|
DeleteMsgPort( prg->sana2devport );
|
||||||
|
|
||||||
|
#ifdef __GNUC__
|
||||||
|
if( (UtilityBase) && (Utility_MY) )
|
||||||
|
{
|
||||||
|
CloseLibrary( (struct Library*)UtilityBase );
|
||||||
|
Utility_MY = 0;
|
||||||
|
UtilityBase = NULL;
|
||||||
|
}
|
||||||
|
#endif /* __GNUC__ */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@@ -105,6 +132,13 @@ LONG start_prog( struct prgdata *prg )
|
|||||||
if( !prg->sana2devio )
|
if( !prg->sana2devio )
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
|
#ifdef __GNUC__
|
||||||
|
if( !UtilityBase )
|
||||||
|
{
|
||||||
|
UtilityBase = (struct UtilityBase*)OpenLibrary("utility.library",37);
|
||||||
|
Utility_MY = 1;
|
||||||
|
}
|
||||||
|
#endif /* __GNUC__ */
|
||||||
return 1;
|
return 1;
|
||||||
err:
|
err:
|
||||||
end_prog( prg );
|
end_prog( prg );
|
||||||
@@ -189,36 +223,37 @@ const struct {
|
|||||||
BYTE *name;
|
BYTE *name;
|
||||||
UWORD namelen;
|
UWORD namelen;
|
||||||
UWORD value;
|
UWORD value;
|
||||||
} media[] = {
|
} mediatypes[] = {
|
||||||
/* The order through 100baseT4 matches bits in the BMSR */
|
/* these are kept in this order for the dump loop decision about best mode */
|
||||||
{ "10baseT-HD", 10,MII_AN_10BASET_HD },
|
{ "10baseT-HD", 10,MII_AN_10BASET_HD },
|
||||||
{ "10baseT-FD", 10,MII_AN_10BASET_FD },
|
{ "10baseT-FD", 10,MII_AN_10BASET_FD },
|
||||||
{ "100baseTx-HD", 12,MII_AN_100BASETX_HD },
|
{ "100baseTx-HD", 12,MII_AN_100BASETX_HD },
|
||||||
{ "100baseTx-FD", 12,MII_AN_100BASETX_FD },
|
{ "100baseTx-FD", 12,MII_AN_100BASETX_FD },
|
||||||
{ "100baseT4", 9,MII_AN_100BASET4 },
|
{ "100baseT4", 9,MII_AN_100BASET4 },
|
||||||
|
/* generic mode names where only the speed matters */
|
||||||
{ "100baseTx", 9,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
|
{ "100baseTx", 9,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
|
||||||
{ "10baseT", 7,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
|
{ "10baseT", 7,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
|
||||||
{ "100bTx", 6,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
|
{ "100bTx", 6,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
|
||||||
{ "10bT", 4,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
|
{ "10bT", 4,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
|
||||||
};
|
};
|
||||||
#define NMEDIA (sizeof(media)/sizeof(media[0]))
|
#define NMEDIA (sizeof(mediatypes)/sizeof(mediatypes[0]))
|
||||||
|
|
||||||
void dump_mii_media( USHORT par, BOOL bestonly )
|
|
||||||
|
void dump_mii_media( USHORT parms, BOOL bestonly )
|
||||||
{
|
{
|
||||||
LONG i;
|
LONG i;
|
||||||
|
|
||||||
par >>= 5; /* get upper bits */
|
for( i=9 ; i >= 5 ; i-- )
|
||||||
for( i=4 ; i >= 0 ; i-- )
|
|
||||||
{
|
{
|
||||||
if( par & (1<<i) )
|
if( parms & (1<<i) )
|
||||||
{
|
{
|
||||||
Printf(" ");
|
Printf(" %s",(ULONG)mediatypes[i-5].name);
|
||||||
Printf("%s",(ULONG)media[i].name);
|
|
||||||
if( bestonly )
|
if( bestonly )
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if( par & (1<<5) )
|
|
||||||
|
if( parms & (1<<10) )
|
||||||
Printf(" flow-control");
|
Printf(" flow-control");
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -234,13 +269,13 @@ LONG parse_speedduplex( BYTE *parameters )
|
|||||||
while( *s != 0 )
|
while( *s != 0 )
|
||||||
{
|
{
|
||||||
for( i=0 ; i < NMEDIA ; i++ )
|
for( i=0 ; i < NMEDIA ; i++ )
|
||||||
if( Strnicmp( media[i].name, s, media[i].namelen ) == 0 )
|
if( Strnicmp( mediatypes[i].name, s, mediatypes[i].namelen ) == 0 )
|
||||||
break;
|
break;
|
||||||
if( i==NMEDIA )
|
if( i==NMEDIA )
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
s += media[i].namelen;
|
s += mediatypes[i].namelen;
|
||||||
res |= media[i].value;
|
res |= mediatypes[i].value;
|
||||||
|
|
||||||
/* skip " " and/or "," */
|
/* skip " " and/or "," */
|
||||||
while( *s != 0 )
|
while( *s != 0 )
|
||||||
@@ -254,26 +289,26 @@ LONG parse_speedduplex( BYTE *parameters )
|
|||||||
|
|
||||||
return res;
|
return res;
|
||||||
err:
|
err:
|
||||||
Printf("Invalid media specification %s\n",parameters);
|
Printf("Invalid media specification %s\n",(ULONG)parameters);
|
||||||
Printf("Valid Arguments:\n");
|
Printf("Valid Arguments:\n");
|
||||||
for( i=0 ; i < NMEDIA ; i++ )
|
for( i=0 ; i < NMEDIA ; i++ )
|
||||||
Printf("%s\n",media[i].name);
|
Printf("%s\n",(ULONG)mediatypes[i].name);
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
note: this code assumes that "mii" has the register contents in natural
|
note: this code assumes that "mii" has the register contents in network
|
||||||
byte ordering. Also, the registers themselves shall be consecutive
|
byte ordering. Also, the registers themselves shall be consecutive
|
||||||
in memory.
|
in memory.
|
||||||
*/
|
*/
|
||||||
int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
||||||
{
|
{
|
||||||
USHORT bmcr,bmsr,advert,curlink;
|
USHORT bmcr,bmsr,selfad,curlink;
|
||||||
LONG i;
|
LONG i;
|
||||||
|
|
||||||
bmcr = mii[MII_BMCR].Content;
|
bmcr = mii[MII_BMCR].Content;
|
||||||
bmsr = mii[MII_BMSR].Content;
|
bmsr = mii[MII_BMSR].Content;
|
||||||
advert = mii[MII_ANAR].Content;
|
selfad = mii[MII_ANAR].Content;
|
||||||
curlink = mii[MII_ANLPAR].Content;
|
curlink = mii[MII_ANLPAR].Content;
|
||||||
|
|
||||||
if( bmcr == 0xffff )
|
if( bmcr == 0xffff )
|
||||||
@@ -286,19 +321,19 @@ int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
|||||||
{
|
{
|
||||||
if( bmsr & MII_BMSR_AN_COMPLETE)
|
if( bmsr & MII_BMSR_AN_COMPLETE)
|
||||||
{
|
{
|
||||||
if( advert & curlink )
|
if( selfad & curlink )
|
||||||
{
|
{
|
||||||
if( curlink & MII_AN_ACK )
|
/* if( curlink & MII_AN_ACK ) */
|
||||||
Printf("negotiated ");
|
Printf("negotiated ");
|
||||||
else Printf("no autonegotiation,");
|
/* else Printf("no autonegotiation,"); */
|
||||||
dump_mii_media( advert & curlink, 1 );
|
dump_mii_media( selfad & curlink, 1 );
|
||||||
Printf(", ");
|
Printf(", ");
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
Printf("autonegotiation failed, ");
|
Printf("autonegotiation failed, ");
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
}
|
||||||
else
|
else
|
||||||
if (bmcr & MII_BMCR_RESTART)
|
if (bmcr & MII_BMCR_RESTART)
|
||||||
{
|
{
|
||||||
@@ -308,8 +343,8 @@ int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
|||||||
else
|
else
|
||||||
{
|
{
|
||||||
Printf("%s Mbit, %s duplex, ",
|
Printf("%s Mbit, %s duplex, ",
|
||||||
(bmcr & MII_BMCR_100MBIT) ? "100" : "10",
|
(bmcr & MII_BMCR_100MBIT) ? (ULONG)"100" : (ULONG)"10",
|
||||||
(bmcr & MII_BMCR_DUPLEX) ? "full" : "half" );
|
(bmcr & MII_BMCR_DUPLEX) ? (ULONG)"full" : (ULONG)"half" );
|
||||||
}
|
}
|
||||||
if( bmsr & MII_BMSR_LINK_VALID )
|
if( bmsr & MII_BMSR_LINK_VALID )
|
||||||
Printf("link ok");
|
Printf("link ok");
|
||||||
@@ -353,8 +388,8 @@ int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
|||||||
Printf("autonegotiation enabled\n");
|
Printf("autonegotiation enabled\n");
|
||||||
else
|
else
|
||||||
Printf("%s Mbit, %s duplex\n",
|
Printf("%s Mbit, %s duplex\n",
|
||||||
(bmcr & MII_BMCR_100MBIT) ? "100" : "10",
|
(bmcr & MII_BMCR_100MBIT) ? (ULONG)"100" : (ULONG)"10",
|
||||||
(bmcr & MII_BMCR_DUPLEX) ? "full" : "half");
|
(bmcr & MII_BMCR_DUPLEX) ? (ULONG)"full" : (ULONG)"half");
|
||||||
Printf(" basic status: ");
|
Printf(" basic status: ");
|
||||||
if( bmsr & MII_BMSR_AN_COMPLETE )
|
if( bmsr & MII_BMSR_AN_COMPLETE )
|
||||||
Printf("autonegotiation complete, ");
|
Printf("autonegotiation complete, ");
|
||||||
@@ -366,7 +401,7 @@ int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
|
|||||||
Printf("\n capabilities:");
|
Printf("\n capabilities:");
|
||||||
dump_mii_media( bmsr >> 6, 0 );
|
dump_mii_media( bmsr >> 6, 0 );
|
||||||
Printf("\n advertising: ");
|
Printf("\n advertising: ");
|
||||||
dump_mii_media( advert, 0 );
|
dump_mii_media( selfad, 0 );
|
||||||
if( curlink & MII_AN_ABILITY_MASK )
|
if( curlink & MII_AN_ABILITY_MASK )
|
||||||
{
|
{
|
||||||
Printf("\n link partner:");
|
Printf("\n link partner:");
|
||||||
@@ -438,6 +473,111 @@ LONG write_mii( struct prgdata *prg, struct S2DevQueryMIIParam *mii, LONG num )
|
|||||||
return parm_mii.Actual;
|
return parm_mii.Actual;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef RSHOW
|
||||||
|
/* return string length without closing 0 */
|
||||||
|
LONG myStrLen( BYTE *str )
|
||||||
|
{
|
||||||
|
LONG ret = 0;
|
||||||
|
|
||||||
|
if( str )
|
||||||
|
{
|
||||||
|
while( *str++ )
|
||||||
|
ret++;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
/* copy string, append 0 */
|
||||||
|
void myStrNCpy( BYTE *dst, BYTE*src, LONG bytes )
|
||||||
|
{
|
||||||
|
if( !dst )
|
||||||
|
return;
|
||||||
|
|
||||||
|
if( src )
|
||||||
|
{
|
||||||
|
while( (bytes--) && (*src != 0) )
|
||||||
|
{
|
||||||
|
*dst++ = *src++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*dst = 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* find active interface and its device in RoadShow (optional) */
|
||||||
|
/* "which" index of Ethernet adapter 0,1,2,... */
|
||||||
|
/* "unit" is the output unit */
|
||||||
|
BYTE *find_active_interface(LONG which, LONG *unit )
|
||||||
|
{
|
||||||
|
struct Library *SocketBase;
|
||||||
|
BYTE *ret = NULL;
|
||||||
|
struct List * interface_list = NULL;
|
||||||
|
struct Node *n;
|
||||||
|
BYTE *dev = NULL;
|
||||||
|
LONG hw = -1;
|
||||||
|
|
||||||
|
SocketBase = OpenLibrary("bsdsocket.library",4);
|
||||||
|
if( !SocketBase )
|
||||||
|
{
|
||||||
|
Printf("Cannot open bsdsocket.library version 4 for device auto-detection\n");
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
LONG have_iface = 0;
|
||||||
|
|
||||||
|
if( !(SocketBaseTags(SBTM_GETREF(SBTC_HAVE_INTERFACE_API), &have_iface, TAG_DONE) == 0)
|
||||||
|
||(!have_iface) )
|
||||||
|
{
|
||||||
|
Printf("RoadShow-style interface API not available in IP stack\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
interface_list = ObtainInterfaceList();
|
||||||
|
if( !interface_list )
|
||||||
|
{
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
for( n=interface_list->lh_Head ; n->ln_Succ != NULL ; n=n->ln_Succ )
|
||||||
|
{
|
||||||
|
/* Printf("Interface %s\n",n->ln_Name); */
|
||||||
|
/* find Ethernet interface */
|
||||||
|
if(!QueryInterfaceTags( n->ln_Name, IFQ_HardwareType, &hw,
|
||||||
|
IFQ_DeviceName, &dev,
|
||||||
|
IFQ_DeviceUnit, unit ) )
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* Printf("device %s hwtype %ld\n",dev,hw); */
|
||||||
|
|
||||||
|
if( hw == S2WireType_Ethernet )
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if( hw == S2WireType_Ethernet )
|
||||||
|
{
|
||||||
|
if( dev )
|
||||||
|
{
|
||||||
|
ret = AllocVec( myStrLen( dev ), 0 );
|
||||||
|
if( ret )
|
||||||
|
myStrNCpy( ret, dev, myStrLen(dev) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
while(0);
|
||||||
|
|
||||||
|
if( interface_list )
|
||||||
|
ReleaseInterfaceList(interface_list);
|
||||||
|
|
||||||
|
CloseLibrary(SocketBase);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/* 8 basic registers, we poll 16 out of curiosity */
|
/* 8 basic registers, we poll 16 out of curiosity */
|
||||||
#define MII_REGNUM 16
|
#define MII_REGNUM 16
|
||||||
/* two spare registers for write mode */
|
/* two spare registers for write mode */
|
||||||
@@ -468,17 +608,34 @@ int main(int argc, char **argv)
|
|||||||
return res;
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
unit = (prg->opts.unit) ? *prg->opts.unit : 0;
|
||||||
|
|
||||||
if( !prg->opts.devname )
|
if( !prg->opts.devname )
|
||||||
{
|
{
|
||||||
|
#ifdef RSHOW
|
||||||
|
LONG _unit;
|
||||||
|
prg->auto_devname = find_active_interface( 0, &_unit );
|
||||||
|
if( prg->auto_devname )
|
||||||
|
{
|
||||||
|
unit = _unit;
|
||||||
|
name = prg->auto_devname;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Printf("cannot auto-determine device, please use DEVICE=... as argument\n");
|
||||||
|
end_prog(prg);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
#else
|
||||||
name = "enc624j6net.device";
|
name = "enc624j6net.device";
|
||||||
Printf("TODO: auto-detect, now trying default %s\n",name);
|
Printf("device auto-detect not compiled in, now trying default %s\n",name);
|
||||||
|
#endif
|
||||||
/* end_prog(prg);
|
/* end_prog(prg);
|
||||||
return res; */
|
return res; */
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
name = prg->opts.devname;
|
name = prg->opts.devname;
|
||||||
|
|
||||||
unit = (prg->opts.unit) ? *prg->opts.unit : 0;
|
|
||||||
if( prg->opts.vverbose )
|
if( prg->opts.vverbose )
|
||||||
prg->opts.verbose = 2;
|
prg->opts.verbose = 2;
|
||||||
else
|
else
|
||||||
@@ -524,7 +681,7 @@ int main(int argc, char **argv)
|
|||||||
parm_productname.Data = productname;
|
parm_productname.Data = productname;
|
||||||
parm_productname.Length = sizeof(productname);
|
parm_productname.Length = sizeof(productname);
|
||||||
parm_productname.Actual = 0;
|
parm_productname.Actual = 0;
|
||||||
#if 1
|
|
||||||
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
|
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
|
||||||
tags[i++].ti_Data = (ULONG) &parm_vendorname;
|
tags[i++].ti_Data = (ULONG) &parm_vendorname;
|
||||||
tags[i ].ti_Tag = S2_DevQueryExtProductName;
|
tags[i ].ti_Tag = S2_DevQueryExtProductName;
|
||||||
@@ -542,55 +699,28 @@ int main(int argc, char **argv)
|
|||||||
parm_mii.Actual = query_mii( prg, mii, 0, 15 );
|
parm_mii.Actual = query_mii( prg, mii, 0, 15 );
|
||||||
if( parm_mii.Actual )
|
if( parm_mii.Actual )
|
||||||
{
|
{
|
||||||
/* read BMSR twice */
|
/* read BMSR a second time */
|
||||||
query_mii( prg, mii+MII_BMSR, MII_BMSR, MII_BMSR );
|
query_mii( prg, mii+MII_BMSR, MII_BMSR, MII_BMSR );
|
||||||
res = RETURN_OK;
|
res = RETURN_OK;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
{
|
||||||
|
Printf("Sana2DeviceQueryExtension for MII access not present\n");
|
||||||
res = RETURN_WARN;
|
res = RETURN_WARN;
|
||||||
#else
|
}
|
||||||
/* MII specific */
|
|
||||||
parm_mii.Data = (APTR)mii;
|
|
||||||
parm_mii.Length = sizeof(mii);
|
|
||||||
parm_mii.Actual = 0;
|
|
||||||
|
|
||||||
for( i=0 ; i < 16 ; i++ ) /* MII standard register set: 8 */
|
|
||||||
{
|
|
||||||
mii[i].ID = i; /* mii[i].Content = 0; */
|
|
||||||
}
|
|
||||||
mii[16].ID = MII_BMSR; /* read BMSR twice */
|
|
||||||
|
|
||||||
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
|
|
||||||
tags[i++].ti_Data = (ULONG) &parm_vendorname;
|
|
||||||
tags[i ].ti_Tag = S2_DevQueryExtProductName;
|
|
||||||
tags[i++].ti_Data = (ULONG) &parm_productname;
|
|
||||||
tags[i ].ti_Tag = S2_DevQueryExtGetMII;
|
|
||||||
tags[i++].ti_Data = (ULONG) &parm_mii;
|
|
||||||
tags[i ].ti_Tag = TAG_DONE;
|
|
||||||
|
|
||||||
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
|
|
||||||
prg->sana2devio->ios2_Data = tags;
|
|
||||||
prg->sana2devio->ios2_DataLength = sizeof tags;
|
|
||||||
|
|
||||||
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
|
|
||||||
res = RETURN_WARN;
|
|
||||||
else res = RETURN_OK;
|
|
||||||
|
|
||||||
mii[MII_BMSR].Content = mii[16].Content; /* read BMSR twice */
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Printf("Device: %s\n",name);
|
Printf("Device: %s\n",(ULONG)name);
|
||||||
/* general info */
|
/* general info */
|
||||||
if( parm_vendorname.Actual != 0 )
|
if( parm_vendorname.Actual != 0 )
|
||||||
{
|
{
|
||||||
vendorname[parm_vendorname.Actual-1] = 0;
|
vendorname[parm_vendorname.Actual-1] = 0;
|
||||||
Printf("Vendor: %s\n",vendorname);
|
Printf("Vendor: %s\n",(ULONG)vendorname);
|
||||||
}
|
}
|
||||||
if( parm_productname.Actual != 0 )
|
if( parm_productname.Actual != 0 )
|
||||||
{
|
{
|
||||||
productname[parm_productname.Actual-1] = 0;
|
productname[parm_productname.Actual-1] = 0;
|
||||||
Printf("Product: %s\n",productname);
|
Printf("Product: %s\n",(ULONG)productname);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* after query, see what we've got */
|
/* after query, see what we've got */
|
||||||
@@ -603,6 +733,7 @@ int main(int argc, char **argv)
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
|
/* command or query ? */
|
||||||
if( !(prg->opts.renegotiate) && !(prg->opts.reset)
|
if( !(prg->opts.renegotiate) && !(prg->opts.reset)
|
||||||
&& !(prg->opts.advertise) && !(prg->opts.force)
|
&& !(prg->opts.advertise) && !(prg->opts.force)
|
||||||
)
|
)
|
||||||
@@ -659,3 +790,4 @@ int main(int argc, char **argv)
|
|||||||
end_prog(prg);
|
end_prog(prg);
|
||||||
return res;
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -66,6 +66,51 @@ struct S2DevQueryExtParam
|
|||||||
/* Current physical link speed, see definitions below: */
|
/* Current physical link speed, see definitions below: */
|
||||||
#define S2_DevQueryExtLinkSpeed (S2_DevQueryExtTagBase + 4)
|
#define S2_DevQueryExtLinkSpeed (S2_DevQueryExtTagBase + 4)
|
||||||
|
|
||||||
|
/* proposal added by Henryk Richter: access to MII */
|
||||||
|
/* MII is the standardized ethernet interface to the
|
||||||
|
PHY registers. It allows to read and modify autonegotiation
|
||||||
|
settings and status, as well as manual reconfiguration of
|
||||||
|
link parameters. In order to ease the burden on the
|
||||||
|
SANA-II driver, this interface is transparent in the sense
|
||||||
|
that no processing of MII registers is necessary.
|
||||||
|
|
||||||
|
Please note that MII read/write is slow. Use with discretion.
|
||||||
|
|
||||||
|
The format of the Data APTR is per entry as follows:
|
||||||
|
UWORD ID
|
||||||
|
UWORD Content
|
||||||
|
|
||||||
|
S2_DevQueryExtGetMII
|
||||||
|
Please pass a writable Data array of Length=2*NumIDs to the call and
|
||||||
|
initialize the IDs you are interested in. The driver will initialize
|
||||||
|
the Content of the IDs it knows about. Should a requested ID be
|
||||||
|
unsupported by the driver or underlying chipset, the driver will
|
||||||
|
overwrite the respective IDs with S2_DEVQUERYEXT_MII_INVALID and
|
||||||
|
clear the associated Content field.
|
||||||
|
In case of fatal error, the "Actual" field of S2DevQueryExtParam
|
||||||
|
will be 0. Otherwise, the last successfully updated location + 2
|
||||||
|
will be returned.
|
||||||
|
|
||||||
|
S2_DevQueryExtSetMII
|
||||||
|
Please pass a Data array of Length=2*NumIDs to the call and initialize
|
||||||
|
the IDs to write along with their content. The driver will write the
|
||||||
|
MII registers corresponding with the IDs in the given order.
|
||||||
|
In case of fatal error, the "Actual" field of S2DevQueryExtParam
|
||||||
|
will be 0. Otherwise, the last successfully updated location + 2
|
||||||
|
will be returned.
|
||||||
|
|
||||||
|
*/
|
||||||
|
#define S2_DevQueryExtGetMII (S2_DevQueryExtTagBase + 0x20)
|
||||||
|
#define S2_DevQueryExtSetMII (S2_DevQueryExtTagBase + 0x21)
|
||||||
|
|
||||||
|
struct S2DevQueryMIIParam
|
||||||
|
{
|
||||||
|
UWORD ID;
|
||||||
|
UWORD Content;
|
||||||
|
};
|
||||||
|
#define S2_DEVQUERYEXT_MII_INVALID 0xfe
|
||||||
|
|
||||||
|
|
||||||
#define S2_DEVQUERYEXT_LINK_UNDEFINED 0xffffffff
|
#define S2_DEVQUERYEXT_LINK_UNDEFINED 0xffffffff
|
||||||
#define S2_DEVQUERYEXT_LINK_DOWN 0
|
#define S2_DEVQUERYEXT_LINK_DOWN 0
|
||||||
#define S2_DEVQUERYEXT_LINK_UP 1
|
#define S2_DEVQUERYEXT_LINK_UP 1
|
||||||
|
|||||||
@@ -37,10 +37,16 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq );
|
|||||||
|
|
||||||
/* tunables: number of one-call read and write requests */
|
/* tunables: number of one-call read and write requests */
|
||||||
/* this limits the number of processed write requests per run when enabled */
|
/* this limits the number of processed write requests per run when enabled */
|
||||||
#define ONE_WRITE_REQ 2
|
#define ONE_WRITE_REQ 1
|
||||||
/* this limits the number of processed read requests per run when enabled */
|
/* this limits the number of processed read requests per run when enabled */
|
||||||
#define ONE_READ_REQ 2
|
#define ONE_READ_REQ 2
|
||||||
|
|
||||||
|
/* heavy debug on read/write */
|
||||||
|
#define D2(x)
|
||||||
|
#define D4(x)
|
||||||
|
/* #define D2(x) D(x) */
|
||||||
|
/* #define D4(x) D(x) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* (avoid external link libraries) this call is not time critical */
|
/* (avoid external link libraries) this call is not time critical */
|
||||||
@@ -384,6 +390,15 @@ static LONG server_changeMulticast( DEVBASEP, ULONG unit, struct IOSana2Req *ior
|
|||||||
COPYMAC( entry->mce_start, ioreq->ios2_SrcAddr );
|
COPYMAC( entry->mce_start, ioreq->ios2_SrcAddr );
|
||||||
COPYMAC( entry->mce_stop, ioreq->ios2_SrcAddr );
|
COPYMAC( entry->mce_stop, ioreq->ios2_SrcAddr );
|
||||||
|
|
||||||
|
D(("ADD Multicast MAC %02lx%02lx%02lx%02lx%02lx%02lx - %02lx%02lx%02lx%02lx%02lx%02lx\n",\
|
||||||
|
(ULONG)entry->mce_start[0],(ULONG)entry->mce_start[1],\
|
||||||
|
(ULONG)entry->mce_start[2],(ULONG)entry->mce_start[3],\
|
||||||
|
(ULONG)entry->mce_start[4],(ULONG)entry->mce_start[5],\
|
||||||
|
(ULONG)entry->mce_stop[0],(ULONG)entry->mce_stop[1],\
|
||||||
|
(ULONG)entry->mce_stop[2],(ULONG)entry->mce_stop[3],\
|
||||||
|
(ULONG)entry->mce_stop[4],(ULONG)entry->mce_stop[5] \
|
||||||
|
));
|
||||||
|
|
||||||
ADDTAIL( &db->db_svdat.sv_mclist, entry );
|
ADDTAIL( &db->db_svdat.sv_mclist, entry );
|
||||||
|
|
||||||
apply:
|
apply:
|
||||||
@@ -715,7 +730,7 @@ static LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
|||||||
UBYTE *header_ptr;
|
UBYTE *header_ptr;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
D(("write: type %08lx, size %ld\n",ioreq->ios2_PacketType,
|
D2(("write: type %08lx, size %ld\n",ioreq->ios2_PacketType,
|
||||||
ioreq->ios2_DataLength));
|
ioreq->ios2_DataLength));
|
||||||
|
|
||||||
frame = db->db_svdat.sv_frame;
|
frame = db->db_svdat.sv_frame;
|
||||||
@@ -765,13 +780,13 @@ static LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
|||||||
if( (*dbm->dbm_CopyFromBuffer32)(copy_ptr,ioreq->ios2_Data, ioreq->ios2_DataLength) )
|
if( (*dbm->dbm_CopyFromBuffer32)(copy_ptr,ioreq->ios2_Data, ioreq->ios2_DataLength) )
|
||||||
{
|
{
|
||||||
send:
|
send:
|
||||||
D(("+hw_send\n"));
|
D2(("+hw_send\n"));
|
||||||
#ifdef HW_DMA_TX
|
#ifdef HW_DMA_TX
|
||||||
ret = hw_send_frame(db, unit, copy_ptr, framesize, header_ptr ) ? SERR_OK:SERR_ERROR;
|
ret = hw_send_frame(db, unit, copy_ptr, framesize, header_ptr ) ? SERR_OK:SERR_ERROR;
|
||||||
#else
|
#else
|
||||||
ret = hw_send_frame(db, unit, frame, framesize ) ? SERR_OK : SERR_ERROR;
|
ret = hw_send_frame(db, unit, frame, framesize ) ? SERR_OK : SERR_ERROR;
|
||||||
#endif
|
#endif
|
||||||
D(("-hw_send\n"));
|
D2(("-hw_send\n"));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
@@ -892,14 +907,14 @@ static void server_read_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, U
|
|||||||
{
|
{
|
||||||
frame += 14; /* skip DST,SRC,Type */
|
frame += 14; /* skip DST,SRC,Type */
|
||||||
framesize -= 18; /* also remove CRC */
|
framesize -= 18; /* also remove CRC */
|
||||||
D(("plain mode: frame flags %ld\n",bcflag));
|
D4(("plain mode: frame flags %ld\n",bcflag));
|
||||||
}
|
}
|
||||||
ioreq->ios2_Req.io_Flags &= SANA2IOF_RAW; /* ignore all other flags */
|
ioreq->ios2_Req.io_Flags &= SANA2IOF_RAW; /* ignore all other flags */
|
||||||
ioreq->ios2_Req.io_Flags |= bcflag;
|
ioreq->ios2_Req.io_Flags |= bcflag;
|
||||||
ioreq->ios2_Req.io_Error = 0;
|
ioreq->ios2_Req.io_Error = 0;
|
||||||
ioreq->ios2_WireError = 0;
|
ioreq->ios2_WireError = 0;
|
||||||
|
|
||||||
D(("ReadFrm IO %lx, DBM %lx frm %lx frmsz %ld\n",(ULONG)ioreq,(ULONG)dbm,(ULONG)frame,framesize));
|
D4(("ReadFrm IO %lx, DBM %lx frm %lx frmsz %ld\n",(ULONG)ioreq,(ULONG)dbm,(ULONG)frame,framesize));
|
||||||
|
|
||||||
if( dbm->dbm_PacketFilter ) /* Filter Packets ? */
|
if( dbm->dbm_PacketFilter ) /* Filter Packets ? */
|
||||||
{
|
{
|
||||||
@@ -918,7 +933,7 @@ static void server_read_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, U
|
|||||||
ioreq->ios2_WireError = S2WERR_BUFF_ERROR;
|
ioreq->ios2_WireError = S2WERR_BUFF_ERROR;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
D(("Copied io_Error %ld\n",(LONG)ioreq->ios2_Req.io_Error));
|
D4(("Copied io_Error %ld\n",(LONG)ioreq->ios2_Req.io_Error));
|
||||||
|
|
||||||
Remove( (struct Node*)ioreq );
|
Remove( (struct Node*)ioreq );
|
||||||
svTermIO( db, ioreq );
|
svTermIO( db, ioreq );
|
||||||
@@ -946,7 +961,7 @@ static LONG server_readqueue( DEVBASEP, ULONG unit )
|
|||||||
/* TODO: devstats */
|
/* TODO: devstats */
|
||||||
frametype = *( (USHORT*)(frame+12) );
|
frametype = *( (USHORT*)(frame+12) );
|
||||||
|
|
||||||
D(("Have Frame size %ld type %ld\n",framesize,frametype));
|
D4(("Have Frame size %ld type %ld\n",framesize,frametype));
|
||||||
|
|
||||||
ObtainSemaphore( &db->db_Units[unit].du_Sem );
|
ObtainSemaphore( &db->db_Units[unit].du_Sem );
|
||||||
|
|
||||||
@@ -964,14 +979,14 @@ orphan:
|
|||||||
ioreq = (struct IOSana2Req *)GetHead( (struct List*)&db->db_Units[unit].du_ReadOrphans );
|
ioreq = (struct IOSana2Req *)GetHead( (struct List*)&db->db_Units[unit].du_ReadOrphans );
|
||||||
if( ioreq )
|
if( ioreq )
|
||||||
{
|
{
|
||||||
D(("Orphaned Frame\n"));
|
D4(("Orphaned Frame\n"));
|
||||||
|
|
||||||
ioreq->ios2_PacketType = frametype;
|
ioreq->ios2_PacketType = frametype;
|
||||||
server_read_frame( db, unit, ioreq, frame, framesize );
|
server_read_frame( db, unit, ioreq, frame, framesize );
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
D(("No ioreq for orphaned frame\n"));
|
D4(("No ioreq for orphaned frame\n"));
|
||||||
}
|
}
|
||||||
|
|
||||||
goto nextframe;
|
goto nextframe;
|
||||||
@@ -1005,7 +1020,7 @@ havetype:
|
|||||||
{
|
{
|
||||||
db->db_Units[unit].du_DevStats.Overruns++;
|
db->db_Units[unit].du_DevStats.Overruns++;
|
||||||
type->srt_Sana2PacketTypeStats.PacketsDropped++;
|
type->srt_Sana2PacketTypeStats.PacketsDropped++;
|
||||||
D(("No Reader for frame\n"));
|
D4(("No Reader for frame\n"));
|
||||||
goto orphan; /* does it help if we give the frame to the orphan list? */
|
goto orphan; /* does it help if we give the frame to the orphan list? */
|
||||||
}
|
}
|
||||||
nextframe:
|
nextframe:
|
||||||
@@ -1071,6 +1086,7 @@ VOID SAVEDS ServerTask(void)
|
|||||||
{
|
{
|
||||||
if( !action ) /* queues quiet ? -> sleep */
|
if( !action ) /* queues quiet ? -> sleep */
|
||||||
{
|
{
|
||||||
|
Disable();
|
||||||
i=0;BOARDLOOP( ( ; i < db->db_NBoards ; i++ ) )
|
i=0;BOARDLOOP( ( ; i < db->db_NBoards ; i++ ) )
|
||||||
{ /* housekeeping -> check for link change on idle, re-enable interrupts etc. */
|
{ /* housekeeping -> check for link change on idle, re-enable interrupts etc. */
|
||||||
hw_check_link_change(db,i);
|
hw_check_link_change(db,i);
|
||||||
@@ -1093,9 +1109,9 @@ VOID SAVEDS ServerTask(void)
|
|||||||
}
|
}
|
||||||
if( hw_recv_pending(db,i) )
|
if( hw_recv_pending(db,i) )
|
||||||
{
|
{
|
||||||
D(("Read on unit %ld start\n",i));
|
D4(("Read on unit %ld start\n",i));
|
||||||
server_readqueue( db, i );
|
server_readqueue( db, i );
|
||||||
D(("Read on unit %ld stop\n",i));
|
D4(("Read on unit %ld stop\n",i));
|
||||||
action = 1;
|
action = 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -46,7 +46,7 @@ ASMDEFS1 = -DHW_DMA_TX=1
|
|||||||
###############################################################################
|
###############################################################################
|
||||||
# debug = 1 will include string debugging for terminal/sushi/sashimi
|
# debug = 1 will include string debugging for terminal/sushi/sashimi
|
||||||
# not enabled yet in SAS/C makefile
|
# not enabled yet in SAS/C makefile
|
||||||
debug = 0
|
#debug = 0
|
||||||
|
|
||||||
###############################################################################
|
###############################################################################
|
||||||
# prefix for system includes (ASM)
|
# prefix for system includes (ASM)
|
||||||
@@ -127,7 +127,7 @@ CFLAGS = $(CFLAGS) INCLUDEDIR="" INCLUDEDIR=$(SUBDIR) $(DEFINES)
|
|||||||
# ASM based alternative to deviceheader.o would be romtag.o
|
# ASM based alternative to deviceheader.o would be romtag.o
|
||||||
|
|
||||||
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
|
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
|
||||||
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE)
|
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE) kprintf.o$(TYPE)
|
||||||
|
|
||||||
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
|
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
|
||||||
|
|
||||||
|
|||||||
@@ -9,9 +9,9 @@
|
|||||||
#define _INC_VERSION_H
|
#define _INC_VERSION_H
|
||||||
|
|
||||||
#define DEVICEVERSION 2
|
#define DEVICEVERSION 2
|
||||||
#define DEVICEREVISION 1
|
#define DEVICEREVISION 3
|
||||||
#define DEVICEEXTRA
|
#define DEVICEEXTRA
|
||||||
/* #define DEVICEEXTRA Beta */
|
/* #define DEVICEEXTRA Beta */
|
||||||
#define DEVICEDATE 21.02.2019
|
#define DEVICEDATE 04.04.2019
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@@ -69,7 +69,7 @@ entity LAN_IDE_CP is
|
|||||||
IDE_R : out STD_LOGIC;
|
IDE_R : out STD_LOGIC;
|
||||||
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
|
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
|
||||||
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
|
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
|
||||||
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
|
-- LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
|
||||||
LAN_RD : out STD_LOGIC;
|
LAN_RD : out STD_LOGIC;
|
||||||
LAN_CS : out STD_LOGIC;
|
LAN_CS : out STD_LOGIC;
|
||||||
LAN_WRH : out STD_LOGIC;
|
LAN_WRH : out STD_LOGIC;
|
||||||
@@ -424,7 +424,7 @@ begin
|
|||||||
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
|
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||||
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
|
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||||
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
|
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
|
||||||
LAN_CFG <= "0010"; -- "ZZZZ";
|
-- LAN_CFG <= "0010"; -- "ZZZZ";
|
||||||
|
|
||||||
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||||
CP_RD <= CP_RD_S when AS='0' else '1';
|
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||||
|
|||||||
+1395
-1395
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,724 @@
|
|||||||
|
----------------------------------------------------------------------------------
|
||||||
|
-- Company: a1k.org
|
||||||
|
-- Engineer: master matze and his padawan buggs
|
||||||
|
--
|
||||||
|
-- Create Date: 22:08:29 12/13/2016
|
||||||
|
-- Design Name: Z3 firmware for V2 card
|
||||||
|
-- Module Name: LAN_IDE_CP - Behavioral
|
||||||
|
-- Project Name:
|
||||||
|
-- Target Devices:
|
||||||
|
-- Tool versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
-- - check CP assignment on V2 boards (see: -- A(5 downto 2) when CP_ACCESS='1' else)
|
||||||
|
-- - disabled PSP config handling - unused on fixed V2
|
||||||
|
--
|
||||||
|
|
||||||
|
-- directory cleanup hint:
|
||||||
|
-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
|
||||||
|
----------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||||
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--use IEEE.NUMERIC_STD.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if instantiating
|
||||||
|
-- any Xilinx primitives in this code.
|
||||||
|
--library UNISIM;
|
||||||
|
--use UNISIM.VComponents.all;
|
||||||
|
|
||||||
|
entity LAN_IDE_CP is
|
||||||
|
Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
|
||||||
|
D : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||||
|
DQ : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||||
|
A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
|
||||||
|
OWN : out STD_LOGIC;
|
||||||
|
SLAVE : out STD_LOGIC;
|
||||||
|
CFOUT : out STD_LOGIC;
|
||||||
|
CFIN : in STD_LOGIC;
|
||||||
|
C1 : in STD_LOGIC;
|
||||||
|
C3 : in STD_LOGIC;
|
||||||
|
MTCR : in STD_LOGIC;
|
||||||
|
OVR : out STD_LOGIC;
|
||||||
|
BERR : in STD_LOGIC;
|
||||||
|
MTACK : out STD_LOGIC;
|
||||||
|
DS0 : in STD_LOGIC;
|
||||||
|
DTACK : out STD_LOGIC;
|
||||||
|
UDS : in STD_LOGIC;
|
||||||
|
LDS : in STD_LOGIC;
|
||||||
|
AS : in STD_LOGIC;
|
||||||
|
RW : in STD_LOGIC;
|
||||||
|
Z3 : in STD_LOGIC;
|
||||||
|
DS1 : in STD_LOGIC;
|
||||||
|
FCS : in STD_LOGIC;
|
||||||
|
RESET : in STD_LOGIC;
|
||||||
|
INT2_OUT : out STD_LOGIC;
|
||||||
|
INT6_OUT : out STD_LOGIC;
|
||||||
|
AUTOBOOT_OFF : in STD_LOGIC;
|
||||||
|
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
|
||||||
|
ROM_OE : out STD_LOGIC;
|
||||||
|
IDE_WAIT : in STD_LOGIC;
|
||||||
|
CLK_EXT : in STD_LOGIC;
|
||||||
|
IDE_W : out STD_LOGIC;
|
||||||
|
IDE_R : out STD_LOGIC;
|
||||||
|
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
|
||||||
|
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
|
||||||
|
-- LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
|
||||||
|
LAN_RD : out STD_LOGIC;
|
||||||
|
LAN_CS : out STD_LOGIC;
|
||||||
|
LAN_WRH : out STD_LOGIC;
|
||||||
|
LAN_WRL : out STD_LOGIC;
|
||||||
|
LAN_INT : in STD_LOGIC;
|
||||||
|
CP_RD : out STD_LOGIC;
|
||||||
|
CP_WE : out STD_LOGIC;
|
||||||
|
CP_CS : out STD_LOGIC;
|
||||||
|
CP_IRQ : in STD_LOGIC);
|
||||||
|
end LAN_IDE_CP;
|
||||||
|
|
||||||
|
architecture Behavioral of LAN_IDE_CP is
|
||||||
|
|
||||||
|
TYPE lan_reset IS (
|
||||||
|
nop,
|
||||||
|
wait0,
|
||||||
|
clr,
|
||||||
|
clr_commit,
|
||||||
|
wait1,
|
||||||
|
set,
|
||||||
|
set_commit,
|
||||||
|
done
|
||||||
|
);
|
||||||
|
|
||||||
|
TYPE lan_bus_sm IS (
|
||||||
|
nop,
|
||||||
|
start_read_upper,
|
||||||
|
wait_read_upper,
|
||||||
|
end_read_upper,
|
||||||
|
start_read_lower,
|
||||||
|
wait_read_lower,
|
||||||
|
end_read_lower,
|
||||||
|
start_write_upper,
|
||||||
|
wait_write_upper,
|
||||||
|
end_write_upper,
|
||||||
|
start_write_lower,
|
||||||
|
wait_write_lower,
|
||||||
|
end_write_lower,
|
||||||
|
config_rw
|
||||||
|
);
|
||||||
|
|
||||||
|
signal LAN_RST_SM: lan_reset :=nop;
|
||||||
|
signal LAN_SM: lan_bus_sm :=nop;
|
||||||
|
signal AUTOCONFIG_Z2_ACCESS: STD_LOGIC;
|
||||||
|
signal IDE_ACCESS: STD_LOGIC;
|
||||||
|
signal IDE_ENABLE: STD_LOGIC;
|
||||||
|
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||||
|
signal IDE_R_S: STD_LOGIC;
|
||||||
|
signal IDE_W_S: STD_LOGIC;
|
||||||
|
signal ROM_OE_S: STD_LOGIC;
|
||||||
|
|
||||||
|
signal CP_ACCESS: STD_LOGIC;
|
||||||
|
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||||
|
signal LAN_ACCESS: STD_LOGIC;
|
||||||
|
signal DQ_SWAP: STD_LOGIC;
|
||||||
|
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
|
||||||
|
signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(2 downto 0):="000";
|
||||||
|
signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0):="000";
|
||||||
|
signal SHUT_UP_Z2:STD_LOGIC_VECTOR(2 downto 0):="111";
|
||||||
|
signal LAN_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
|
||||||
|
signal LAN_INT_ENABLE: std_logic :='0';
|
||||||
|
signal LAN_RD_S: std_logic;
|
||||||
|
signal LAN_WRH_S: std_logic;
|
||||||
|
signal LAN_WRL_S: std_logic;
|
||||||
|
signal LAN_READY: std_logic;
|
||||||
|
signal CONFIG_READY: std_logic;
|
||||||
|
signal LAN_IRQ_D0: std_logic;
|
||||||
|
signal LAN_IRQ_OUT: std_logic;
|
||||||
|
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
|
||||||
|
signal Z3_DATA_IN:STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
signal Z3_DATA:STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
signal DQ_DATA:STD_LOGIC_VECTOR(15 downto 0);
|
||||||
|
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
|
||||||
|
signal Z3_A_LOW:STD_LOGIC;
|
||||||
|
signal LAN_SM_RST:STD_LOGIC;
|
||||||
|
|
||||||
|
signal CP_RD_S: std_logic;
|
||||||
|
signal CP_WE_S: std_logic;
|
||||||
|
signal CP_WE_QUIRK: std_logic;
|
||||||
|
|
||||||
|
signal AMIGA_CLK:STD_LOGIC;
|
||||||
|
signal DS:STD_LOGIC;
|
||||||
|
|
||||||
|
signal LAN_CS_RST: std_logic;
|
||||||
|
signal LAN_WR_RST: std_logic;
|
||||||
|
signal INT_VECTOR_CYCLE: std_logic;
|
||||||
|
|
||||||
|
signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
|
||||||
|
signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
|
||||||
|
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
|
||||||
|
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
|
||||||
|
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000001000010010"; --25MHz SET-MASK
|
||||||
|
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000110100000000"; --25MHz CLEAR-MASK
|
||||||
|
|
||||||
|
Function to_std_logic(X: in Boolean) return Std_Logic is
|
||||||
|
variable ret : std_logic;
|
||||||
|
begin
|
||||||
|
if x then ret := '1'; else ret := '0'; end if;
|
||||||
|
return ret;
|
||||||
|
end to_std_logic;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
|
||||||
|
|
||||||
|
Z3_DS <= UDS & LDS & DS1 & DS0;
|
||||||
|
AMIGA_CLK <= not (C1 xor C3);
|
||||||
|
DS <= UDS and LDS;
|
||||||
|
|
||||||
|
|
||||||
|
clock_init: process(reset,CLK_EXT)
|
||||||
|
begin
|
||||||
|
if(reset='1')then
|
||||||
|
--default values
|
||||||
|
LAN_CS_RST<='0';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=nop;
|
||||||
|
LAN_A_INIT<="11"&x"FFF";
|
||||||
|
LAN_D_INIT<= x"0000";
|
||||||
|
elsif(rising_edge(CLK_EXT))then --reset is low!
|
||||||
|
case LAN_RST_SM is
|
||||||
|
when nop=>
|
||||||
|
LAN_CS_RST<='0';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=wait0;
|
||||||
|
LAN_A_INIT <= LAN_A_CLRREG;
|
||||||
|
LAN_D_INIT <= LAN_D_CLR;
|
||||||
|
when wait0=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=clr;
|
||||||
|
LAN_A_INIT <= LAN_A_CLRREG;
|
||||||
|
LAN_D_INIT <= LAN_D_CLR;
|
||||||
|
when clr=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='1';
|
||||||
|
LAN_RST_SM<=clr_commit;
|
||||||
|
LAN_A_INIT <= LAN_A_CLRREG;
|
||||||
|
LAN_D_INIT <= LAN_D_CLR;
|
||||||
|
when clr_commit=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=wait1;
|
||||||
|
LAN_A_INIT <= LAN_A_CLRREG;
|
||||||
|
LAN_D_INIT <= LAN_D_CLR;
|
||||||
|
when wait1=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=set;
|
||||||
|
LAN_A_INIT <= LAN_A_SETREG;
|
||||||
|
LAN_D_INIT <= LAN_D_SET;
|
||||||
|
when set=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='1';
|
||||||
|
LAN_RST_SM<=set_commit;
|
||||||
|
LAN_A_INIT <= LAN_A_SETREG;
|
||||||
|
LAN_D_INIT <= LAN_D_SET;
|
||||||
|
when set_commit=>
|
||||||
|
LAN_CS_RST<='1';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=done;
|
||||||
|
LAN_A_INIT <= LAN_A_SETREG;
|
||||||
|
LAN_D_INIT <= LAN_D_SET;
|
||||||
|
when done=>
|
||||||
|
LAN_CS_RST<='0';
|
||||||
|
LAN_WR_RST<='0';
|
||||||
|
LAN_RST_SM<=done;
|
||||||
|
LAN_A_INIT <= LAN_A_SETREG;
|
||||||
|
LAN_D_INIT <= LAN_D_SET;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process clock_init;
|
||||||
|
|
||||||
|
ADDRESS_Z3_DECODE: process(reset,FCS)
|
||||||
|
begin
|
||||||
|
if(reset='0')then
|
||||||
|
LAN_ACCESS <= '0';
|
||||||
|
DQ_SWAP <= '1';
|
||||||
|
Z3_ADR <= (others => '1');
|
||||||
|
INT_VECTOR_CYCLE <='0';
|
||||||
|
elsif(falling_edge(FCS))then
|
||||||
|
|
||||||
|
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
|
||||||
|
|
||||||
|
INT_VECTOR_CYCLE <= not MTCR; --is this s special int vector cycle?!?
|
||||||
|
|
||||||
|
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
|
||||||
|
|
||||||
|
--lan base
|
||||||
|
--if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
|
||||||
|
if(Z3='1' and (D(15 downto 8) ) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
|
||||||
|
if(A(14 downto 13)<"11")then
|
||||||
|
DQ_SWAP <= '1';
|
||||||
|
else
|
||||||
|
DQ_SWAP <= '0';
|
||||||
|
end if;
|
||||||
|
LAN_ACCESS <= '1';
|
||||||
|
else
|
||||||
|
LAN_ACCESS <= '0';
|
||||||
|
DQ_SWAP <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process ADDRESS_Z3_DECODE;
|
||||||
|
|
||||||
|
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
|
||||||
|
begin
|
||||||
|
if(reset='0' or FCS='1')then
|
||||||
|
AUTOCONFIG_Z2_ACCESS <= '0';
|
||||||
|
IDE_ACCESS <= '0';
|
||||||
|
CP_ACCESS <= '0';
|
||||||
|
elsif(falling_edge(AS))then
|
||||||
|
|
||||||
|
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
|
||||||
|
AUTOCONFIG_Z2_ACCESS <= '1';
|
||||||
|
else
|
||||||
|
AUTOCONFIG_Z2_ACCESS <= '0';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--CP base
|
||||||
|
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' and LAN_ACCESS = '0')then
|
||||||
|
CP_ACCESS <= '1';
|
||||||
|
else
|
||||||
|
CP_ACCESS <= '0';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--IDE base
|
||||||
|
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' and LAN_ACCESS = '0' )then
|
||||||
|
IDE_ACCESS <= '1';
|
||||||
|
else
|
||||||
|
IDE_ACCESS <= '0';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process ADDRESS_Z2_DECODE;
|
||||||
|
|
||||||
|
--LAN interrupt controll
|
||||||
|
lan_int_proc: process (CLK_EXT,reset)
|
||||||
|
begin
|
||||||
|
if(reset ='0') then
|
||||||
|
LAN_IRQ_D0 <='1';
|
||||||
|
LAN_IRQ_OUT <='1';
|
||||||
|
elsif rising_edge(CLK_EXT) then
|
||||||
|
LAN_IRQ_D0 <= LAN_INT;
|
||||||
|
|
||||||
|
--set/deassert the LAN-interrupt bit
|
||||||
|
if( LAN_INT ='1' --or --no interupt
|
||||||
|
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
|
||||||
|
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
|
||||||
|
)then
|
||||||
|
LAN_IRQ_OUT <='1';
|
||||||
|
elsif(
|
||||||
|
(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
|
||||||
|
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
|
||||||
|
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
|
||||||
|
) then
|
||||||
|
LAN_IRQ_OUT <='0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process lan_int_proc;
|
||||||
|
|
||||||
|
--clock this signal to avoid glitches due to short resets
|
||||||
|
lan_rst_gen: process (CLK_EXT)
|
||||||
|
begin
|
||||||
|
if falling_edge(CLK_EXT) then
|
||||||
|
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or INT_VECTOR_CYCLE ='1') then
|
||||||
|
LAN_SM_RST <='1';
|
||||||
|
else
|
||||||
|
LAN_SM_RST <='0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process lan_rst_gen;
|
||||||
|
|
||||||
|
--lan signal generation: all Signals are HIGH active!
|
||||||
|
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
|
||||||
|
begin
|
||||||
|
if(LAN_SM_RST ='1' ) then
|
||||||
|
LAN_SM <=nop;
|
||||||
|
LAN_RD_S <= '0';
|
||||||
|
LAN_WRH_S <= '0';
|
||||||
|
LAN_WRL_S <= '0';
|
||||||
|
Z3_A_LOW <= '0';
|
||||||
|
LAN_READY <= '0';
|
||||||
|
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
|
||||||
|
DQ_DATA(15 downto 0) <= x"FFFF";
|
||||||
|
elsif rising_edge(CLK_EXT) then
|
||||||
|
--default values
|
||||||
|
LAN_RD_S <= '0';
|
||||||
|
LAN_WRH_S <= '0';
|
||||||
|
LAN_WRL_S <= '0';
|
||||||
|
Z3_A_LOW <= '0';
|
||||||
|
LAN_READY <= '0';
|
||||||
|
case LAN_SM is
|
||||||
|
when nop=>
|
||||||
|
--cycle start!
|
||||||
|
|
||||||
|
-- prepare the data for write
|
||||||
|
-- this is a quite complex thing for a cpld
|
||||||
|
-- so I have to move this out of the cycle start condition and prepare it for every loop
|
||||||
|
if(Z3_DS(3 downto 2) < "11")then
|
||||||
|
if(DQ_SWAP='0') then
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
|
||||||
|
else
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
|
||||||
|
end if;
|
||||||
|
else -- lower word!
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
if(DQ_SWAP='0') then
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
||||||
|
else
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
if(Z3_ADR(15)='1')then
|
||||||
|
LAN_SM <= config_rw;
|
||||||
|
elsif(RW='1')then --read from MSB
|
||||||
|
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_SM <= wait_read_upper;
|
||||||
|
else
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_SM <= wait_read_lower;
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
|
||||||
|
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
|
||||||
|
LAN_SM <= start_write_upper;
|
||||||
|
else
|
||||||
|
LAN_SM <= start_write_lower;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when start_read_upper=>
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_SM <= wait_read_upper;
|
||||||
|
when wait_read_upper=>
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_SM<=end_read_upper;
|
||||||
|
when end_read_upper=>
|
||||||
|
--fetch data
|
||||||
|
if(DQ_SWAP='0') then
|
||||||
|
Z3_DATA(31 downto 16) <= DQ;
|
||||||
|
else
|
||||||
|
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||||
|
end if;
|
||||||
|
if(Z3_DS(1 downto 0) = "11")then -- no lower half
|
||||||
|
LAN_READY <='1';
|
||||||
|
LAN_SM <= end_read_upper; -- stay here until cylce end
|
||||||
|
else
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
LAN_SM <= start_read_lower;
|
||||||
|
end if;
|
||||||
|
when start_read_lower=>
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_SM <= wait_read_lower;
|
||||||
|
when wait_read_lower=>
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
LAN_RD_S <= '1';
|
||||||
|
LAN_READY <= '1';
|
||||||
|
LAN_SM<=end_read_lower;
|
||||||
|
when end_read_lower=>
|
||||||
|
--fetch data
|
||||||
|
if(DQ_SWAP='0') then
|
||||||
|
Z3_DATA(15 downto 0) <= DQ;
|
||||||
|
else
|
||||||
|
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||||
|
end if;
|
||||||
|
LAN_READY <='1';
|
||||||
|
LAN_SM<=end_read_lower; -- stay here until cylce end
|
||||||
|
when start_write_upper=>
|
||||||
|
-- swapped DS3/DS2 here: ENC624 is little endian
|
||||||
|
LAN_WRH_S <= not Z3_DS(2);
|
||||||
|
LAN_WRL_S <= not Z3_DS(3);
|
||||||
|
LAN_SM <= wait_write_upper;
|
||||||
|
when wait_write_upper=>
|
||||||
|
LAN_SM<=end_write_upper;
|
||||||
|
when end_write_upper=>
|
||||||
|
-- prepare the data for write
|
||||||
|
if(DQ_SWAP='0') then
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
||||||
|
else
|
||||||
|
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
if(Z3_DS(1 downto 0) = "11")then -- no lower half
|
||||||
|
LAN_READY <='1';
|
||||||
|
LAN_SM <= end_write_upper; -- stay here until cylce end
|
||||||
|
else
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
LAN_SM <= start_write_lower;
|
||||||
|
end if;
|
||||||
|
when start_write_lower=>
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
-- swapped DS0/DS1 here: ENC624 is little endian
|
||||||
|
LAN_WRH_S <= not Z3_DS(0);
|
||||||
|
LAN_WRL_S <= not Z3_DS(1);
|
||||||
|
LAN_SM <= wait_write_lower;
|
||||||
|
when wait_write_lower=>
|
||||||
|
Z3_A_LOW <= '1';
|
||||||
|
LAN_READY <='1';
|
||||||
|
LAN_SM<=end_write_lower;
|
||||||
|
when end_write_lower=>
|
||||||
|
LAN_READY <='1';
|
||||||
|
LAN_SM<=end_write_lower; -- stay here until cylce end
|
||||||
|
when config_rw=>
|
||||||
|
LAN_READY <='1';
|
||||||
|
if(Z3_DS(3) ='0' and RW='0')then
|
||||||
|
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
|
||||||
|
elsif(Z3_DS(1) ='0' and RW='0')then
|
||||||
|
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
|
||||||
|
end if;
|
||||||
|
LAN_SM<=config_rw; -- stay here until cylce end
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process lan_rw_gen;
|
||||||
|
|
||||||
|
--autoconfig
|
||||||
|
autoconfig_proc: process (reset, AMIGA_CLK)
|
||||||
|
begin
|
||||||
|
if reset = '0' then
|
||||||
|
-- reset active ...
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE <="000";
|
||||||
|
D_Z2_OUT<="1111";
|
||||||
|
SHUT_UP_Z2 <="111";
|
||||||
|
IDE_BASEADR<=x"FF";
|
||||||
|
CP_BASEADR<=x"FF";
|
||||||
|
AUTO_CONFIG_Z2_DONE <="000";
|
||||||
|
LAN_BASEADR<=x"FFFF";
|
||||||
|
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
|
||||||
|
D_Z2_OUT<="1111";
|
||||||
|
if(AS='1')then
|
||||||
|
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE;
|
||||||
|
elsif(AUTOCONFIG_Z2_ACCESS= '1' and DS='0') then
|
||||||
|
case A(6 downto 1) is
|
||||||
|
when "000000" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||||
|
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
|
||||||
|
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
|
||||||
|
end if;
|
||||||
|
when "000001" => D_Z2_OUT <= "0001" ; --one Card, 64KB =001
|
||||||
|
when "000010" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "1000" ; --ProductID high nibble : 7->1000
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "1111" ; --ProductID high nibble : 0->1111
|
||||||
|
end if;
|
||||||
|
when "000011" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||||
|
D_Z2_OUT <= "0100" ; --ProductID low nibble: B->0100
|
||||||
|
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "0011" ; --ProductID low nibble: C->0011
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "1001" ; --ProductID low nibble: 6->1001
|
||||||
|
end if;
|
||||||
|
when "000100" => --er_flags (Z3)
|
||||||
|
D_Z2_OUT <= "1110" ; -- io device no size extension 64kb subsize
|
||||||
|
when "000101" => --er_flags (Z3)
|
||||||
|
D_Z2_OUT <= "1101" ; -- io device no size extension 64kb subsize
|
||||||
|
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
|
||||||
|
|
||||||
|
when "001001" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "0101" ; --Ventor ID 1
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "0111" ; --Ventor ID 1
|
||||||
|
end if;
|
||||||
|
when "001010" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "1110" ; --Ventor ID 2
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "1101" ; --Ventor ID 2
|
||||||
|
end if;
|
||||||
|
when "001011" =>
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
|
||||||
|
else
|
||||||
|
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $082C: BSC
|
||||||
|
end if;
|
||||||
|
when "001100" => D_Z2_OUT <= "0100" ; --Serial byte 0 (msb) high nibble
|
||||||
|
when "001101" => D_Z2_OUT <= "1110" ; --Serial byte 0 (msb) low nibble
|
||||||
|
when "001110" => D_Z2_OUT <= "1001" ; --Serial byte 1 high nibble
|
||||||
|
when "001111" => D_Z2_OUT <= "0100" ; --Serial byte 1 low nibble
|
||||||
|
when "010000" => D_Z2_OUT <= "1111" ; --Serial byte 2 high nibble
|
||||||
|
when "010001" => D_Z2_OUT <= "1111" ; --Serial byte 2 low nibble
|
||||||
|
when "010010" => D_Z2_OUT <= "0100" ; --Serial byte 3 (lsb) high nibble
|
||||||
|
when "010011" => D_Z2_OUT <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
|
||||||
|
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
|
||||||
|
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
|
||||||
|
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
|
||||||
|
when "010111" =>
|
||||||
|
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
|
||||||
|
when "100010" =>
|
||||||
|
D_Z2_OUT <= "1111" ;
|
||||||
|
if(RW='0')then
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||||
|
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
|
||||||
|
SHUT_UP_Z2(0) <='0'; --enable board
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when "100100" =>
|
||||||
|
D_Z2_OUT <= "1111" ;
|
||||||
|
if(RW='0' and AUTO_CONFIG_Z2_DONE(0)='1')then
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||||
|
SHUT_UP_Z2(1) <='0'; --enable board
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||||
|
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||||
|
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||||
|
SHUT_UP_Z2(2) <= '0'; --enable board
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when "100110" =>
|
||||||
|
D_Z2_OUT <= "1111" ;
|
||||||
|
if(RW='0')then
|
||||||
|
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||||
|
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||||
|
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||||
|
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when others => D_Z2_OUT <= "1111" ;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process autoconfig_proc; --- that's all
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
|
||||||
|
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
||||||
|
LAN_WRH <= LAN_WRH_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
||||||
|
LAN_RD <= LAN_RD_S when FCS='0' and reset = '1' else '0';
|
||||||
|
-- LAN_CFG <= "ZZZZ";
|
||||||
|
|
||||||
|
|
||||||
|
A_LAN(13 downto 6)<= LAN_A_INIT(13 downto 6) when reset ='0' else
|
||||||
|
Z3_ADR(14 downto 7);
|
||||||
|
A_LAN(5 downto 2) <= LAN_A_INIT(5 downto 2) when reset ='0' else
|
||||||
|
-- A(5 downto 2) when CP_ACCESS='1' else --mux the clock-port adresses! (CP was shifted by 1 on V1 boards, condition disabled here for V2)
|
||||||
|
Z3_ADR(6 downto 3);
|
||||||
|
A_LAN(1 downto 0)<= LAN_A_INIT(1 downto 0) when reset ='0' else
|
||||||
|
Z3_ADR(2) & Z3_A_LOW;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--signal assignment
|
||||||
|
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||||
|
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
|
||||||
|
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
|
||||||
|
DQ(15 downto 0) when RW='1' and IDE_ACCESS = '1' and AS='0' else
|
||||||
|
(others => 'Z');
|
||||||
|
|
||||||
|
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||||
|
(others => 'Z');
|
||||||
|
|
||||||
|
A(7 downto 1) <= (others => 'Z');
|
||||||
|
|
||||||
|
--defined lancp signal that matches both LAN and CP addresses
|
||||||
|
DQ <= LAN_D_INIT when reset='0' else
|
||||||
|
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
|
||||||
|
D when RW='0' and AS='0' and CP_ACCESS ='1' else
|
||||||
|
D when RW='0' and AS='0' and IDE_ACCESS ='1' else
|
||||||
|
(others => 'Z');
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
|
||||||
|
--'0' when CP_IRQ = '0' else
|
||||||
|
'Z';
|
||||||
|
INT6_OUT <= '0' when CP_IRQ = '0' else
|
||||||
|
'Z';
|
||||||
|
OWN <= 'Z';
|
||||||
|
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
|
||||||
|
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
|
||||||
|
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
|
||||||
|
|
||||||
|
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
|
||||||
|
|
||||||
|
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
|
||||||
|
|
||||||
|
MTACK <= 'Z';
|
||||||
|
|
||||||
|
|
||||||
|
--ide signal generation
|
||||||
|
ide_rw_gen: process (reset,AMIGA_CLK)
|
||||||
|
begin
|
||||||
|
if (reset = '0') then
|
||||||
|
IDE_ENABLE <= '1';
|
||||||
|
IDE_R_S <= '1';
|
||||||
|
IDE_W_S <= '1';
|
||||||
|
ROM_OE_S <= '1';
|
||||||
|
elsif falling_edge(AMIGA_CLK) then
|
||||||
|
--default values
|
||||||
|
IDE_R_S <= '1';
|
||||||
|
IDE_W_S <= '1';
|
||||||
|
ROM_OE_S <= '1';
|
||||||
|
if(IDE_ACCESS='1' and AS='0')then
|
||||||
|
if(RW='0')then
|
||||||
|
--the write goes to the hdd!
|
||||||
|
IDE_ENABLE <= '0'; -- enable IDE on first read
|
||||||
|
IDE_W_S <= '0';
|
||||||
|
else
|
||||||
|
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
|
||||||
|
ROM_OE_S <= not IDE_ENABLE;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process ide_rw_gen;
|
||||||
|
|
||||||
|
IDE_W <= IDE_W_S when AS='0' else '1';
|
||||||
|
IDE_R <= IDE_R_S when AS='0' else '1';
|
||||||
|
ROM_OE<= ROM_OE_S when AS='0' and AUTOBOOT_OFF ='0' else '1';
|
||||||
|
IDE_CS(0)<= not(A(12));
|
||||||
|
IDE_CS(1)<= not(A(13));
|
||||||
|
IDE_A(2 downto 0) <= A(11 downto 9);
|
||||||
|
ROM_B <= "00";
|
||||||
|
|
||||||
|
|
||||||
|
--cp signal generation
|
||||||
|
cp_rw_gen: process (AMIGA_CLK)
|
||||||
|
begin
|
||||||
|
if falling_edge(AMIGA_CLK) then
|
||||||
|
--default values
|
||||||
|
CP_RD_S <= '1';
|
||||||
|
CP_WE_S <= '1';
|
||||||
|
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
|
||||||
|
CP_RD_S <= not RW;
|
||||||
|
CP_WE_S <= RW;
|
||||||
|
end if;
|
||||||
|
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
|
||||||
|
end if;
|
||||||
|
end process cp_rw_gen;
|
||||||
|
|
||||||
|
--for the future
|
||||||
|
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||||
|
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||||
|
CP_CS <= not CP_ACCESS;
|
||||||
|
|
||||||
|
end Behavioral;
|
||||||
|
|
||||||
@@ -12,7 +12,7 @@
|
|||||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||||
</header>
|
</header>
|
||||||
|
|
||||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
|
||||||
|
|
||||||
<files>
|
<files>
|
||||||
<file xil_pn:name="LAN_IDE_CP-Z2v2.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="LAN_IDE_CP-Z2v2.vhd" xil_pn:type="FILE_VHDL">
|
||||||
@@ -82,9 +82,9 @@
|
|||||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP-z2v2|Behavioral" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP-z2v2" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
@@ -129,7 +129,7 @@
|
|||||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP-z2v2" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
|
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
|
||||||
@@ -146,7 +146,7 @@
|
|||||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP-z2v2" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
|||||||
@@ -0,0 +1,244 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||||
|
|
||||||
|
<header>
|
||||||
|
<!-- ISE source project file created by Project Navigator. -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- This file contains project source information including a list of -->
|
||||||
|
<!-- project source files, project and process properties. This file, -->
|
||||||
|
<!-- along with the project source files, is sufficient to open and -->
|
||||||
|
<!-- implement in ISE Project Navigator. -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||||
|
</header>
|
||||||
|
|
||||||
|
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
|
||||||
|
|
||||||
|
<files>
|
||||||
|
<file xil_pn:name="LAN_IDE_CP.vhd" xil_pn:type="FILE_VHDL">
|
||||||
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||||
|
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||||
|
</file>
|
||||||
|
<file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
|
||||||
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||||
|
</file>
|
||||||
|
<file xil_pn:name="LAN_IDE_CP_TB.vhd" xil_pn:type="FILE_VHDL">
|
||||||
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||||
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
|
||||||
|
</file>
|
||||||
|
</files>
|
||||||
|
|
||||||
|
<properties>
|
||||||
|
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||||
|
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Device" xil_pn:value="xc95288xl" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||||
|
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP.vhd" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Max Fanout" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||||
|
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||||
|
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP-z3v2" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="LAN_IDE_CP_map.vhd" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="LAN_IDE_CP_timesim.vhd" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="LAN_IDE_CP_synthesis.vhd" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="LAN_IDE_CP_translate.vhd" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||||
|
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Target UCF File Name" xil_pn:value="pinlist.ucf" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<!-- -->
|
||||||
|
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||||
|
<!-- -->
|
||||||
|
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|LAN_IDE_CP_TB|behavior" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-12-18T11:26:25" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A2E624B6ED1449CD92F77DE849BF7B51" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||||
|
</properties>
|
||||||
|
|
||||||
|
<bindings/>
|
||||||
|
|
||||||
|
<libraries/>
|
||||||
|
|
||||||
|
<autoManagedFiles>
|
||||||
|
<!-- The following files are identified by `include statements in verilog -->
|
||||||
|
<!-- source files and are automatically managed by Project Navigator. -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||||
|
<!-- project is analyzed based on files automatically identified as -->
|
||||||
|
<!-- include files. -->
|
||||||
|
</autoManagedFiles>
|
||||||
|
|
||||||
|
</project>
|
||||||
@@ -96,10 +96,11 @@ NET "IDE_R" LOC = "P27" ;
|
|||||||
NET "IDE_W" LOC = "P28" ;
|
NET "IDE_W" LOC = "P28" ;
|
||||||
NET "IDE_WAIT" LOC = "P33" ;
|
NET "IDE_WAIT" LOC = "P33" ;
|
||||||
NET "INT2_OUT" LOC = "P32" ;
|
NET "INT2_OUT" LOC = "P32" ;
|
||||||
NET "LAN_CFG<1>" LOC = "P12" ;
|
//NET "UNUSED_LAN_CFG<1>" LOC = "P12" ;
|
||||||
NET "LAN_CFG<2>" LOC = "P135" ;
|
NET "INT6_OUT" LOC = "P135" ;
|
||||||
NET "LAN_CFG<3>" LOC = "P13" ;
|
//NET "LAN_CFG<2>" LOC = "P135" ; // was: LAN_CFG2, now is INT6_OUT
|
||||||
NET "LAN_CFG<4>" LOC = "P110" ;
|
//NET "UNUSED_LAN_CFG<3>" LOC = "P13" ;
|
||||||
|
//NET "UNUSED_LAN_CFG<4>" LOC = "P110" ;
|
||||||
NET "LAN_CS" LOC = "P133" ;
|
NET "LAN_CS" LOC = "P133" ;
|
||||||
NET "LAN_WRL" LOC = "P76" ;
|
NET "LAN_WRL" LOC = "P76" ;
|
||||||
NET "LAN_INT" LOC = "P111" ;
|
NET "LAN_INT" LOC = "P111" ;
|
||||||
@@ -111,8 +112,7 @@ NET "MTCR" LOC = "P101" ;
|
|||||||
NET "OVR" LOC = "P100" ;
|
NET "OVR" LOC = "P100" ;
|
||||||
NET "OWN" LOC = "P107" ;
|
NET "OWN" LOC = "P107" ;
|
||||||
NET "RESET" LOC = "P143" ;
|
NET "RESET" LOC = "P143" ;
|
||||||
#NET "ROM_B<0>" LOC = "P68" ;//comment if fix for broken Xilinx!
|
NET "ROM_B<0>" LOC = "P68" ;//comment if fix for broken Xilinx!
|
||||||
NET "INT6_OUT" LOC = "P68" ;
|
|
||||||
NET "ROM_B<1>" LOC = "P69" ;
|
NET "ROM_B<1>" LOC = "P69" ;
|
||||||
NET "ROM_OE" LOC = "P35" ;
|
NET "ROM_OE" LOC = "P35" ;
|
||||||
NET "RW" LOC = "P83" ;
|
NET "RW" LOC = "P83" ;
|
||||||
|
|||||||
Reference in New Issue
Block a user