IDE and CP working in z2-mode
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@@ -110,8 +110,6 @@ INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP>
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <AUTOBOOT_OFF> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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@@ -167,7 +165,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 173.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 181.
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Found 1-bit register for signal <AUTO_CONFIG_DONE>.
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Found 1-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 2-bit register for signal <AUTO_CONFIG_Z2_DONE>.
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@@ -176,22 +174,26 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit register for signal <AUTOCONFIG_Z3_ACCESS>.
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Found 1-bit register for signal <CONFIG_READY>.
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Found 1-bit register for signal <CP_ACCESS>.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 290.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 297.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_QUIRK>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 8-bit register for signal <D_OUT>.
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Found 4-bit register for signal <D_Z2_OUT>.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 669.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 675.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 261.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 269.
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Found 1-bit register for signal <IDE_ACCESS>.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 297.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 304.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 8-bit comparator equal for signal <IDE_ENABLE$cmp_eq0000> created at line 297.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 260.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 268.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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@@ -200,11 +202,12 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 405.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 411.
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Found 1-bit register for signal <LAN_SM_RST>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 1-bit register for signal <SHUT_UP>.
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Found 2-bit register for signal <SHUT_UP_Z2>.
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Found 1-bit register for signal <Z3_A_LOW>.
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@@ -213,8 +216,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 ROM(s).
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inferred 57 D-type flip-flop(s).
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inferred 7 Comparator(s).
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inferred 61 D-type flip-flop(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 57 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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@@ -226,18 +229,18 @@ HDL Synthesis Report
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Macro Statistics
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# ROMs : 1
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16x8-bit ROM : 1
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# Registers : 68
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1-bit register : 58
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# Registers : 74
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1-bit register : 64
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14-bit register : 2
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16-bit register : 3
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2-bit register : 1
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4-bit register : 1
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8-bit register : 3
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# Comparators : 7
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# Comparators : 6
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16-bit comparator equal : 1
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2-bit comparator less : 2
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4-bit comparator less : 1
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8-bit comparator equal : 3
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8-bit comparator equal : 2
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# Tristates : 27
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1-bit tristate buffer : 25
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16-bit tristate buffer : 2
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@@ -311,11 +314,11 @@ Macro Statistics
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# FSMs : 2
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# ROMs : 1
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16x8-bit ROM : 1
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# Registers : 57
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Flip-Flops : 57
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# Comparators : 4
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# Registers : 61
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Flip-Flops : 61
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# Comparators : 3
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16-bit comparator equal : 1
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8-bit comparator equal : 3
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8-bit comparator equal : 2
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=========================================================================
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@@ -348,28 +351,28 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=s : D_OUT_7
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implementation constraint: INIT=s : D_Z2_OUT_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=s : D_OUT_4
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=s : D_Z2_OUT_3
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implementation constraint: INIT=s : LAN_A_INIT_3
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
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implementation constraint: INIT=s : LAN_A_INIT_6
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implementation constraint: INIT=s : D_OUT_0
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implementation constraint: INIT=s : D_OUT_1
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implementation constraint: INIT=s : D_OUT_2
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=s : D_OUT_3
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : D_OUT_4
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=s : D_Z2_OUT_2
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implementation constraint: INIT=s : D_OUT_5
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implementation constraint: INIT=s : D_OUT_6
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
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implementation constraint: INIT=s : LAN_A_INIT_6
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implementation constraint: INIT=s : D_Z2_OUT_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=s : D_Z2_OUT_0
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implementation constraint: INIT=s : D_OUT_7
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implementation constraint: INIT=s : D_OUT_6
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implementation constraint: INIT=s : D_OUT_5
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implementation constraint: INIT=s : D_OUT_3
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=s : D_OUT_2
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implementation constraint: INIT=s : D_OUT_1
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implementation constraint: INIT=s : D_OUT_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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@@ -408,26 +411,25 @@ Design Statistics
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# IOs : 116
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Cell Usage :
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# BELS : 1263
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# AND2 : 379
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# AND3 : 54
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# AND4 : 10
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# BELS : 1268
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# AND2 : 378
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# AND3 : 53
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# AND4 : 11
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# AND8 : 6
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# GND : 1
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# INV : 465
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# OR2 : 277
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# OR3 : 18
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# INV : 468
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# OR2 : 278
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# OR3 : 21
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# OR4 : 1
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# VCC : 1
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# XOR2 : 51
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# FlipFlops/Latches : 145
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# FD : 1
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# FlipFlops/Latches : 151
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# FD : 4
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# FDC : 22
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# FDCE : 8
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# FDP : 46
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# FDPE : 68
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# IO Buffers : 112
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# IBUF : 22
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# FDCE : 7
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# FDP : 49
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# FDPE : 69
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# IO Buffers : 114
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# IBUF : 24
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# IOBUFE : 48
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# OBUF : 33
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# OBUFE : 9
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@@ -435,13 +437,13 @@ Cell Usage :
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Total REAL time to Xst completion: 19.00 secs
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Total CPU time to Xst completion: 19.05 secs
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Total CPU time to Xst completion: 18.89 secs
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-->
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Total memory usage is 4534736 kilobytes
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Total memory usage is 4534828 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 48 ( 0 filtered)
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Number of warnings : 46 ( 0 filtered)
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Number of infos : 10 ( 0 filtered)
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