sm cleaned up

This commit is contained in:
MHeinrichs
2018-12-17 23:03:12 +01:00
parent 73899442dc
commit deb69da927
41 changed files with 20882 additions and 21991 deletions
+3 -5
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Dec 14 01:20:14 2018">
<application name="pn" timeStamp="Mon Dec 17 22:58:41 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="0" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -13,16 +13,14 @@ This means code written to parse this file will need to be revisited each subseq
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="area;C:/Xilinx/14.7/ISE_DS/ISE/data/area.xds" type="design"/>
<property name="PROP_LastAppliedStrategy" value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthFsmEncode" value="Compact" type="process"/>
<property name="PROP_SynthOpt" value="Area" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Xilinx/14.7/ISE_DS/ISE/data/area.xds" type="process"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
<property name="PROP_intWbtProjectID" value="0" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>