enc624j6net
- improved duplex/offline check handling - better TX handling (one less full frame copy per TX request), i.e. direct write from driver to HW buffer - some other minor changes - revised TX is optional (see smakefile), requires a VHDL fix that is not checked in to svn as of yet
This commit is contained in:
HenrykRichter
@@ -1,8 +1,8 @@
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#ifndef _DEV_INFO_H
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#define _DEV_INFO_H
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#define DEVICE_NAME "enc624j6net"
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#define DEVICE_DATE "18.12.2017"
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#define DEVICE_VER "0.1"
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#define DEVICE_DATE "16.04.2018"
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#define DEVICE_VER "0.2"
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#define DEVICE_VERSION 0
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#define DEVICE_REVISION 1
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#define DEVICE_REVISION 2
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#endif
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@@ -2,10 +2,10 @@ DEVICE_NAME MACRO
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dc.b 'enc624j6net'
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ENDM
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DEVICE_DATE MACRO
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dc.b '18.12.2017'
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dc.b '16.04.2018'
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ENDM
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DEVICE_VER MACRO
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dc.b '0.1'
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dc.b '0.2'
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ENDM
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DEVICE_VERSION equ 0
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DEVICE_REVISION equ 1
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DEVICE_REVISION equ 2
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@@ -448,7 +448,7 @@ PRIVATE APTR pb_AllocExpansion( ULONG portid, BASEPTR )
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{
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d(("starting server"));
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if (pb->pb_Server = CreateNewProcTags(NP_Entry, ServerTask, NP_Name,
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NP_Priority, 59, SERVERTASKNAME, TAG_DONE))
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SERVERTASKNAME, NP_Priority, 5, TAG_DONE))
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{
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ss.ss_Error = 1;
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ss.ss_PLIPBase = pb;
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@@ -630,6 +630,16 @@ PRIVATE APTR pb_AllocExpansion( ULONG portid, BASEPTR )
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/*
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** initiate io command (1st level dispatcher)
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*/
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#if 1
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/* got so tired of the SAS/C "inlining notice", made a macro instead */
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#define DevForwardIO( _BP_ , _REQ_ ) \
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{\
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struct IOSana2Req *_rq_ = (struct IOSana2Req*)_REQ_;\
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_rq_->ios2_Req.io_Flags &= ~SANA2IOF_QUICK;\
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PutMsg( (_BP_)->pb_ServerPort, (struct Message*)_rq_);\
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}
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#else
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/*F*/ static INLINE VOID DevForwardIO(BASEPTR, struct IOSana2Req *ios2)
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{
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d(("forwarding request %ld\n", ios2->ios2_Req.io_Command));
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@@ -639,6 +649,9 @@ PRIVATE APTR pb_AllocExpansion( ULONG portid, BASEPTR )
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PutMsg(pb->pb_ServerPort, (struct Message*)ios2);
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}
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/*E*/
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#endif
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/*F*/ PUBLIC VOID DevTermIO(BASEPTR, struct IOSana2Req *ios2)
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{
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d(("cmd = %ld, error = %ld, wireerror = %ld\n", ios2->ios2_Req.io_Command, ios2->ios2_Req.io_Error,ios2->ios2_WireError));
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@@ -1,4 +1,3 @@
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;APS00000000000000000000000000000000000000000000000000000000000000000000000000000000
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; ------------------------------------------------------------------------------
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; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
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; | Henryk Richter <henryk.richter@gmx.net> |
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@@ -27,6 +26,7 @@
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DEBUG EQU 0
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;
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;------------- <DANGER! APPLY CHANGES HERE ALSO TO enc624j6l.h !!> ------------
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;
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; options for buffer memory configuration, please reserve some space for private variables
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;
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@@ -48,7 +48,7 @@ PNextPacket EQU PSTART_INIT ;2 Bytes - private "next packet" pointer for RX
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PNextTX EQU PSTART_INIT+2 ;2 Bytes - private "next packet" pointer for TX (init as 0)
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PSigBit EQU PSTART_INIT+4 ;2 Bytes interrupt bit
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PSigTask EQU PSTART_INIT+6 ;4 Bytes signaled task
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PLinkChange EQU PSTART_INIT+10 ;2 Bytes Link Change (Bit0 used right now)
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PLinkChange EQU PSTART_INIT+10 ;2 Bytes Link Change (copy of PHYDPX,PHYLNK bits)
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Punused EQU PSTART_INIT+12 ;
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;------------- TX: double buffering --------------------------------
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@@ -64,6 +64,7 @@ PIO_INIT_FLOW_CONTROL EQU 8
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PIO_INIT_MULTI_CAST EQU 16
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PIO_INIT_PROMISC EQU 32
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;------------- </DANGER! APPLY CHANGES HERE ALSO TO enc624j6l.h !!> -----------
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ifne DEBUG
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@@ -95,6 +96,7 @@ ENC_BOARDID EQU 123 ;ZII-IDE-LAN-CP
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;online/offline
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XDEF _enc624j6l_SetOffline
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XDEF _enc624j6l_SetOnline
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XDEF _enc624j6l_CheckLinkChange
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;transmit/receive functions
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XDEF _enc624j6l_HaveRecv ;
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@@ -252,6 +254,14 @@ opendos:
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error:
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rts
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regtests:
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READREG ESTAT,a0,d0
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READREG ECON1,a0,d1
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READREG MACON2,a0,d2
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READREG MABBIPG,a0,d3
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rts
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DosLibrary: dc.b "dos.library",0
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ExpansionLibrary: dc.b "expansion.library",0
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cnop 0,4
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@@ -535,8 +545,16 @@ _enc624j6l_Init:
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;Multicast,Broadcast,Unicast(self),MagicPacket,correct CRC,filter runts
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;"not me" Unicast == |ERXFCON_NOTMEEN
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moveq #PIO_INIT_MULTI_CAST,d0
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and d1,d0
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beq.s .no_multicast
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move #ERXFCON_MCEN|ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
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bra.s .setfilter
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.no_multicast
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move #ERXFCON_BCEN|ERXFCON_UCEN|ERXFCON_MPEN|ERXFCON_CRCEN|ERXFCON_RUNTEN,d0
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.setfilter
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WRITEREG ERXFCON,a0,d0 ;set filter TODO: pattern matching stuff
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move #RXSTOP_INIT&$fffe,d0
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WRITEREG ERXTAIL,a0,d0 ;tail pointer in buffer = rx-2, wraparound
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@@ -565,7 +583,7 @@ _enc624j6l_Init:
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move #MACON2_PADCFG2|MACON2_PADCFG1|MACON2_PADCFG0|MACON2_PHDREN,d0
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CLRREG MACON2,a0,d0
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; add CRC by ENC Chip
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move #MACON2_PADCFG1|MACON2_PADCFG0|MACON2_TXCRCEN,d0
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move #MACON2_PADCFG2|MACON2_PADCFG0|MACON2_TXCRCEN,d0 ;
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SETREG MACON2,a0,d0
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move #MAX_FRAMELEN,d0
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@@ -573,6 +591,8 @@ _enc624j6l_Init:
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moveq #0,d0
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WRITEREG PNextTX,a0,d0 ;private pointer, "last written, maybe still pending frame"
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moveq #0,d0
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WRITEREG PLinkChange,a0,d0 ;no detected/acknowledged link right now, i.e. LNK and DPX bits = 0
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;--------------- DONE: enable reception -----------------
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moveq #ECON1_RXEN,d0
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@@ -635,8 +655,8 @@ _enc624j6l_SetOnline:
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moveq #ECON1_RXEN,d0
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SETREG ECON1,a0,d0
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moveq #1,d0
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WRITEREG PLinkChange,a0,d0
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moveq #0,d0
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WRITEREG PLinkChange,a0,d0 ;no detected/acknowledged link right now, i.e. LNK and DPX bits = 0
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;moveq #1,d0 ;already set, see above
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.err
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@@ -842,6 +862,83 @@ _enc624j6l_IntServer:
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moveq #0,d0 ;set Z flag
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rts
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;---------------------------------------------------------------------------------------
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;
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; check for link change events
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;
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; In: A0 = board base address
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;
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; Out: D0 <0 error
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; =0 ok, no link change handled
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; >0 ok, link change handled
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;
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; Notes: assumes that init() was called before
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;
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_enc624j6l_CheckLinkChange:
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move.l a0,d0
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beq.s .rts
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; link change events are captured with Interrupts and stored
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; in the (custom) PLinkChange location (per board) by init and
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; the int server (0 -> no link change, !=0 -> link change)
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READREG PLinkChange,a0,d0 ;last known status of LNK and DPX
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READREG ESTAT,a0,d1
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and #ESTAT_PHYLNK|ESTAT_PHYDPX,d1 ;
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eor.w d1,d0 ;compare
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beq .nochg
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WRITEREG PLinkChange,a0,d1 ;remember last parsed settings
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;check for link down before setting registers
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;also be aware of shutting down FDX mode
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;
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move #ESTAT_PHYLNK,d0
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and d1,d0
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bne.s .linkup
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;
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; offline
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;
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; D1 = ESTAT & (ESTAT_PHYDPX|ESTAT_PHYLNK)
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;
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moveq #MACON2_FULDPX,d0
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CLRREG MACON2,a0,d0 ;clear fullduplex bit when offline
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moveq #$12,d0
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WRITEREG MABBIPG,a0,d0 ;half duplex when offline
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bra.s .endchg
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.linkup:
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;
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; online
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;
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; D1 = ESTAT & (ESTAT_PHYDPX|ESTAT_PHYLNK)
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;
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; link up and configured
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bfextu d1{21:1},d1 ;get Bit 10 to Bit 0 (ESTAT_PHYDPX -> MACON2_FULDPX)
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READREG MACON2,a0,d0
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bclr #0,d0 ;clear FDX bit
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or.l d1,d0 ;set if active
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WRITEREG MACON2,a0,d0
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moveq #$12,d1 ;half duplex $12
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btst #0,d0
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beq.s .nofdx
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moveq #$15,d1 ;full duplex $15
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.nofdx:
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WRITEREG MABBIPG,a0,d1
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.endchg:
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moveq #1,d0
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bra.s .rts
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.nochg:
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moveq #0,d0
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.rts:
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rts
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;---------------------------------------------------------------------------------------
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;
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; Reset Receive pointers
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@@ -1157,28 +1254,18 @@ _enc624j6l_TransmitFrame:
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move.l a0,d1 ;no base PTR
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beq.w .err ;exit
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READREG PLinkChange,a0,d1
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tst d1
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beq .linkup
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; link up and configured
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; this check moved to server.c -> hw.c -> enc624j6l_CheckLinkChange()
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; instead of checking with every TX frame, do it before going to sleep
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ifne _OPT_CHECKLINK_TX
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READREG ESTAT,a0,d1 ;Bit 10 is FULL DUPLEX (ESTAT_PHYDPX)
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bfextu d1{21:1},d1 ;get Bit 10 to Bit 0 (MACON2_FULDPX)
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READREG MACON2,a0,d2
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bclr #0,d2 ;clear FDX bit
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or.l d1,d2 ;set if active
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WRITEREG MACON2,a0,d2
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READREG PLinkChange,a0,d1 ;last known status of LNK and DPX
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READREG ESTAT,a0,d2 ;
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and #ESTAT_PHYLNK|ESTAT_PHYDPX,d2 ;
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eor.w d2,d1 ;compare
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bne.s .linkchg ;jump to parameter adjust
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.linkchgdone: ;.linkchg returns here with another branch
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moveq #$12,d1 ;half duplex $12
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btst #0,d2
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beq.s .nofdx
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moveq #$15,d1 ;full duplex $15
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.nofdx:
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WRITEREG MABBIPG,a0,d1
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moveq #0,d1
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WRITEREG PLinkChange,a0,d1
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.linkup:
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endc
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move.l a1,d1 ;no send frame ?
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beq.w .err ;exit
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@@ -1223,17 +1310,17 @@ _enc624j6l_TransmitFrame:
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swap d4
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;---------------- wait on last frame ----------------------------------
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moveq #100,d3
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move #200,d3
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.txwait:
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READREG ECON1,a0,d1
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and.w #ECON1_TXRTS,d1
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beq.s .txrdy
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;100 MBit/s frame time is max. 0.12 ms (without inter-frame spacing)
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;wait 50 us via CIA
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moveq #50,d0
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;wait 20 us via CIA
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moveq #120,d0
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bsr _enc624j6l_UMinDelay
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dbf d3,.txwait ;approx. 5ms max. wait
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dbf d3,.txwait ;approx. 4ms max. wait
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;hmpf. abort last transmission
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move #ECON1_TXRTS,d1 ;
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@@ -1252,6 +1339,15 @@ _enc624j6l_TransmitFrame:
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movem.l (sp)+,d2-d4/a2
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rts
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ifne _OPT_CHECKLINK_TX
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;branch here for link change events and adjust parameters in case
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.linkchg:
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movem.l d0-d1/a0-a1,-(sp)
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bsr _enc624j6l_CheckLinkChange
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movem.l (sp)+,d0-d1/a0-a1
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bra.s .linkchgdone
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endc
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;------------------------------------------------------------------------------------------------
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;------------------------------------------------------------------------------------------------
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@@ -40,6 +40,37 @@
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/* control ids */
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#define PIO_CONTROL_FLOW 0
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/*-- --*/
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/*------------- <DANGER! APPLY CHANGES IN HERE ALSO TO enc624j6l.asm !!> ----------*/
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/*-- --*/
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/* buffers and locations */
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#define PSTART_INIT 0x0BF0 /* 16 Bytes private storage for driver */
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#define PSTOP_INIT 0x0BFF /* (see below for definitions) */
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#define RXSTART_INIT 0x2000 /* start of RX buffer, room for 14 packets */
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#define RXSTOP_INIT 0x5fff /* end of RX buffer */
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#define TXSTART_INIT 0x0000 /* start of TX buffer, room for 2 packets */
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#define TXSTOP_INIT 0x0BEF /* end of TX buffer (1536+1520 bytes) */
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/* max frame length which the conroller will accept:
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(note: maximum ethernet frame length would be 1518 w/o 802.1Q) */
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#define MAX_FRAMELEN 1518
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/* ------------ driver private storage ------------------------------ */
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#define PNextPacket PSTART_INIT /* 2 Bytes - private "next packet" pointer for RX */
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#define PNextTX PSTART_INIT+2 /* 2 Bytes - private "next packet" pointer for TX (init as 0) */
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#define PSigBit PSTART_INIT+4 /* 2 Bytes interrupt bit */
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#define PSigTask PSTART_INIT+6 /* 4 Bytes signaled task */
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#define PLinkChange PSTART_INIT+10 /* 2 Bytes Link Change (Bit0 used right now) */
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#define Punused PSTART_INIT+12 /* */
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/* ------------- TX: double buffering -------------------------------- */
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#define PSwapTX 0x600 /* swap between two TX buffers (one active, one activated after last TX done) */
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/*-- --*/
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/*------------- </DANGER! APPLY CHANGES IN HERE ALSO TO enc624j6l.asm !!> ---------*/
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/*-- --*/
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/*
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@@ -268,5 +299,20 @@ ASM SAVEDS void enc624j6l_DisableGlobalInterrupt( ASMR(a0) void *board AS
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*/
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ASM SAVEDS void enc624j6l_IntServer( void );
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/*
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Purpose: check for link change events
|
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input: board - mmapped board base address
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output: <0 - error
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0 - ok, no link change handled
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>0 - ok, link change handled
|
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notes:
|
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|
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*/
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ASM SAVEDS int enc624j6l_CheckLinkChange( ASMR(a0) void *board ASMREG(a0) );
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#endif /* _INC_ENC624J6L_H */
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@@ -82,9 +82,10 @@
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#endif
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#ifdef PROTO_ENC624NET
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#include "enc624j6l.h"
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#include "registers.h"
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|
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/* 10000 without HW interrupt 100000 with HW interrupt */
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#define HW_INTERVALDEF 50000L
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#define HW_INTERVALDEF 100000L
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/* this is a BIG TODO! Make plipbox source multi-board aware */
|
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#define BOARD hwb->hwb_boards[0]
|
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@@ -93,6 +94,14 @@
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/*#define HW_INTSOURCE INTB_EXTER */ /* Int 6 */
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#define HW_INTSOURCE INTB_PORTS /* Int 2 */
|
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|
||||
/* write_frame, see server.c, too. .oO(move this into .h) */
|
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typedef enum { AW_OK, AW_BUFFER_ERROR, AW_ERROR } AW_RESULT;
|
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|
||||
#define READREG(_x_,_off_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) )
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#define WRITEREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) ) = (_y_);
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#define SETREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + SET_OFFSET )) = (_y_);
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#define CLRREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + CLR_OFFSET )) = (_y_);
|
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#endif
|
||||
|
||||
/* this is currently necessary on Apollo Core. We don't have an interrupt on the SD card slot */
|
||||
@@ -144,6 +153,110 @@ PRIVATE void startInt(struct PLIPBase *pb, struct HWBase *hwb, APTR board )
|
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}
|
||||
#endif
|
||||
|
||||
/* write_frame moved from server.c to here, because it directly interfaces with
|
||||
network module in this driver, active only when ENC624_OPT is given on compiler
|
||||
command line */
|
||||
#ifdef ENC624_OPT
|
||||
/*
|
||||
** write frames direcly to HW
|
||||
* CAUTION: don't mix up with hw_send_frame() / enc624j6l_TransmitFrame --
|
||||
* the double buffered write location is not shared right now
|
||||
*
|
||||
* logic in here
|
||||
* - swap buffer
|
||||
* - write into buffer
|
||||
* - wait for previous frame to finish (most likely there is no waiting time)
|
||||
* - issue HW TX command
|
||||
*
|
||||
*/
|
||||
/*F*/ GLOBAL REGARGS AW_RESULT write_frame(BASEPTR, struct IOSana2Req *ios2)
|
||||
{
|
||||
AW_RESULT rc;
|
||||
struct HWBase *hwb = &pb->pb_HWBase;
|
||||
|
||||
struct BufferManagement *bm;
|
||||
ULONG tl,totsize;
|
||||
unsigned short *s_wrptr,*s_tmp1;
|
||||
UBYTE *b_hwio_ptr = BOARD; /* somewhere $e80000 and beyond */
|
||||
|
||||
/* Note Link Change check moved to main loop */
|
||||
|
||||
d(("owrite: type %08lx, size %ld\n",ios2->ios2_PacketType,
|
||||
ios2->ios2_DataLength));
|
||||
|
||||
hwb->hwb_txdbuf = (hwb->hwb_txdbuf & PSwapTX) ^ PSwapTX; /* swap buffers (+sanity check by "&") */
|
||||
s_wrptr = (USHORT*)(b_hwio_ptr + hwb->hwb_txdbuf); /* next write location (byte->short) */
|
||||
|
||||
if(!(ios2->ios2_Req.io_Flags & SANA2IOF_RAW))
|
||||
{ /* structured SANAII Request, not a valid Ethernet Frame (yet) */
|
||||
/* Q: What about a length field and SNAP ? -> relevant here? */
|
||||
|
||||
/* write Ethernet header by hand: DMAC,SMAC,TYPE */
|
||||
s_tmp1 = (USHORT*)ios2->ios2_DstAddr;
|
||||
*s_wrptr++ = *s_tmp1++; *s_wrptr++ = *s_tmp1++; *s_wrptr++ = *s_tmp1; /* copy 6 bytes */
|
||||
|
||||
s_tmp1 = (USHORT*)pb->pb_CfgAddr;
|
||||
*s_wrptr++ = *s_tmp1++; *s_wrptr++ = *s_tmp1++; *s_wrptr++ = *s_tmp1; /* copy 6 bytes */
|
||||
|
||||
*s_wrptr++ = (USHORT)ios2->ios2_PacketType; /* copy 2 bytes TYPE field */
|
||||
|
||||
totsize = HW_ETH_HDR_SIZE + ios2->ios2_DataLength; /* 14; */
|
||||
}
|
||||
else
|
||||
{ /* RAW, pre-formatted Ethernet frame (sans CRC32) */
|
||||
totsize = ios2->ios2_DataLength; /* */
|
||||
}
|
||||
|
||||
/* copy frame to HW without a step in between (i.e. directly to mmapped card) */
|
||||
bm = (struct BufferManagement *)ios2->ios2_BufferManagement;
|
||||
|
||||
if( (*bm->bm_CopyFromBuffer)(s_wrptr, ios2->ios2_Data, ios2->ios2_DataLength) )
|
||||
{
|
||||
/* buffer delivered to HW, now trigger actual TX */
|
||||
/* waste time should the last frame still be in TX (unlikely) */
|
||||
/* 100 MBit/s frame time is max. 0.12 ms (without inter-frame spacing) */
|
||||
tl=0;
|
||||
while( READREG(b_hwio_ptr,ECON1) & ECON1_TXRTS )
|
||||
{
|
||||
if( ++tl > 100000 ) /* this read cylces through ZII/ZIII and still not finished ? */
|
||||
{
|
||||
CLRREG( b_hwio_ptr, ECON1, ECON1_TXRTS ); /* give up, cancel last transmission */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*------ set new frame parameters ----------- */
|
||||
WRITEREG( b_hwio_ptr, ETXST, hwb->hwb_txdbuf ); /* write location */
|
||||
WRITEREG( b_hwio_ptr, ETXLEN,totsize ); /* frame TX length (-CRC) */
|
||||
SETREG( b_hwio_ptr, ECON1, ECON1_TXRTS ); /* trigger TX */
|
||||
|
||||
rc = AW_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* meh: What's so hard about copying some bytes ? */
|
||||
rc = AW_BUFFER_ERROR;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
** check for link change
|
||||
* - call ASM file for that task
|
||||
* - the relevant flag is set by the interrupt handler and in that case,
|
||||
* a number of registers is reconfigured accordingly
|
||||
*
|
||||
*/
|
||||
/*F*/ GLOBAL REGARGS void hw_check_link_change( BASEPTR )
|
||||
{
|
||||
struct HWBase *hwb = &pb->pb_HWBase;
|
||||
|
||||
enc624j6l_CheckLinkChange(BOARD); /* somewhere $e80000 and beyond */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
magic: HW_MAGIC_OFFLINE, HW_MAGIC_ONLINE
|
||||
return TRUE/FALSE
|
||||
@@ -191,7 +304,9 @@ GLOBAL REGARGS void hw_config_init(struct PLIPBase *pb)
|
||||
|
||||
hwb->hwb_timervalue = HW_INTERVALDEF;
|
||||
hwb->hwb_fullduplex = 0;
|
||||
#ifndef PROTO_ENC624NET
|
||||
hwb->hwb_spispeed = 1; /* optimistic default */
|
||||
#endif
|
||||
hwb->hwb_multicast = 0;
|
||||
hwb->hwb_flowcontrol= 0; /* no flow control by default */
|
||||
}
|
||||
@@ -205,10 +320,12 @@ GLOBAL REGARGS void hw_config_update(struct PLIPBase *pb, struct TemplateConfig
|
||||
{
|
||||
hwb->hwb_timervalue = BOUNDS(*args->timervalue, HW_INTERVALMIN, HW_INTERVALMAX );
|
||||
}
|
||||
#ifndef PROTO_ENC624NET
|
||||
if( args->spispeed )
|
||||
{
|
||||
hwb->hwb_spispeed = BOUNDS(*args->spispeed, 1, 20 );
|
||||
}
|
||||
#endif
|
||||
if( args->fullduplex )
|
||||
{
|
||||
hwb->hwb_fullduplex = 1;
|
||||
@@ -468,7 +585,7 @@ GLOBAL REGARGS BOOL hw_recv_frame(struct PLIPBase *pb, struct HWFrame *frame)
|
||||
unsigned char *ptr = (unsigned char*)frame;
|
||||
struct HWBase *hwb = &pb->pb_HWBase;
|
||||
|
||||
len = enc624j6l_RecvFrame( BOARD, ptr+sizeof(USHORT), 1518 );
|
||||
len = enc624j6l_RecvFrame( BOARD, ptr+sizeof(USHORT), 1522 );
|
||||
frame->hwf_Size = len;
|
||||
|
||||
if( len > 0 )
|
||||
|
||||
@@ -37,13 +37,20 @@ struct HWBase
|
||||
|
||||
struct IVT_TimerStruct hwb_ivtimer; /* Timer interval handling (via Interrupt) */
|
||||
|
||||
#ifdef ENC624_OPT
|
||||
USHORT hwb_txdbuf; /* TX double buffering location (0x0/0x600) */
|
||||
USHORT hwb_unused_free_for_future;
|
||||
#endif
|
||||
|
||||
/* config options */
|
||||
ULONG hwb_timervalue; /* timer speed */
|
||||
UBYTE hwb_fullduplex; /* full duplex */
|
||||
UBYTE hwb_flowcontrol; /* flow control enable (1/0) */
|
||||
UBYTE hwb_multicast; /* multicast enable */
|
||||
UBYTE hwb_free_unused1;
|
||||
#ifndef PROTO_ENC624NET
|
||||
ULONG hwb_spispeed; /* SPI speed */
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HWB_RECV_PENDING 0
|
||||
@@ -60,8 +67,21 @@ struct HWBase
|
||||
/* ----- config ----- */
|
||||
|
||||
#define CONFIGFILE "ENV:SANA2/enc624j6net.config"
|
||||
#define TEMPLATE "TIMER/K/N,FULLDUPLEX/S,SPISPEED/K/N,MULTICAST/S,FLOWCONTROL/S"
|
||||
#ifdef PROTO_ENC624NET
|
||||
#define TEMPLATE "TIMER/K/N,FULLDUPLEX/S,MULTICAST/S,FLOWCONTROL/S"
|
||||
/* structure to be filled by ReadArgs template */
|
||||
struct TemplateConfig
|
||||
{
|
||||
struct CommonConfig common;
|
||||
ULONG *timervalue;
|
||||
ULONG fullduplex;
|
||||
ULONG multicast;
|
||||
ULONG flowcontrol;
|
||||
};
|
||||
|
||||
#else /* PROTO_ENC624NET */
|
||||
|
||||
#define TEMPLATE "TIMER/K/N,FULLDUPLEX/S,SPISPEED/K/N,MULTICAST/S"
|
||||
/* structure to be filled by ReadArgs template */
|
||||
struct TemplateConfig
|
||||
{
|
||||
@@ -72,5 +92,6 @@ struct TemplateConfig
|
||||
ULONG multicast;
|
||||
ULONG flowcontrol;
|
||||
};
|
||||
#endif /* PROTO_ENC624NET */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -10,6 +10,7 @@ _OPT_REG_SWAP EQU 0 ;perform byte swap on register ops (1) or assume native end
|
||||
_OPT_ADR_QUIRK EQU 0 ;address lines 12/13 are swapped (1) or linear addressing (0)
|
||||
_OPT_FLOWCONTROL EQU 0 ;perform flow control on RX (1) or not (0)
|
||||
_OPT_RECV EQU 1 ;faster recv (1) or generic (0)
|
||||
_OPT_CHECKLINK_TX EQU 0 ;check for link changes in TX (1) or expect from outside (0) -> see server.c
|
||||
|
||||
;\1 register offset (without CLEAR offset)
|
||||
;\2 address register of board I/O base
|
||||
@@ -32,6 +33,9 @@ SETREG macro
|
||||
;\1 register offset (e.g. ESTAT)
|
||||
;\2 address register of board I/O base (e.g. a0)
|
||||
;\3 destination register to be written (e.g. d0)
|
||||
;
|
||||
;important: when changing this, make sure the flags
|
||||
;are set according to the return value
|
||||
READREG macro
|
||||
rol.w #8,\3
|
||||
move.w \1(\2),\3
|
||||
@@ -61,6 +65,9 @@ SETREG macro
|
||||
;\1 register offset (e.g. ESTAT)
|
||||
;\2 address register of board I/O base (e.g. a0)
|
||||
;\3 destination register to be written (e.g. d0)
|
||||
;
|
||||
;important: when changing this, make sure the flags
|
||||
;are set according to the return value
|
||||
READREG macro
|
||||
move.w \1(\2),\3
|
||||
endm
|
||||
|
||||
Executable
+606
@@ -0,0 +1,606 @@
|
||||
/* ------------------------------------------------------------------------------ */
|
||||
/* | Lowlevel Access to memory mapped ENC624J600 in PSP mode | */
|
||||
/* | Henryk Richter <henryk.richter@gmx.net> | */
|
||||
/* ------------------------------------------------------------------------------ */
|
||||
/* register definition section */
|
||||
#ifndef _REGISTERS_H_
|
||||
#define _REGISTERS_H_
|
||||
|
||||
/* set/clr register offsets */
|
||||
#define SET_OFFSET 0x0100
|
||||
#define CLR_OFFSET 0x0180
|
||||
|
||||
/* Register definitions */
|
||||
|
||||
/* SPI Bank 0 registers -------- */
|
||||
#define ETXST 0x7E00
|
||||
#define ETXSTL 0x7E00
|
||||
#define ETXSTH 0x7E01
|
||||
#define ETXLEN 0x7E02
|
||||
#define ETXLENL 0x7E02
|
||||
#define ETXLENH 0x7E03
|
||||
#define ERXST 0x7E04
|
||||
#define ERXSTL 0x7E04
|
||||
#define ERXSTH 0x7E05
|
||||
#define ERXTAIL 0x7E06
|
||||
#define ERXTAILL 0x7E06
|
||||
#define ERXTAILH 0x7E07
|
||||
#define ERXHEAD 0x7E08
|
||||
#define ERXHEADL 0x7E08
|
||||
#define ERXHEADH 0x7E09
|
||||
#define EDMAST 0x7E0A
|
||||
#define EDMASTL 0x7E0A
|
||||
#define EDMASTH 0x7E0B
|
||||
#define EDMALEN 0x7E0C
|
||||
#define EDMALENL 0x7E0C
|
||||
#define EDMALENH 0x7E0D
|
||||
#define EDMADST 0x7E0E
|
||||
#define EDMADSTL 0x7E0E
|
||||
#define EDMADSTH 0x7E0F
|
||||
#define EDMACS 0x7E10
|
||||
#define EDMACSL 0x7E10
|
||||
#define EDMACSH 0x7E11
|
||||
#define ETXSTAT 0x7E12
|
||||
#define ETXSTATL 0x7E12
|
||||
#define ETXSTATH 0x7E13
|
||||
#define ETXWIRE 0x7E14
|
||||
#define ETXWIREL 0x7E14
|
||||
#define ETXWIREH 0x7E15
|
||||
|
||||
/* SPI all bank registers */
|
||||
#define EUDAST 0x7E16
|
||||
#define EUDASTL 0x7E16
|
||||
#define EUDASTH 0x7E17
|
||||
#define EUDAND 0x7E18
|
||||
#define EUDANDL 0x7E18
|
||||
#define EUDANDH 0x7E19
|
||||
#define ESTAT 0x7E1A
|
||||
#define ESTATL 0x7E1A
|
||||
#define ESTATH 0x7E1B
|
||||
#define EIR 0x7E1C
|
||||
#define EIRL 0x7E1C
|
||||
#define EIRH 0x7E1D
|
||||
#define ECON1 0x7E1E
|
||||
#define ECON1L 0x7E1E
|
||||
#define ECON1H 0x7E1F
|
||||
|
||||
|
||||
/* SPI Bank 1 registers ----- */
|
||||
#define EHT1 0x7E20
|
||||
#define EHT1L 0x7E20
|
||||
#define EHT1H 0x7E21
|
||||
#define EHT2 0x7E22
|
||||
#define EHT2L 0x7E22
|
||||
#define EHT2H 0x7E23
|
||||
#define EHT3 0x7E24
|
||||
#define EHT3L 0x7E24
|
||||
#define EHT3H 0x7E25
|
||||
#define EHT4 0x7E26
|
||||
#define EHT4L 0x7E26
|
||||
#define EHT4H 0x7E27
|
||||
#define EPMM1 0x7E28
|
||||
#define EPMM1L 0x7E28
|
||||
#define EPMM1H 0x7E29
|
||||
#define EPMM2 0x7E2A
|
||||
#define EPMM2L 0x7E2A
|
||||
#define EPMM2H 0x7E2B
|
||||
#define EPMM3 0x7E2C
|
||||
#define EPMM3L 0x7E2C
|
||||
#define EPMM3H 0x7E2D
|
||||
#define EPMM4 0x7E2E
|
||||
#define EPMM4L 0x7E2E
|
||||
#define EPMM4H 0x7E2F
|
||||
#define EPMCS 0x7E30
|
||||
#define EPMCSL 0x7E30
|
||||
#define EPMCSH 0x7E31
|
||||
#define EPMO 0x7E32
|
||||
#define EPMOL 0x7E32
|
||||
#define EPMOH 0x7E33
|
||||
#define ERXFCON 0x7E34
|
||||
#define ERXFCONL 0x7E34
|
||||
#define ERXFCONH 0x7E35
|
||||
|
||||
/* SPI all bank registers from 0x36 to 0x3F */
|
||||
/* SPI Bank 2 registers ----- */
|
||||
#define MACON1 0x7E40
|
||||
#define MACON1L 0x7E40
|
||||
#define MACON1H 0x7E41
|
||||
#define MACON2 0x7E42
|
||||
#define MACON2L 0x7E42
|
||||
#define MACON2H 0x7E43
|
||||
#define MABBIPG 0x7E44
|
||||
#define MABBIPGL 0x7E44
|
||||
#define MABBIPGH 0x7E45
|
||||
#define MAIPG 0x7E46
|
||||
#define MAIPGL 0x7E46
|
||||
#define MAIPGH 0x7E47
|
||||
#define MACLCON 0x7E48
|
||||
#define MACLCONL 0x7E48
|
||||
#define MACLCONH 0x7E49
|
||||
#define MAMXFL 0x7E4A
|
||||
#define MAMXFLL 0x7E4A
|
||||
#define MAMXFLH 0x7E4B
|
||||
#define MICMD 0x7E52
|
||||
#define MICMDL 0x7E52
|
||||
#define MICMDH 0x7E53
|
||||
#define MIREGADR 0x7E54
|
||||
#define MIREGADRL 0x7E54
|
||||
#define MIREGADRH 0x7E55
|
||||
|
||||
/* SPI all bank registers from 0x56 to 0x5F */
|
||||
/* SPI Bank 3 registers ----- */
|
||||
#define MAADR3 0x7E60
|
||||
#define MAADR3L 0x7E60
|
||||
#define MAADR3H 0x7E61
|
||||
#define MAADR2 0x7E62
|
||||
#define MAADR2L 0x7E62
|
||||
#define MAADR2H 0x7E63
|
||||
#define MAADR1 0x7E64
|
||||
#define MAADR1L 0x7E64
|
||||
#define MAADR1H 0x7E65
|
||||
#define MIWR 0x7E66
|
||||
#define MIWRL 0x7E66
|
||||
#define MIWRH 0x7E67
|
||||
#define MIRD 0x7E68
|
||||
#define MIRDL 0x7E68
|
||||
#define MIRDH 0x7E69
|
||||
#define MISTAT 0x7E6A
|
||||
#define MISTATL 0x7E6A
|
||||
#define MISTATH 0x7E6B
|
||||
#define EPAUS 0x7E6C
|
||||
#define EPAUSL 0x7E6C
|
||||
#define EPAUSH 0x7E6D
|
||||
#define ECON2 0x7E6E
|
||||
#define ECON2L 0x7E6E
|
||||
#define ECON2H 0x7E6F
|
||||
#define ERXWM 0x7E70
|
||||
#define ERXWML 0x7E70
|
||||
#define ERXWMH 0x7E71
|
||||
#define EIE 0x7E72
|
||||
#define EIEL 0x7E72
|
||||
#define EIEH 0x7E73
|
||||
#define EIDLED 0x7E74
|
||||
#define EIDLEDL 0x7E74
|
||||
#define EIDLEDH 0x7E75
|
||||
|
||||
/* SPI all bank registers from 0x66 to 0x6F */
|
||||
|
||||
/* SPI Non-banked Special Function Registers */
|
||||
#define EGPDATA 0x7E80
|
||||
#define EGPDATAL 0x7E80
|
||||
#define ERXDATA 0x7E82
|
||||
#define ERXDATAL 0x7E82
|
||||
#define EUDADATA 0x7E84
|
||||
#define EUDADATAL 0x7E84
|
||||
#define EGPRDPT 0x7E86
|
||||
#define EGPRDPTL 0x7E86
|
||||
#define EGPRDPTH 0x7E87
|
||||
#define EGPWRPT 0x7E88
|
||||
#define EGPWRPTL 0x7E88
|
||||
#define EGPWRPTH 0x7E89
|
||||
#define ERXRDPT 0x7E8A
|
||||
#define ERXRDPTL 0x7E8A
|
||||
#define ERXRDPTH 0x7E8B
|
||||
#define ERXWRPT 0x7E8C
|
||||
#define ERXWRPTL 0x7E8C
|
||||
#define ERXWRPTH 0x7E8D
|
||||
#define EUDARDPT 0x7E8E
|
||||
#define EUDARDPTL 0x7E8E
|
||||
#define EUDARDPTH 0x7E8F
|
||||
#define EUDAWRPT 0x7E90
|
||||
#define EUDAWRPTL 0x7E90
|
||||
#define EUDAWRPTH 0x7E91
|
||||
|
||||
/* ;;;;;;;;;;;;;;;;;;;;;;;;; */
|
||||
/* ENC424J600/624J600 register bits */
|
||||
/* ;;;;;;;;;;;;;;;;;;;;;;;;; */
|
||||
/* ESTAT bits ---------- */
|
||||
#define ESTAT_INT (1<<15)
|
||||
#define ESTAT_FCIDLE (1<<14)
|
||||
#define ESTAT_RXBUSY (1<<13)
|
||||
#define ESTAT_CLKRDY (1<<12)
|
||||
#define ESTAT_RSTDONE (1<<11)
|
||||
#define ESTAT_PHYDPX (1<<10)
|
||||
#define ESTAT_PHYRDY (1<<9)
|
||||
#define ESTAT_PHYLNK (1<<8)
|
||||
#define ESTAT_PKTCNT7 (1<<7)
|
||||
#define ESTAT_PKTCNT6 (1<<6)
|
||||
#define ESTAT_PKTCNT5 (1<<5)
|
||||
#define ESTAT_PKTCNT4 (1<<4)
|
||||
#define ESTAT_PKTCNT3 (1<<3)
|
||||
#define ESTAT_PKTCNT2 (1<<2)
|
||||
#define ESTAT_PKTCNT1 (1<<1)
|
||||
#define ESTAT_PKTCNT0 (1)
|
||||
|
||||
/* EIR bits ------------ */
|
||||
#define EIR_CRYPTEN (1<<15)
|
||||
#define EIR_MODEXIF (1<<14)
|
||||
#define EIR_HASHIF (1<<13)
|
||||
#define EIR_AESIF (1<<12)
|
||||
#define EIR_LINKIF (1<<11)
|
||||
#define EIR_PRDYIF (1<<10)
|
||||
#define EIR_r9 (1<<9)
|
||||
#define EIR_r8 (1<<8)
|
||||
#define EIR_r7 (1<<7)
|
||||
#define EIR_PKTIF (1<<6)
|
||||
#define EIR_DMAIF (1<<5)
|
||||
#define EIR_r4 (1<<4)
|
||||
#define EIR_TXIF (1<<3)
|
||||
#define EIR_TXABTIF (1<<2)
|
||||
#define EIR_RXABTIF (1<<1)
|
||||
#define EIR_PCFULIF (1)
|
||||
|
||||
/* ECON1 bits ---------- */
|
||||
#define ECON1_MODEXST (1<<15)
|
||||
#define ECON1_HASHEN (1<<14)
|
||||
#define ECON1_HASHOP (1<<13)
|
||||
#define ECON1_HASHLST (1<<12)
|
||||
#define ECON1_AESST (1<<11)
|
||||
#define ECON1_AESOP1 (1<<10)
|
||||
#define ECON1_AESOP0 (1<<9)
|
||||
#define ECON1_PKTDEC (1<<8)
|
||||
#define ECON1_FCOP1 (1<<7)
|
||||
#define ECON1_FCOP0 (1<<6)
|
||||
#define ECON1_DMAST (1<<5)
|
||||
#define ECON1_DMACPY (1<<4)
|
||||
#define ECON1_DMACSSD (1<<3)
|
||||
#define ECON1_DMANOCS (1<<2)
|
||||
#define ECON1_TXRTS (1<<1)
|
||||
#define ECON1_RXEN (1)
|
||||
|
||||
/* ETXSTAT bits -------- */
|
||||
#define ETXSTAT_r12 (1<<12)
|
||||
#define ETXSTAT_r11 (1<<11)
|
||||
#define ETXSTAT_LATECOL (1<<10)
|
||||
#define ETXSTAT_MAXCOL (1<<9)
|
||||
#define ETXSTAT_EXDEFER (1<<8)
|
||||
#define ETXSTAT_DEFER (1<<7)
|
||||
#define ETXSTAT_r6 (1<<6)
|
||||
#define ETXSTAT_r5 (1<<5)
|
||||
#define ETXSTAT_CRCBAD (1<<4)
|
||||
#define ETXSTAT_COLCNT3 (1<<3)
|
||||
#define ETXSTAT_COLCNT2 (1<<2)
|
||||
#define ETXSTAT_COLCNT1 (1<<1)
|
||||
#define ETXSTAT_COLCNT0 (1)
|
||||
|
||||
/* ERXFCON bits -------- */
|
||||
#define ERXFCON_HTEN (1<<15)
|
||||
#define ERXFCON_MPEN (1<<14)
|
||||
#define ERXFCON_NOTPM (1<<12)
|
||||
#define ERXFCON_PMEN3 (1<<11)
|
||||
#define ERXFCON_PMEN2 (1<<10)
|
||||
#define ERXFCON_PMEN1 (1<<9)
|
||||
#define ERXFCON_PMEN0 (1<<8)
|
||||
#define ERXFCON_CRCEEN (1<<7)
|
||||
#define ERXFCON_CRCEN (1<<6)
|
||||
#define ERXFCON_RUNTEEN (1<<5)
|
||||
#define ERXFCON_RUNTEN (1<<4)
|
||||
#define ERXFCON_UCEN (1<<3)
|
||||
#define ERXFCON_NOTMEEN (1<<2)
|
||||
#define ERXFCON_MCEN (1<<1)
|
||||
#define ERXFCON_BCEN (1)
|
||||
|
||||
/* MACON1 bits --------- */
|
||||
#define MACON1_r15 (1<<15)
|
||||
#define MACON1_r14 (1<<14)
|
||||
#define MACON1_r11 (1<<11)
|
||||
#define MACON1_r10 (1<<10)
|
||||
#define MACON1_r9 (1<<9)
|
||||
#define MACON1_r8 (1<<8)
|
||||
#define MACON1_LOOPBK (1<<4)
|
||||
#define MACON1_r3 (1<<3)
|
||||
#define MACON1_RXPAUS (1<<2)
|
||||
#define MACON1_PASSALL (1<<1)
|
||||
#define MACON1_r0 (1)
|
||||
|
||||
/* MACON2 bits --------- */
|
||||
#define MACON2_DEFER (1<<14)
|
||||
#define MACON2_BPEN (1<<13)
|
||||
#define MACON2_NOBKOFF (1<<12)
|
||||
#define MACON2_r9 (1<<9)
|
||||
#define MACON2_r8 (1<<8)
|
||||
#define MACON2_PADCFG2 (1<<7)
|
||||
#define MACON2_PADCFG1 (1<<6)
|
||||
#define MACON2_PADCFG0 (1<<5)
|
||||
#define MACON2_TXCRCEN (1<<4)
|
||||
#define MACON2_PHDREN (1<<3)
|
||||
#define MACON2_HFRMEN (1<<2)
|
||||
#define MACON2_r1 (1<<1)
|
||||
#define MACON2_FULDPX (1)
|
||||
|
||||
/* MABBIPG bits -------- */
|
||||
#define MABBIPG_BBIPG6 (1<<6)
|
||||
#define MABBIPG_BBIPG5 (1<<5)
|
||||
#define MABBIPG_BBIPG4 (1<<4)
|
||||
#define MABBIPG_BBIPG3 (1<<3)
|
||||
#define MABBIPG_BBIPG2 (1<<2)
|
||||
#define MABBIPG_BBIPG1 (1<<1)
|
||||
#define MABBIPG_BBIPG0 (1)
|
||||
|
||||
/* MAIPG bits ---------- */
|
||||
#define MAIPG_r14 (1<<14)
|
||||
#define MAIPG_r13 (1<<13)
|
||||
#define MAIPG_r12 (1<<12)
|
||||
#define MAIPG_r11 (1<<11)
|
||||
#define MAIPG_r10 (1<<10)
|
||||
#define MAIPG_r9 (1<<9)
|
||||
#define MAIPG_r8 (1<<8)
|
||||
#define MAIPG_IPG6 (1<<6)
|
||||
#define MAIPG_IPG5 (1<<5)
|
||||
#define MAIPG_IPG4 (1<<4)
|
||||
#define MAIPG_IPG3 (1<<3)
|
||||
#define MAIPG_IPG2 (1<<2)
|
||||
#define MAIPG_IPG1 (1<<1)
|
||||
#define MAIPG_IPG0 (1)
|
||||
|
||||
/* MACLCON bits -------- */
|
||||
#define MACLCON_r13 (1<<13)
|
||||
#define MACLCON_r12 (1<<12)
|
||||
#define MACLCON_r11 (1<<11)
|
||||
#define MACLCON_r10 (1<<10)
|
||||
#define MACLCON_r9 (1<<9)
|
||||
#define MACLCON_r8 (1<<8)
|
||||
#define MACLCON_MAXRET3 (1<<3)
|
||||
#define MACLCON_MAXRET2 (1<<2)
|
||||
#define MACLCON_MAXRET1 (1<<1)
|
||||
#define MACLCON_MAXRET0 (1)
|
||||
|
||||
/* MICMD bits ---------- */
|
||||
#define MICMD_MIISCAN (1<<1)
|
||||
#define MICMD_MIIRD (1)
|
||||
|
||||
/* MIREGADR bits ------- */
|
||||
#define MIREGADR_r12 (1<<12)
|
||||
#define MIREGADR_r11 (1<<11)
|
||||
#define MIREGADR_r10 (1<<10)
|
||||
#define MIREGADR_r9 (1<<9)
|
||||
#define MIREGADR_r8 (1<<8)
|
||||
#define MIREGADR_PHREG4 (1<<4)
|
||||
#define MIREGADR_PHREG3 (1<<3)
|
||||
#define MIREGADR_PHREG2 (1<<2)
|
||||
#define MIREGADR_PHREG1 (1<<1)
|
||||
#define MIREGADR_PHREG0 (1)
|
||||
|
||||
/* MISTAT bits --------- */
|
||||
#define MISTAT_r3 (1<<3)
|
||||
#define MISTAT_NVALID (1<<2)
|
||||
#define MISTAT_SCAN (1<<1)
|
||||
#define MISTAT_BUSY (1)
|
||||
|
||||
/* ECON2 bits ---------- */
|
||||
#define ECON2_ETHEN (1<<15)
|
||||
#define ECON2_STRCH (1<<14)
|
||||
#define ECON2_TXMAC (1<<13)
|
||||
#define ECON2_SHA1MD5 (1<<12)
|
||||
#define ECON2_COCON3 (1<<11)
|
||||
#define ECON2_COCON2 (1<<10)
|
||||
#define ECON2_COCON1 (1<<9)
|
||||
#define ECON2_COCON0 (1<<8)
|
||||
#define ECON2_AUTOFC (1<<7)
|
||||
#define ECON2_TXRST (1<<6)
|
||||
#define ECON2_RXRST (1<<5)
|
||||
#define ECON2_ETHRST (1<<4)
|
||||
#define ECON2_MODLEN1 (1<<3)
|
||||
#define ECON2_MODLEN0 (1<<2)
|
||||
#define ECON2_AESLEN1 (1<<1)
|
||||
#define ECON2_AESLEN0 (1)
|
||||
|
||||
/* ERXWM bits ---------- */
|
||||
#define ERXWM_RXFWM7 (1<<15)
|
||||
#define ERXWM_RXFWM6 (1<<14)
|
||||
#define ERXWM_RXFWM5 (1<<13)
|
||||
#define ERXWM_RXFWM4 (1<<12)
|
||||
#define ERXWM_RXFWM3 (1<<11)
|
||||
#define ERXWM_RXFWM2 (1<<10)
|
||||
#define ERXWM_RXFWM1 (1<<9)
|
||||
#define ERXWM_RXFWM0 (1<<8)
|
||||
#define ERXWM_RXEWM7 (1<<7)
|
||||
#define ERXWM_RXEWM6 (1<<6)
|
||||
#define ERXWM_RXEWM5 (1<<5)
|
||||
#define ERXWM_RXEWM4 (1<<4)
|
||||
#define ERXWM_RXEWM3 (1<<3)
|
||||
#define ERXWM_RXEWM2 (1<<2)
|
||||
#define ERXWM_RXEWM1 (1<<1)
|
||||
#define ERXWM_RXEWM0 (1)
|
||||
|
||||
/* EIE bits ------------ */
|
||||
#define EIE_INTIE (1<<15)
|
||||
#define EIE_MODEXIE (1<<14)
|
||||
#define EIE_HASHIE (1<<13)
|
||||
#define EIE_AESIE (1<<12)
|
||||
#define EIE_LINKIE (1<<11)
|
||||
#define EIE_PRDYIE (1<<10)
|
||||
#define EIE_r9 (1<<9)
|
||||
#define EIE_r8 (1<<8)
|
||||
#define EIE_r7 (1<<7)
|
||||
#define EIE_PKTIE (1<<6)
|
||||
#define EIE_DMAIE (1<<5)
|
||||
#define EIE_r4 (1<<4)
|
||||
#define EIE_TXIE (1<<3)
|
||||
#define EIE_TXABTIE (1<<2)
|
||||
#define EIE_RXABTIE (1<<1)
|
||||
#define EIE_PCFULIE (1)
|
||||
|
||||
/* EIDLED bits --------- */
|
||||
#define EIDLED_LACFG3 (1<<15)
|
||||
#define EIDLED_LACFG2 (1<<14)
|
||||
#define EIDLED_LACFG1 (1<<13)
|
||||
#define EIDLED_LACFG0 (1<<12)
|
||||
#define EIDLED_LBCFG3 (1<<11)
|
||||
#define EIDLED_LBCFG2 (1<<10)
|
||||
#define EIDLED_LBCFG1 (1<<9)
|
||||
#define EIDLED_LBCFG0 (1<<8)
|
||||
#define EIDLED_DEVID2 (1<<7)
|
||||
#define EIDLED_DEVID1 (1<<6)
|
||||
#define EIDLED_DEVID0 (1<<5)
|
||||
#define EIDLED_REVID4 (1<<4)
|
||||
#define EIDLED_REVID3 (1<<3)
|
||||
#define EIDLED_REVID2 (1<<2)
|
||||
#define EIDLED_REVID1 (1<<1)
|
||||
#define EIDLED_REVID0 (1)
|
||||
|
||||
/* PHCON1 bits --------- */
|
||||
#define PHCON1_PRST (1<<15)
|
||||
#define PHCON1_PLOOPBK (1<<14)
|
||||
#define PHCON1_SPD100 (1<<13)
|
||||
#define PHCON1_ANEN (1<<12)
|
||||
#define PHCON1_PSLEEP (1<<11)
|
||||
#define PHCON1_r10 (1<<10)
|
||||
#define PHCON1_RENEG (1<<9)
|
||||
#define PHCON1_PFULDPX (1<<8)
|
||||
#define PHCON1_r7 (1<<7)
|
||||
#define PHCON1_r6 (1<<6)
|
||||
#define PHCON1_r5 (1<<5)
|
||||
#define PHCON1_r4 (1<<4)
|
||||
#define PHCON1_r3 (1<<3)
|
||||
#define PHCON1_r2 (1<<2)
|
||||
#define PHCON1_r1 (1<<1)
|
||||
#define PHCON1_r0 (1)
|
||||
|
||||
/* PHSTAT1 bits -------- */
|
||||
#define PHSTAT1_r15 (1<<15)
|
||||
#define PHSTAT1_FULL100 (1<<14)
|
||||
#define PHSTAT1_HALF100 (1<<13)
|
||||
#define PHSTAT1_FULL10 (1<<12)
|
||||
#define PHSTAT1_HALF10 (1<<11)
|
||||
#define PHSTAT1_r10 (1<<10)
|
||||
#define PHSTAT1_r9 (1<<9)
|
||||
#define PHSTAT1_r8 (1<<8)
|
||||
#define PHSTAT1_r7 (1<<7)
|
||||
#define PHSTAT1_r6 (1<<6)
|
||||
#define PHSTAT1_ANDONE (1<<5)
|
||||
#define PHSTAT1_LRFAULT (1<<4)
|
||||
#define PHSTAT1_ANABLE (1<<3)
|
||||
#define PHSTAT1_LLSTAT (1<<2)
|
||||
#define PHSTAT1_r1 (1<<1)
|
||||
#define PHSTAT1_EXTREGS (1)
|
||||
|
||||
/* PHANA bits ---------- */
|
||||
#define PHANA_ADNP (1<<15)
|
||||
#define PHANA_r14 (1<<14)
|
||||
#define PHANA_ADFAULT (1<<13)
|
||||
#define PHANA_r12 (1<<12)
|
||||
#define PHANA_ADPAUS1 (1<<11)
|
||||
#define PHANA_ADPAUS0 (1<<10)
|
||||
#define PHANA_r9 (1<<9)
|
||||
#define PHANA_AD100FD (1<<8)
|
||||
#define PHANA_AD100 (1<<7)
|
||||
#define PHANA_AD10FD (1<<6)
|
||||
#define PHANA_AD10 (1<<5)
|
||||
#define PHANA_ADIEEE4 (1<<4)
|
||||
#define PHANA_ADIEEE3 (1<<3)
|
||||
#define PHANA_ADIEEE2 (1<<2)
|
||||
#define PHANA_ADIEEE1 (1<<1)
|
||||
#define PHANA_ADIEEE0 (1)
|
||||
|
||||
/* PHANLPA bits -------- */
|
||||
#define PHANLPA_LPNP (1<<15)
|
||||
#define PHANLPA_LPACK (1<<14)
|
||||
#define PHANLPA_LPFAULT (1<<13)
|
||||
#define PHANLPA_r12 (1<<12)
|
||||
#define PHANLPA_LPPAUS1 (1<<11)
|
||||
#define PHANLPA_LPPAUS0 (1<<10)
|
||||
#define PHANLPA_LP100T4 (1<<9)
|
||||
#define PHANLPA_LP100FD (1<<8)
|
||||
#define PHANLPA_LP100 (1<<7)
|
||||
#define PHANLPA_LP10FD (1<<6)
|
||||
#define PHANLPA_LP10 (1<<5)
|
||||
#define PHANLPA_LPIEEE4 (1<<4)
|
||||
#define PHANLPA_LPIEEE3 (1<<3)
|
||||
#define PHANLPA_LPIEEE2 (1<<2)
|
||||
#define PHANLPA_LPIEEE1 (1<<1)
|
||||
#define PHANLPA_LPIEEE0 (1)
|
||||
|
||||
/* PHANE bits ---------- */
|
||||
#define PHANE_r15 (1<<15)
|
||||
#define PHANE_r14 (1<<14)
|
||||
#define PHANE_r13 (1<<13)
|
||||
#define PHANE_r12 (1<<12)
|
||||
#define PHANE_r11 (1<<11)
|
||||
#define PHANE_r10 (1<<10)
|
||||
#define PHANE_r9 (1<<9)
|
||||
#define PHANE_r8 (1<<8)
|
||||
#define PHANE_r7 (1<<7)
|
||||
#define PHANE_r6 (1<<6)
|
||||
#define PHANE_r5 (1<<5)
|
||||
#define PHANE_PDFLT (1<<4)
|
||||
#define PHANE_r3 (1<<3)
|
||||
#define PHANE_r2 (1<<2)
|
||||
#define PHANE_LPARCD (1<<1)
|
||||
#define PHANA_LPANABL (1)
|
||||
|
||||
/* PHCON2 bits --------- */
|
||||
#define PHCON2_r15 (1<<15)
|
||||
#define PHCON2_r14 (1<<14)
|
||||
#define PHCON2_EDPWRDN (1<<13)
|
||||
#define PHCON2_r12 (1<<12)
|
||||
#define PHCON2_EDTHRES (1<<11)
|
||||
#define PHCON2_r10 (1<<10)
|
||||
#define PHCON2_r9 (1<<9)
|
||||
#define PHCON2_r8 (1<<8)
|
||||
#define PHCON2_r7 (1<<7)
|
||||
#define PHCON2_r6 (1<<6)
|
||||
#define PHCON2_r5 (1<<5)
|
||||
#define PHCON2_r4 (1<<4)
|
||||
#define PHCON2_r3 (1<<3)
|
||||
#define PHCON2_FRCLNK (1<<2)
|
||||
#define PHCON2_EDSTAT (1<<1)
|
||||
#define PHCON2_r0 (1)
|
||||
|
||||
/* PHSTAT2 bits --------- */
|
||||
#define PHSTAT2_r15 (1<<15)
|
||||
#define PHSTAT2_r14 (1<<14)
|
||||
#define PHSTAT2_r13 (1<<13)
|
||||
#define PHSTAT2_r12 (1<<12)
|
||||
#define PHSTAT2_r11 (1<<11)
|
||||
#define PHSTAT2_r10 (1<<10)
|
||||
#define PHSTAT2_r9 (1<<9)
|
||||
#define PHSTAT2_r8 (1<<8)
|
||||
#define PHSTAT2_r7 (1<<7)
|
||||
#define PHSTAT2_r6 (1<<6)
|
||||
#define PHSTAT2_r5 (1<<5)
|
||||
#define PHSTAT2_PLRITY (1<<4)
|
||||
#define PHSTAT2_r3 (1<<3)
|
||||
#define PHSTAT2_r2 (1<<2)
|
||||
#define PHSTAT2_r1 (1<<1)
|
||||
#define PHSTAT2_r0 (1)
|
||||
|
||||
/* PHSTAT3 bits -------- */
|
||||
#define PHSTAT3_r15 (1<<15)
|
||||
#define PHSTAT3_r14 (1<<14)
|
||||
#define PHSTAT3_r13 (1<<13)
|
||||
#define PHSTAT3_r12 (1<<12)
|
||||
#define PHSTAT3_r11 (1<<11)
|
||||
#define PHSTAT3_r10 (1<<10)
|
||||
#define PHSTAT3_r9 (1<<9)
|
||||
#define PHSTAT3_r8 (1<<8)
|
||||
#define PHSTAT3_r7 (1<<7)
|
||||
#define PHSTAT3_r6 (1<<6)
|
||||
#define PHSTAT3_r5 (1<<5)
|
||||
#define PHSTAT3_SPDDPX2 (1<<4)
|
||||
#define PHSTAT3_SPDDPX1 (1<<3)
|
||||
#define PHSTAT3_SPDDPX0 (1<<2)
|
||||
#define PHSTAT3_r1 (1<<1)
|
||||
#define PHSTAT3_r0 (1)
|
||||
|
||||
/* ------------------------------ internal defaults ---------------------------------- */
|
||||
/* 33.333Mhz clock out frequency */
|
||||
#define CLOCK_33_CLR (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) /* clr mask */
|
||||
#define CLOCK_33_SET (ECON2_COCON0) /* set mask */
|
||||
/* 25 MHz */
|
||||
#define CLOCK_25_CLR (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) /* clr mask */
|
||||
#define CLOCK_25_SET (ECON2_COCON1) /* set mask */
|
||||
/* 20 MHz */
|
||||
#define CLOCK_20_CLR (ECON2_COCON3|ECON2_COCON2) /* clr mask */
|
||||
#define CLOCK_20_SET (ECON2_COCON1|ECON2_COCON0) /* set mask */
|
||||
/* 16 MHz */
|
||||
#define CLOCK_16_CLR (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) /* clr mask */
|
||||
#define CLOCK_16_SET (ECON2_COCON2) /* set mask */
|
||||
/* 4 MHz (after reset) */
|
||||
#define CLOCK_4_CLR (ECON2_COCON2) /* clr mask */
|
||||
#define CLOCK_4_SET (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) /* set mask */
|
||||
|
||||
#define CLOCK_DEF_CLR CLOCK_33_CLR
|
||||
#define CLOCK_DEF_SET CLOCK_33_SET
|
||||
|
||||
#endif /* _REGISTERS_H_ */
|
||||
@@ -58,5 +58,7 @@ GLOBAL REGARGS void hw_config_update(struct PLIPBase *pb, struct TemplateConfig
|
||||
GLOBAL REGARGS void hw_config_dump(struct PLIPBase *pb);
|
||||
GLOBAL REGARGS void hw_enable_global_int(struct PLIPBase *pb);
|
||||
GLOBAL REGARGS void hw_disable_global_int(struct PLIPBase *pb);
|
||||
GLOBAL REGARGS void hw_check_link_change(struct PLIPBase *pb);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Binary file not shown.
+22
-13
@@ -185,6 +185,8 @@ PRIVATE REGARGS VOID dos2reqs(BASEPTR);
|
||||
}
|
||||
/*E*/
|
||||
|
||||
/* moved this function out to hw.c for the ENC624 variant */
|
||||
#ifndef ENC624_OPT
|
||||
/*
|
||||
** writing packets
|
||||
*/
|
||||
@@ -230,6 +232,8 @@ PRIVATE REGARGS VOID dos2reqs(BASEPTR);
|
||||
return rc;
|
||||
}
|
||||
/*E*/
|
||||
#endif /* ENC624_OPT */
|
||||
|
||||
/*F*/ PRIVATE REGARGS VOID dowritereqs(BASEPTR)
|
||||
{
|
||||
struct IOSana2Req *currentwrite, *nextwrite;
|
||||
@@ -237,9 +241,15 @@ PRIVATE REGARGS VOID dos2reqs(BASEPTR);
|
||||
|
||||
ObtainSemaphore(&pb->pb_WriteListSem);
|
||||
|
||||
#if 0
|
||||
/* test only */
|
||||
currentwrite = (struct IOSana2Req *)pb->pb_WriteList.lh_Head;
|
||||
if( currentwrite->ios2_Req.io_Message.mn_Node.ln_Succ )
|
||||
#else
|
||||
for(currentwrite = (struct IOSana2Req *)pb->pb_WriteList.lh_Head;
|
||||
nextwrite = (struct IOSana2Req *) currentwrite->ios2_Req.io_Message.mn_Node.ln_Succ;
|
||||
currentwrite = nextwrite )
|
||||
#endif
|
||||
{
|
||||
code = write_frame(pb, currentwrite);
|
||||
|
||||
@@ -352,11 +362,11 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
{
|
||||
LONG datasize;
|
||||
struct IOSana2Req *got;
|
||||
ULONG pkttyp = 0; /* just to avoid warning with opt build, irrelevant otherwise */
|
||||
ULONG pkttyp;
|
||||
BOOL rv,ok;
|
||||
struct HWFrame *frame = pb->pb_Frame;
|
||||
|
||||
/* while(hw_recv_pending(pb)){*/
|
||||
/* while(hw_recv_pending(pb)){ */
|
||||
while(1){
|
||||
/* if(1){ */
|
||||
d8(("+hw_recv\n"));
|
||||
@@ -368,7 +378,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
|
||||
pkttyp = frame->hwf_Type;
|
||||
|
||||
#if 0
|
||||
#if 0
|
||||
/* perform internal loop back of magic packets of type 0xfffd */
|
||||
if(pkttyp == HW_MAGIC_LOOPBACK) {
|
||||
d(("loop back packet (size %ld)\n",frame->hwf_Size));
|
||||
@@ -382,7 +392,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
hw_send_magic_pkt(pb, HW_MAGIC_ONLINE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
datasize = frame->hwf_Size - HW_ETH_HDR_SIZE;
|
||||
|
||||
@@ -441,7 +451,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
dotracktype(pb, pkttyp, 0, 0, 0, 0, 1);
|
||||
d(("packet thrown away...\n"));
|
||||
}
|
||||
got = NULL;
|
||||
/* got = NULL; */
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -459,6 +469,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
}
|
||||
/*E*/
|
||||
|
||||
|
||||
/*
|
||||
** 2nd level device command dispatcher (~SANA2IOF_QUICK)
|
||||
*/
|
||||
@@ -476,12 +487,6 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
*/
|
||||
while(ios2 = (struct IOSana2Req *)GetMsg(pb->pb_ServerPort))
|
||||
{
|
||||
if (hw_recv_pending(pb))
|
||||
{
|
||||
d(("incoming data!"));
|
||||
break;
|
||||
}
|
||||
|
||||
d(("sana2req %ld from serverport\n", ios2->ios2_Req.io_Command));
|
||||
|
||||
switch (ios2->ios2_Req.io_Command)
|
||||
@@ -683,7 +688,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
|
||||
if (init(pb))
|
||||
{
|
||||
ULONG recv=0, portsigmask, recvsigmask, wmask,specialmask;
|
||||
ULONG recv, portsigmask, recvsigmask, wmask,specialmask;
|
||||
LONG haverec;
|
||||
BOOL running;
|
||||
struct IOSana2Req *wr;
|
||||
@@ -719,10 +724,14 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
||||
/* if no recv is pending then wait for incoming signals */
|
||||
haverec = hw_recv_pending(pb);
|
||||
recv = 0;
|
||||
if( !haverec )
|
||||
if( !haverec ) /* if( (!haverec) && (!wr->ios2_Req.io_Message.mn_Node.ln_Succ) ) */
|
||||
{
|
||||
d2(("**> wait\n"));
|
||||
hw_enable_global_int(pb);
|
||||
|
||||
/* we've got some spare time here: check for link change condition */
|
||||
hw_check_link_change(pb);
|
||||
|
||||
recv = Wait(wmask);
|
||||
d2(("**> wait: got 0x%08lx\n", recv));
|
||||
/*haverec = hw_recv_pending(pb);*/
|
||||
|
||||
@@ -10,14 +10,18 @@
|
||||
#
|
||||
DEVICE_DATE = 16.04.2018
|
||||
DEVICE_VERSION = 0
|
||||
DEVICE_REVISION = 2
|
||||
DEVICE_REVISION = 3
|
||||
|
||||
# see below for EXTRAOBJ, disable for plipbox, enable for sdnet/enc624j6net
|
||||
HWSRCDIR = enc624j6net
|
||||
DEVICE_NAME = enc624j6net
|
||||
DEFS = DEFINE PROTO_ENC624NET=1
|
||||
|
||||
# quick hack/test to write directly - didn't work out for me
|
||||
# direct SANA-II to HW Write without intermediate buffer
|
||||
# don`t enable on current (Feb2018) CPLD, byte swap issue
|
||||
# JIC after 25-Apr-2018 will fix the byte swap on byte write
|
||||
#DEFINE ENC624_OPT=1
|
||||
# quick hack/test to write directly - didn't work out well for me
|
||||
#DEFINE DIRECT_WRITE=1
|
||||
|
||||
#####################################################################
|
||||
@@ -133,6 +137,8 @@ BUILDDEPS=libsize.auto.i $(DEVINFO_INC) $(DEVINFO_HINC)
|
||||
#
|
||||
.c.opt$(SUFFIX): $(BUILDDEPS)
|
||||
$(CC) $(OPTCFLAGS) OBJECTNAME $@ $*.c
|
||||
# DISASM $@.disas.s
|
||||
|
||||
#
|
||||
# assemble a file
|
||||
#
|
||||
|
||||
@@ -46,8 +46,18 @@ PRIVATE struct TrackRec *findtracktype(BASEPTR, ULONG type);
|
||||
tr = (struct TrackRec *) tr->tr_Link.mln_Succ)
|
||||
{
|
||||
if( tr->tr_PacketType == type )
|
||||
{
|
||||
#if 0
|
||||
/* simple MTF for PacketType search */
|
||||
if( (struct Node*)tr != pb->pb_TrackList.lh_Head )
|
||||
{
|
||||
Remove( (struct Node*)tr );
|
||||
AddHead( (struct List*)&pb->pb_TrackList, (struct Node*)tr );
|
||||
}
|
||||
#endif
|
||||
return( tr );
|
||||
}
|
||||
}
|
||||
|
||||
return( NULL );
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user