Where is the bug?

This commit is contained in:
MHeinrichs
2017-01-07 22:38:11 +01:00
parent 3eb6ab740e
commit cd4fb86c55
77 changed files with 31363 additions and 15394 deletions
+4 -2
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Dec 29 14:55:23 2016">
<application name="pn" timeStamp="Sat Jan 07 22:34:21 2017">
<section name="Project Information" visible="false">
<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -33,8 +33,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
<property name="PROP_FitterOptimization" value="Density" type="process"/>
<property name="PROP_xcpldFitDesPtermLmt_xc9500" value="10" type="process"/>
<property name="PROP_xstSafeImplement" value="Yes" type="process"/>
<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
<property name="PROP_DevDevice" value="xc95288xl" type="design"/>
<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
<property name="PROP_DevPackage" value="TQ144" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>