Where is the bug?
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@@ -3,7 +3,7 @@
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pn" timeStamp="Thu Dec 29 14:55:23 2016">
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<application name="pn" timeStamp="Sat Jan 07 22:34:21 2017">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
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<property name="ProjectIteration" value="0" type="project"/>
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@@ -33,8 +33,10 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
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<property name="PROP_AutoTop" value="true" type="design"/>
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<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
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<property name="PROP_FitterOptimization" value="Density" type="process"/>
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<property name="PROP_xcpldFitDesPtermLmt_xc9500" value="10" type="process"/>
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<property name="PROP_xstSafeImplement" value="Yes" type="process"/>
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<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
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<property name="PROP_DevDevice" value="xc95288xl" type="design"/>
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<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
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<property name="PROP_DevPackage" value="TQ144" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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