Byteswap disabled
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@@ -11,6 +11,9 @@
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">DQ<5></arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P38</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DS0</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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@@ -26,7 +29,7 @@
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">Z3</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ<8></arg> to allow all signals assigned to this function block to be placed.
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<msg type="warning" file="Cpld" num="1239" delta="new" >The global <arg fmt="%s" index="1">clock</arg> designation (BUFG) on signal '<arg fmt="%s" index="2">N66</arg>' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal.
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</msg>
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</messages>
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@@ -8,5 +8,8 @@
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" into library work</arg>
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</msg>
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</messages>
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@@ -5,6 +5,9 @@
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="Xst" num="2679" delta="new" >Register <<arg fmt="%s" index="1">lan_adr_sw</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> has a constant value of <arg fmt="%s" index="3">0</arg> during circuit operation. The register is replaced by logic.
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</msg>
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<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
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</msg>
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