OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...

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MHeinrichs

2017-01-26 22:24:01 +01:00

parent 9d64477682

commit c5e1b0debd

47 changed files with 9515 additions and 9811 deletions

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Logic/LAN_IDE/xst/work/sub00/vhpl00.vho

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Logic/LAN_IDE/xst/work/sub00/vhpl01.vho

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