OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...

This commit is contained in:
MHeinrichs
2017-01-26 22:24:01 +01:00
parent 9d64477682
commit c5e1b0debd
47 changed files with 9515 additions and 9811 deletions
+1 -1
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Jan 26 22:00:46 2017">
<application name="pn" timeStamp="Thu Jan 26 22:15:57 2017">
<section name="Project Information" visible="false">
<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>