Dominick.Vansevenant/Zorro-LAN-IDE
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...

Browse Source
This commit is contained in:
MHeinrichs
2017-01-26 22:24:01 +01:00
parent 9d64477682
commit c5e1b0debd
47 changed files with 9515 additions and 9811 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE/pinlist.ucf
+8 -1
View File
@@ -117,4 +117,11 @@ NET "ROM_OE" LOC = "P35" ;
NET "RW" LOC = "P83" ;
NET "SLAVE" LOC = "P106" ;
NET "UDS" LOC = "P81" ;
NET "Z3" LOC = "P79" ;
NET "Z3" LOC = "P79" ;
#Created by Constraints Editor (xc95288xl-tq144-10) - 2017/01/26
NET "CLK_EXT" TNM_NET = CLK_EXT;
TIMESPEC TS_CLK_EXT = PERIOD "CLK_EXT" 33 MHz HIGH 50%;
NET "C1" TNM_NET = C1;
TIMESPEC TS_C1 = PERIOD "C1" 3.5 MHz HIGH 50%;
NET "C3" TNM_NET = C3;
TIMESPEC TS_C3 = PERIOD "C3" 3.5 MHz HIGH 50%;