OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...

2017-01-26 22:24:01 +01:00
parent 9d64477682
commit c5e1b0debd
47 changed files with 9515 additions and 9811 deletions
@@ -8,8 +8,5 @@
 <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->

 <messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd&quot; into library work</arg>
-</msg>
-
 </messages>