OK Clock is 33MHz but the timing to AmigaCLK cannot be convertet 1:1...

This commit is contained in:
MHeinrichs
2017-01-26 22:24:01 +01:00
parent 9d64477682
commit c5e1b0debd
47 changed files with 9515 additions and 9811 deletions
+1 -1
View File
@@ -231,7 +231,7 @@ begin
if(reset ='0') then
LAN_INT_ENABLE <='0';
elsif falling_edge(AMIGA_CLK) then
if(lan_adr = '1' and AS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
LAN_INT_ENABLE <= D(15);
end if;
end if;