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Replace legacy LAN design with Pico 2 W Clockport project

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yannick
2026-10-05 22:46:10 +02:00
parent f8dc4383d2
commit c50dc04cb0
266 changed files with 784353 additions and 189801 deletions
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Pico2W-Clockport-Version/kicad/Gerbers.zip
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/DPACK.kicad_mod
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/HC18U-V.kicad_mod
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/HC49UP.kicad_mod
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/SQFP-S-10X10-64.kicad_mod
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/TQFP144.kicad_mod
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F.pretty/TSSOP20.kicad_mod
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(at 2.925 3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "8b80ee6f-2352-4c78-a1b6-fdf2d0362e4a")
)
(pad "11" smd rect
(at 2.925 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "b393c81f-2ead-47ba-9d63-d2708bbee542")
)
(pad "12" smd rect
(at 2.275 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "e7a94f68-3877-4c02-88f5-5f76a39e5e35")
)
(pad "13" smd rect
(at 1.625 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "32601f35-075b-4dc8-8fe0-f8f71d85915b")
)
(pad "14" smd rect
(at 0.975 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "5caca25a-0e48-4cef-9df0-e351fbced9e2")
)
(pad "15" smd rect
(at 0.325 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "30e8e05f-bb01-41dd-b460-57785f2d1d24")
)
(pad "16" smd rect
(at -0.325 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "584b7588-584f-4544-a6a2-8ea21081dfcd")
)
(pad "17" smd rect
(at -0.975 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "e24ad478-8131-4150-9379-e1439713c57e")
)
(pad "18" smd rect
(at -1.625 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "5df56d91-a33e-4d79-aae2-2921aa5f3085")
)
(pad "19" smd rect
(at -2.275 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "7a5c0530-9765-41a2-888d-d86864e024b9")
)
(pad "20" smd rect
(at -2.925 -3)
(size 0.3 1)
(layers "F.Cu" "F.Mask" "F.Paste")
(solder_mask_margin 0.075)
(solder_paste_margin 0)
(thermal_bridge_angle 0)
(uuid "152e7575-53f9-408e-b8a0-6357431dc396")
)
(embedded_fonts no)
)
Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F_1.kicad_sch
+21136
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F_2.kicad_sch
+12806
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Pico2W-Clockport-Version/kicad/ZORRO-LAN-IDE-CP-V2F_3.kicad_sch
+13051
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Pico2W-Clockport-Version/kicad/ZORRO-PICO2W-CP-cache.lib
+95
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# PICO2W_CLOCKPORT
#
DEF PICO2W_CLOCKPORT PICO 0 40 Y Y 1 F N
F0 "PICO" 0 1150 60 H V C CNN
F1 "Raspberry Pi Pico 2 W" 0 1050 60 H V C CNN
F2 "MCU_RaspberryPi_and_Boards:RPi_Pico_SMD_TH" 0 0 50 H I C CNN
DRAW
S -450 950 450 -950 0 1 12 f
X GP0 1 -650 800 200 R 45 45 1 1 B
X GP1 2 -650 700 200 R 45 45 1 1 B
X GP2 4 -650 600 200 R 45 45 1 1 B
X GP3 5 -650 500 200 R 45 45 1 1 B
X GP4 6 -650 400 200 R 45 45 1 1 B
X GP5 7 -650 300 200 R 45 45 1 1 B
X GP6 9 -650 200 200 R 45 45 1 1 B
X GP7 10 -650 100 200 R 45 45 1 1 B
X GP8 11 -650 -50 200 R 45 45 1 1 I
X GP9 12 -650 -150 200 R 45 45 1 1 I
X GP10 14 -650 -250 200 R 45 45 1 1 I
X GP11 15 -650 -350 200 R 45 45 1 1 I
X GP12_CS 16 -650 -450 200 R 45 45 1 1 I
X GP13_WE 17 -650 -550 200 R 45 45 1 1 I
X GP14_RD 19 -650 -650 200 R 45 45 1 1 I
X GP15_RST 20 -650 -750 200 R 45 45 1 1 I
X GP18_IRQ 24 650 250 200 L 45 45 1 1 O
X VSYS_5V 39 650 800 200 L 45 45 1 1 W
X 3V3 36 650 700 200 L 45 45 1 1 w
X GND 38 650 600 200 L 45 45 1 1 W
ENDDRAW
ENDDEF
#
# LVC8T245
#
DEF LVC8T245 U 0 40 Y Y 1 F N
F0 "U" 0 750 60 H V C CNN
F1 "SN74LVC8T245" 0 650 60 H V C CNN
F2 "Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm" 0 0 50 H I C CNN
DRAW
S -350 550 350 -550 0 1 12 f
X A1 3 -550 400 200 R 45 45 1 1 B
X A2 4 -550 300 200 R 45 45 1 1 B
X A3 5 -550 200 200 R 45 45 1 1 B
X A4 6 -550 100 200 R 45 45 1 1 B
X A5 7 -550 0 200 R 45 45 1 1 B
X A6 8 -550 -100 200 R 45 45 1 1 B
X A7 9 -550 -200 200 R 45 45 1 1 B
X A8 10 -550 -300 200 R 45 45 1 1 B
X B1 21 550 400 200 L 45 45 1 1 B
X B2 20 550 300 200 L 45 45 1 1 B
X B3 19 550 200 200 L 45 45 1 1 B
X B4 18 550 100 200 L 45 45 1 1 B
X B5 17 550 0 200 L 45 45 1 1 B
X B6 16 550 -100 200 L 45 45 1 1 B
X B7 15 550 -200 200 L 45 45 1 1 B
X B8 14 550 -300 200 L 45 45 1 1 B
X DIR 2 -550 -450 200 R 45 45 1 1 I
X ~OE 22 550 -450 200 L 45 45 1 1 I
X VCCA 1 0 750 200 D 45 45 1 1 W
X VCCB 24 150 750 200 D 45 45 1 1 W
X GND 12 0 -750 200 U 45 45 1 1 W
ENDDRAW
ENDDEF
#
# INV1
#
DEF INV1 U 0 40 Y Y 1 F N
F0 "U" 0 250 60 H V C CNN
F1 "SN74LVC1G04" 0 150 60 H V C CNN
F2 "Package_TO_SOT_SMD:SOT-23" 0 0 50 H I C CNN
DRAW
P 4 0 1 12 -100 150 -100 -150 150 0 -100 150 f
X A 1 -300 0 200 R 45 45 1 1 I
X Y 3 350 0 200 L 45 45 1 1 O
X GND 2 0 -350 200 U 45 45 1 1 W
X VCC 5 0 350 200 D 45 45 1 1 W
ENDDRAW
ENDDEF
#
# NMOS_IRQ
#
DEF NMOS_IRQ Q 0 40 Y Y 1 F N
F0 "Q" 0 250 60 H V C CNN
F1 "2N7002" 0 150 60 H V C CNN
F2 "Package_TO_SOT_SMD:SOT-23" 0 0 50 H I C CNN
DRAW
S -100 100 100 -100 0 1 10 f
X G 1 -300 0 200 R 45 45 1 1 I
X S 2 0 -300 200 U 45 45 1 1 P
X D 3 0 300 200 D 45 45 1 1 P
ENDDRAW
ENDDEF
#End Library
Pico2W-Clockport-Version/kicad/ZORRO-PICO2W-CP.sch
+323
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@@ -0,0 +1,323 @@
EESchema Schematic File Version 4
LIBS:ZORRO-PICO2W-CP-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
Sheet 1 1
Title "Zorro Pico 2 W Clockport Interface"
Comment1 "Pico 2 W replaces LAN/Clockport connector"
Comment2 "SN74LVC8T245 level translation, open-drain IRQ"
$EndDescr
$Comp
L ZORRO-PICO2W-CP-cache:PICO2W_CLOCKPORT PICO1
U 1 1 1
P 9000 3500
F 0 "PICO1" H 9000 4650 60 0000 C CNN
F 1 "Raspberry Pi Pico 2 W" H 9000 4550 60 0000 C CNN
F 2 "MCU_RaspberryPi_and_Boards:RPi_Pico_SMD_TH" H 9000 3500 50 0001 C CNN
1 9000 3500
1 0 0 -1
$EndComp
$Comp
L ZORRO-PICO2W-CP-cache:LVC8T245 U1
U 1 1 2
P 3550 2500
F 0 "U1" H 3550 3250 60 0000 C CNN
F 1 "SN74LVC8T245 DATA" H 3550 3150 60 0000 C CNN
1 3550 2500
1 0 0 -1
$EndComp
$Comp
L ZORRO-PICO2W-CP-cache:LVC8T245 U2
U 1 1 3
P 3550 5200
F 0 "U2" H 3550 5950 60 0000 C CNN
F 1 "SN74LVC8T245 CONTROL" H 3550 5850 60 0000 C CNN
1 3550 5200
1 0 0 -1
$EndComp
$Comp
L ZORRO-PICO2W-CP-cache:INV1 U3
U 1 1 4
P 5300 6450
F 0 "U3" H 5300 6800 60 0000 C CNN
F 1 "SN74LVC1G04" H 5300 6700 60 0000 C CNN
1 5300 6450
1 0 0 -1
$EndComp
$Comp
L ZORRO-PICO2W-CP-cache:NMOS_IRQ Q3
U 1 1 5
P 7000 6450
F 0 "Q3" H 7000 6800 60 0000 C CNN
F 1 "2N7002" H 7000 6700 60 0000 C CNN
1 7000 6450
1 0 0 -1
$EndComp
Text Notes 1200 1150 0 100 ~ 20
ZORRO CLOCKPORT SIDE (5 V LOGIC)
Text Notes 7700 1150 0 100 ~ 20
PICO 2 W SIDE (3.3 V LOGIC)
Text Notes 1150 7050 0 60 ~ 12
U1: bidirectional data buffer, OE=CP_CS, DIR=not CP_WE. U2: Clockport inputs to Pico GPIO.
Text Notes 1150 7200 0 60 ~ 12
Q3 provides an open-drain CP_IRQ output. R11 is a 1 kΩ pull-up to +5V.
Wire Wire Line
2800 2900 3000 2900
Text Label 2800 2900 0 50 ~ 0
DQ0
Wire Wire Line
2800 2800 3000 2800
Text Label 2800 2800 0 50 ~ 0
DQ1
Wire Wire Line
2800 2700 3000 2700
Text Label 2800 2700 0 50 ~ 0
DQ2
Wire Wire Line
2800 2600 3000 2600
Text Label 2800 2600 0 50 ~ 0
DQ3
Wire Wire Line
2800 2500 3000 2500
Text Label 2800 2500 0 50 ~ 0
DQ4
Wire Wire Line
2800 2400 3000 2400
Text Label 2800 2400 0 50 ~ 0
DQ5
Wire Wire Line
2800 2300 3000 2300
Text Label 2800 2300 0 50 ~ 0
DQ6
Wire Wire Line
2800 2200 3000 2200
Text Label 2800 2200 0 50 ~ 0
DQ7
Wire Wire Line
4100 2900 4300 2900
Text Label 4300 2900 2 50 ~ 0
PICO_D0
Wire Wire Line
4100 2800 4300 2800
Text Label 4300 2800 2 50 ~ 0
PICO_D1
Wire Wire Line
4100 2700 4300 2700
Text Label 4300 2700 2 50 ~ 0
PICO_D2
Wire Wire Line
4100 2600 4300 2600
Text Label 4300 2600 2 50 ~ 0
PICO_D3
Wire Wire Line
4100 2500 4300 2500
Text Label 4300 2500 2 50 ~ 0
PICO_D4
Wire Wire Line
4100 2400 4300 2400
Text Label 4300 2400 2 50 ~ 0
PICO_D5
Wire Wire Line
4100 2300 4300 2300
Text Label 4300 2300 2 50 ~ 0
PICO_D6
Wire Wire Line
4100 2200 4300 2200
Text Label 4300 2200 2 50 ~ 0
PICO_D7
Wire Wire Line
2800 2050 3000 2050
Text Label 2800 2050 0 50 ~ 0
CP_DIR
Wire Wire Line
4100 2050 4300 2050
Text Label 4300 2050 2 50 ~ 0
CP_CS
Wire Wire Line
2800 5600 3000 5600
Text Label 2800 5600 0 50 ~ 0
LAN_A3
Wire Wire Line
2800 5500 3000 5500
Text Label 2800 5500 0 50 ~ 0
LAN_A4
Wire Wire Line
2800 5400 3000 5400
Text Label 2800 5400 0 50 ~ 0
LAN_A5
Wire Wire Line
2800 5300 3000 5300
Text Label 2800 5300 0 50 ~ 0
LAN_A6
Wire Wire Line
2800 5200 3000 5200
Text Label 2800 5200 0 50 ~ 0
CP_CS
Wire Wire Line
2800 5100 3000 5100
Text Label 2800 5100 0 50 ~ 0
CP_WE
Wire Wire Line
2800 5000 3000 5000
Text Label 2800 5000 0 50 ~ 0
CP_RD
Wire Wire Line
2800 4900 3000 4900
Text Label 2800 4900 0 50 ~ 0
IDE_RST
Wire Wire Line
4100 5600 4300 5600
Text Label 4300 5600 2 50 ~ 0
PICO_A2
Wire Wire Line
4100 5500 4300 5500
Text Label 4300 5500 2 50 ~ 0
PICO_A3
Wire Wire Line
4100 5400 4300 5400
Text Label 4300 5400 2 50 ~ 0
PICO_A4
Wire Wire Line
4100 5300 4300 5300
Text Label 4300 5300 2 50 ~ 0
PICO_A5
Wire Wire Line
4100 5200 4300 5200
Text Label 4300 5200 2 50 ~ 0
PICO_CS
Wire Wire Line
4100 5100 4300 5100
Text Label 4300 5100 2 50 ~ 0
PICO_WE
Wire Wire Line
4100 5000 4300 5000
Text Label 4300 5000 2 50 ~ 0
PICO_RD
Wire Wire Line
4100 4900 4300 4900
Text Label 4300 4900 2 50 ~ 0
PICO_RESET
Wire Wire Line
8150 4300 8350 4300
Text Label 8150 4300 0 50 ~ 0
PICO_D0
Wire Wire Line
8150 4200 8350 4200
Text Label 8150 4200 0 50 ~ 0
PICO_D1
Wire Wire Line
8150 4100 8350 4100
Text Label 8150 4100 0 50 ~ 0
PICO_D2
Wire Wire Line
8150 4000 8350 4000
Text Label 8150 4000 0 50 ~ 0
PICO_D3
Wire Wire Line
8150 3900 8350 3900
Text Label 8150 3900 0 50 ~ 0
PICO_D4
Wire Wire Line
8150 3800 8350 3800
Text Label 8150 3800 0 50 ~ 0
PICO_D5
Wire Wire Line
8150 3700 8350 3700
Text Label 8150 3700 0 50 ~ 0
PICO_D6
Wire Wire Line
8150 3600 8350 3600
Text Label 8150 3600 0 50 ~ 0
PICO_D7
Wire Wire Line
8150 3450 8350 3450
Text Label 8150 3450 0 50 ~ 0
PICO_A2
Wire Wire Line
8150 3350 8350 3350
Text Label 8150 3350 0 50 ~ 0
PICO_A3
Wire Wire Line
8150 3250 8350 3250
Text Label 8150 3250 0 50 ~ 0
PICO_A4
Wire Wire Line
8150 3150 8350 3150
Text Label 8150 3150 0 50 ~ 0
PICO_A5
Wire Wire Line
8150 3050 8350 3050
Text Label 8150 3050 0 50 ~ 0
PICO_CS
Wire Wire Line
8150 2950 8350 2950
Text Label 8150 2950 0 50 ~ 0
PICO_WE
Wire Wire Line
8150 2850 8350 2850
Text Label 8150 2850 0 50 ~ 0
PICO_RD
Wire Wire Line
8150 2750 8350 2750
Text Label 8150 2750 0 50 ~ 0
PICO_RESET
Wire Wire Line
9650 3750 9850 3750
Text Label 9850 3750 2 50 ~ 0
PICO_IRQ
Wire Wire Line
9650 4300 9850 4300
Text Label 9850 4300 2 50 ~ 0
+5V
Wire Wire Line
9650 4200 9850 4200
Text Label 9850 4200 2 50 ~ 0
+3V3
Wire Wire Line
9650 4100 9850 4100
Text Label 9850 4100 2 50 ~ 0
GND
Text Label 3550 1750 1 50 ~ 0
+3V3
Text Label 3700 1750 1 50 ~ 0
+3V3
Text Label 3550 3250 1 50 ~ 0
GND
Text Label 3550 4450 3 50 ~ 0
+3V3
Text Label 3700 4450 3 50 ~ 0
+3V3
Text Label 3550 5950 3 50 ~ 0
GND
Text Label 5300 6100 3 50 ~ 0
+3V3
Text Label 5300 6800 3 50 ~ 0
GND
Text Label 7000 6750 3 50 ~ 0
GND
Wire Wire Line
4800 6450 5000 6450
Text Label 4800 6450 0 50 ~ 0
CP_WE
Wire Wire Line
5650 6450 5850 6450
Text Label 5850 6450 2 50 ~ 0
CP_DIR
Wire Wire Line
6500 6450 6700 6450
Text Label 6500 6450 0 50 ~ 0
PICO_IRQ
Text Label 7000 6150 1 50 ~ 0
CP_IRQ
Text Label 7350 6150 0 50 ~ 0
CP_IRQ
Text Label 7600 6150 0 50 ~ 0
+5V
Text Label 3000 2050 0 50 ~ 0
CP_DIR
Text Label 4100 2050 2 50 ~ 0
CP_CS
Text Notes 7480 6200 0 50 ~ 0
R11 1k pull-up
$EndSCHEMATC
Pico2W-Clockport-Version/kicad/Zorro-Pico2W-Lan.dsn
+2347
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Pico2W-Clockport-Version/kicad/Zorro-Pico2W-Lan.kicad_pcb
+54862
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Pico2W-Clockport-Version/kicad/Zorro-Pico2W-Lan.kicad_pro
+284
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@@ -0,0 +1,284 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 2.54
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpthpad": true,
"td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false,
"td_onvia": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "ZORRO-PICO2W-CP-freerouting-dangling-clean.kicad_pro",
"version": 3
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 4
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}
Pico2W-Clockport-Version/kicad/Zorro-Pico2W-Lan.ses
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Pico2W-Clockport-Version/kicad/create_pico2w_layout.py
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#!/usr/bin/env python3
"""Create a Pico 2 W placement revision from the imported Zorro LAN/IDE board."""
from pathlib import Path
import shutil
import pcbnew
HERE = Path(__file__).resolve().parent
SOURCE = HERE / "ZORRO-LAN-IDE-CP-V2F.kicad_pcb"
TARGET = HERE / "ZORRO-PICO2W-CP.kicad_pcb"
PICO_LIBRARY = "/usr/share/kicad/demos/tiny_tapeout/tinytapeout-kicad-libs/footprints/MCU_RaspberryPi_and_Boards.pretty"
SO_LIBRARY = "/usr/share/kicad/footprints/Package_SO.pretty"
SOT_LIBRARY = "/usr/share/kicad/footprints/Package_TO_SOT_SMD.pretty"
def mm(value):
return pcbnew.FromMM(value)
def point(x, y):
return pcbnew.VECTOR2I(mm(x), mm(y))
def add_footprint(board, library, name, reference, value, x, y, rotation=0):
footprint = pcbnew.FootprintLoad(library, name)
if footprint is None:
raise RuntimeError(f"Cannot load {library}:{name}")
footprint.SetReference(reference)
footprint.SetValue(value)
footprint.SetPosition(point(x, y))
footprint.SetOrientationDegrees(rotation)
board.Add(footprint)
return footprint
def set_net(footprint, pad_number, net):
for pad in footprint.Pads():
if pad.GetNumber() == str(pad_number):
pad.SetNet(net)
def add_text(board, text, x, y, size=1.2):
label = pcbnew.PCB_TEXT(board)
label.SetText(text)
label.SetPosition(point(x, y))
label.SetTextSize(pcbnew.VECTOR2I(mm(size), mm(size)))
label.SetLayer(pcbnew.F_SilkS)
board.Add(label)
def add_net(board, nets, name):
net = pcbnew.NETINFO_ITEM(board, name)
board.Add(net)
nets[name] = net
return net
def pad_position(footprint, number):
"""Return the absolute pad location for a unique footprint pad."""
for pad in footprint.Pads():
if pad.GetNumber() == str(number):
return pad.GetPosition()
raise RuntimeError(f"Pad {number} not found on {footprint.GetReference()}")
def add_route(board, net, coordinates, width=0.20, layer=pcbnew.F_Cu):
"""Add a deliberate Manhattan copper route through the supplied points."""
for start, end in zip(coordinates, coordinates[1:]):
if start == end:
continue
track = pcbnew.PCB_TRACK(board)
track.SetNet(net)
track.SetLayer(layer)
track.SetWidth(mm(width))
track.SetStart(start)
track.SetEnd(end)
board.Add(track)
shutil.copy2(SOURCE, TARGET)
board = pcbnew.LoadBoard(str(TARGET))
if board is None:
raise RuntimeError("KiCad could not load the imported board")
# The converter placed CN1's footprint drawing on Edge.Cuts. Those three
# segments duplicate part of the actual perimeter and make the outline appear
# self-intersecting. Keep them as silkscreen artwork instead.
for footprint in board.GetFootprints():
if footprint.GetReference() == "CN1":
for graphic in footprint.GraphicalItems():
if graphic.GetLayer() == pcbnew.Edge_Cuts:
graphic.SetLayer(pcbnew.F_SilkS)
board_nets = board.GetNetsByName()
nets = {str(name): board_nets[name] for name in board_nets}
for name in (
*(f"PICO_D{index}" for index in range(8)),
"PICO_A2", "PICO_A3", "PICO_A4", "PICO_A5", "PICO_CS", "PICO_WE",
"PICO_RD", "PICO_RESET", "PICO_IRQ", "CP_DIR",
):
add_net(board, nets, name)
def source_pad(reference, number):
for footprint in board.GetFootprints():
if footprint.GetReference() == reference:
return pad_position(footprint, number)
raise RuntimeError(f"Source footprint {reference} not found")
# The direct signal roots at the Zorro glue logic. These replace the removed
# Clockport header endpoints; routing from them avoids any dead-end detour into
# the former connector area.
signal_sources = {
"DQ0": source_pad("IC2", 118), "DQ1": source_pad("IC2", 117),
"DQ2": source_pad("IC2", 120), "DQ3": source_pad("IC2", 119),
"DQ4": source_pad("IC2", 124), "DQ5": source_pad("IC2", 121),
"DQ6": source_pad("IC2", 126), "DQ7": source_pad("IC2", 125),
"LAN_A3": source_pad("IC2", 5), "LAN_A4": source_pad("IC2", 9),
"LAN_A5": source_pad("IC2", 7), "LAN_A6": source_pad("IC2", 11),
"CP_CS": source_pad("IC2", 34), "CP_WE": source_pad("IC2", 70),
"CP_RD": source_pad("IC2", 71), "IDE_RST": source_pad("IC5", 18),
"CP_IRQ": source_pad("IC2", 31),
}
# Pico 2 W uses the same 2x20 castellated pad geometry as Pico W. It is placed
# horizontally in the former LAN/MagJack area, USB toward the right board edge.
pico = add_footprint(board, PICO_LIBRARY, "RPi_Pico_SMD_TH", "PICO1", "Raspberry Pi Pico 2 W", 183.5, 102.0, 90)
mapping = {
1: "PICO_D0", 2: "PICO_D1", 4: "PICO_D2", 5: "PICO_D3", 6: "PICO_D4", 7: "PICO_D5", 9: "PICO_D6", 10: "PICO_D7",
11: "PICO_A2", 12: "PICO_A3", 14: "PICO_A4", 15: "PICO_A5", 16: "PICO_CS",
17: "PICO_WE", 19: "PICO_RD", 20: "PICO_RESET", 24: "PICO_IRQ", 36: "+3V3", 39: "+5V",
}
for pad, name in mapping.items():
set_net(pico, pad, nets[name])
for pad in (3, 8, 13, 18, 23, 28, 38):
set_net(pico, pad, nets["GND"])
# Clockport routing. U1 translates the bidirectional data bus, U2 buffers the
# address/control lines, U3 derives U1's direction, and Q3 drives !INT6 safely.
u1 = add_footprint(board, SO_LIBRARY, "TSSOP-24_4.4x7.8mm_P0.65mm", "U1", "SN74LVC8T245 DATA BUFFER", 150.0, 94.0, 90)
u2 = add_footprint(board, SO_LIBRARY, "TSSOP-24_4.4x7.8mm_P0.65mm", "U2", "SN74LVC8T245 CONTROL BUFFER", 150.0, 104.5, 90)
u3 = add_footprint(board, SOT_LIBRARY, "SOT-23", "U3", "SN74LVC1G04", 153.0, 113.5, 0)
q3 = add_footprint(board, SOT_LIBRARY, "SOT-23", "Q3", "2N7002 !INT6 OPEN DRAIN", 158.0, 116.5, 0)
r11 = next(footprint for footprint in board.GetFootprints() if footprint.GetReference() == "R11")
r11.SetPosition(point(162.5, 116.5))
r11.SetOrientationDegrees(90)
for index, pad in enumerate(range(3, 11)):
set_net(u1, pad, nets[f"DQ{index}"])
for index, pad in enumerate(range(21, 13, -1)):
set_net(u1, pad, nets[f"PICO_D{index}"])
for pad in (1, 23, 24):
set_net(u1, pad, nets["+3V3"])
for pad in (11, 12, 13):
set_net(u1, pad, nets["GND"])
set_net(u1, 2, nets["CP_DIR"])
set_net(u1, 22, nets["CP_CS"])
control_inputs = ("LAN_A3", "LAN_A4", "LAN_A5", "LAN_A6", "CP_CS", "CP_WE", "CP_RD", "IDE_RST")
control_outputs = ("PICO_A2", "PICO_A3", "PICO_A4", "PICO_A5", "PICO_CS", "PICO_WE", "PICO_RD", "PICO_RESET")
for pad, name in zip(range(3, 11), control_inputs):
set_net(u2, pad, nets[name])
for pad, name in zip(range(21, 13, -1), control_outputs):
set_net(u2, pad, nets[name])
for pad in (1, 2, 23, 24):
set_net(u2, pad, nets["+3V3"])
for pad in (11, 12, 13, 22):
set_net(u2, pad, nets["GND"])
set_net(u3, 1, nets["CP_WE"])
set_net(u3, 2, nets["GND"])
set_net(u3, 3, nets["CP_DIR"])
set_net(u3, 5, nets["+3V3"])
set_net(q3, 1, nets["PICO_IRQ"])
set_net(q3, 2, nets["GND"])
set_net(q3, 3, nets["CP_IRQ"])
# Remove only the connector-side copper stubs. The retained portions keep the
# original Zorro circuitry intact, while no selected signal returns to CN2.
def remove_clockport_stubs():
# These branches ended at CN2, IC1, R10, or R11 and otherwise leave visible,
# electrically meaningless DQ stubs such as the old DQ1 run.
routed_nets = set(signal_sources)
for track in list(board.GetTracks()):
# A3-A6 were repurposed as the four Clockport address lines. Every
# other LAN-named net terminated at the omitted ENC controller.
if track.GetNetname().startswith("LAN_") and track.GetNetname() not in {"LAN_A3", "LAN_A4", "LAN_A5", "LAN_A6"}:
board.Remove(track)
continue
if track.GetNetname() in {"N$3", "LAN_A2", "LAN_INT", "LEDA", "LEDAC", "LEDB", "LEDBC"}:
board.Remove(track)
continue
if track.GetNetname() not in routed_nets:
continue
start, end = track.GetStart(), track.GetEnd()
if ((min(start.x, end.x) > mm(155) and max(start.y, end.y) < mm(110)) or
(min(start.y, end.y) < mm(75) and max(start.x, end.x) > mm(150))):
board.Remove(track)
# Route all new logic on F.Cu so it electrically joins the SMD pads. Lanes are
# separated to make the handoff readable.
def route_from_source(net_name, destination, lane_y):
source = signal_sources[net_name]
add_route(board, nets[net_name], [source, point(source.x / 1e6, lane_y),
point(destination.x / 1e6, lane_y), destination])
# Clockport to the A sides of both translators.
for index, name in enumerate(f"DQ{n}" for n in range(8)):
route_from_source(name, pad_position(u1, 3 + index), 91.8 + index * 0.42)
for index, name in enumerate(control_inputs):
route_from_source(name, pad_position(u2, 3 + index), 104.0 + index * 0.42)
route_from_source("CP_CS", pad_position(u1, 22), 90.8)
route_from_source("CP_WE", pad_position(u3, 1), 112.0)
route_from_source("CP_IRQ", pad_position(q3, 3), 114.0)
# Data translator to the Pico data GPIOs (GP0-GP7).
pico_data_pads = (1, 2, 4, 5, 6, 7, 9, 10)
for index, pico_pad in enumerate(pico_data_pads):
start = pad_position(u1, 21 - index)
end = pad_position(pico, pico_pad)
lane_y = 89.0 + index * 0.45
add_route(board, nets[f"PICO_D{index}"], [start, point(start.x / 1e6, lane_y),
point(end.x / 1e6, lane_y), end])
# Control translator to GP8-GP15. The Pico pin numbers skip ground pads.
pico_control_pads = (11, 12, 14, 15, 16, 17, 19, 20)
for index, (name, pico_pad) in enumerate(zip(control_outputs, pico_control_pads)):
start = pad_position(u2, 21 - index)
end = pad_position(pico, pico_pad)
lane_y = 97.5 + index * 0.42
add_route(board, nets[name], [start, point(start.x / 1e6, lane_y),
point(end.x / 1e6, lane_y), end])
# Local direction and interrupt paths.
add_route(board, nets["CP_DIR"], [pad_position(u3, 3), point(156.0, 113.5),
point(156.0, 90.0), pad_position(u1, 2)])
add_route(board, nets["PICO_IRQ"], [pad_position(q3, 1), point(160.0, 115.55),
point(160.0, 96.5), point(200.01, 96.5),
pad_position(pico, 24)])
add_route(board, nets["CP_IRQ"], [pad_position(q3, 3), pad_position(r11, 2)])
add_text(board, "ZORRO PICO 2 W CLOCKPORT", 183.0, 124.0, 1.4)
add_text(board, "PICO USB -> BOARD EDGE", 196.0, 85.0, 0.9)
add_text(board, "NO COPPER UNDER ANTENNA", 159.0, 85.0, 0.9)
add_text(board, "LAN COMPONENTS OMITTED", 183.0, 129.0, 1.0)
# The full ENC624J600/MagJack circuit is not fitted in this revision. Existing
# copper is intentionally retained until the follow-up routing pass so that the
# imported board remains reviewable against the original.
lan_references = {
"CN2", "IC1", "X1", "Q1", "Q2", "C1", "C3", "C4", "C5", "C6", "C7", "C8", "C13", "C18",
"C19", "C24", "C25", "C26", "C27", "C28", "C33", "R4", "R6", "R13",
"R10", "R12", "R14", "R15", "R16", "R17", "R18", "R19", "LEDA", "LEDB", "LEDA0", "LEDB0", "SJ2", "SV1",
}
for footprint in list(board.GetFootprints()):
if footprint.GetReference() in lan_references:
board.Remove(footprint)
remove_clockport_stubs()
pcbnew.SaveBoard(str(TARGET), board)
print(TARGET)
Pico2W-Clockport-Version/kicad/fp-lib-table
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(fp_lib_table
(version 7)
(lib (name "ZORRO-LAN-IDE-CP-V2F")(type "KiCad")(uri "$(KIPRJMOD)/ZORRO-LAN-IDE-CP-V2F.pretty")(options "")(descr ""))
)
Pico2W-Clockport-Version/kicad/sym-lib-table
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(sym_lib_table
(version 7)
(lib (name "ZORRO-PICO2W-CP-cache")(type "Legacy")(uri "${KIPRJMOD}/ZORRO-PICO2W-CP-cache.lib")(options "")(descr "Pico 2W Clockport interface symbols"))
)