alignment bug fixed and asm routines splitted
Revertet server.c to a stable version
This commit is contained in:
MHeinrichs
Binary file not shown.
@@ -11,30 +11,19 @@
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; Note: This code is in some places intentionally saving more registers than
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; Note: This code is in some places intentionally saving more registers than
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; required by the AmigaOS ABI.
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; required by the AmigaOS ABI.
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;
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;
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; HW BUG:
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; possible address line mismatch (see RXSTART_INIT)
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; $5000 was set -> frame appears at $3000
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; $4000 was set -> frame appears at $2000
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; $3000 was set -> frame appears at $5000
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; $2000 was set -> frame appears at $4000
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;
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;
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;TODO:
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;TODO:
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; - setMAC/getMAC endianess awareness
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; - setMAC/getMAC endianess awareness
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; - Pattern Matching, MC/MC filtering: Multicast,Broadcast,Unicast(self),MagicPacket,correct CRC,"not me" Unicast
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; - Pattern Matching, MC/MC filtering: Multicast,Broadcast,Unicast(self),MagicPacket,correct CRC,"not me" Unicast
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; - _enc624j6l_RXReset -> won't recover from totally unresponsive chip (but exits gracefully)
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; - _enc624j6l_RXReset -> won't recover from totally unresponsive chip (but exits gracefully)
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; - put includes out (for now, self-contained ASM file)
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; - RXSTART_INIT = $0c00 -> currently $2000 due to location bug
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; - RXSTART_INIT = $0c00 -> currently $2000 due to location bug
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; enable debugging code block
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include "enc624j6net/registers.i"
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DEBUG EQU 1
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include "enc624j6net/macros.i"
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;
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;------------------ options, some depend on hardware (CPLD) configuration -------------------------
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; enable debugging code block
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_OPT_BUFFER_SWAP EQU 0 ;perform byte swap on buffer ops (1) or assume native endian (0)
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DEBUG EQU 0
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_OPT_REG_SWAP EQU 0 ;perform byte swap on register ops (1) or assume native endian (0)
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;
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_OPT_ADR_QUIRK EQU 0 ;address lines 12/13 are swapped (1) or linear addressing (0)
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_OPT_FLOWCONTROL EQU 0 ;perform flow control on RX (1) or not (0)
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_OPT_RECV EQU 1 ;faster recv (1) or generic (0)
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;
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;
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; options for buffer memory configuration, please reserve some space for private variables
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; options for buffer memory configuration, please reserve some space for private variables
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@@ -128,711 +117,7 @@ _LVOSignal EQU -324
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section code,code
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section code,code
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;------------------------ UGH! this belongs into a proper .i ------------------------------
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; set/clr register offsets
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SET_OFFSET EQU $0100
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CLR_OFFSET EQU $0180
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; Register definitions
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; SPI Bank 0 registers --------
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ETXST EQU $7E00
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ETXSTL EQU $7E00
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ETXSTH EQU $7E01
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ETXLEN EQU $7E02
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ETXLENL EQU $7E02
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ETXLENH EQU $7E03
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ERXST EQU $7E04
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ERXSTL EQU $7E04
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ERXSTH EQU $7E05
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ERXTAIL EQU $7E06
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ERXTAILL EQU $7E06
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ERXTAILH EQU $7E07
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ERXHEAD EQU $7E08
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ERXHEADL EQU $7E08
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ERXHEADH EQU $7E09
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EDMAST EQU $7E0A
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EDMASTL EQU $7E0A
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EDMASTH EQU $7E0B
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EDMALEN EQU $7E0C
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EDMALENL EQU $7E0C
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EDMALENH EQU $7E0D
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EDMADST EQU $7E0E
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EDMADSTL EQU $7E0E
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EDMADSTH EQU $7E0F
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EDMACS EQU $7E10
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EDMACSL EQU $7E10
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EDMACSH EQU $7E11
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ETXSTAT EQU $7E12
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ETXSTATL EQU $7E12
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ETXSTATH EQU $7E13
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ETXWIRE EQU $7E14
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ETXWIREL EQU $7E14
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ETXWIREH EQU $7E15
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; SPI all bank registers
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EUDAST EQU $7E16
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EUDASTL EQU $7E16
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EUDASTH EQU $7E17
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EUDAND EQU $7E18
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EUDANDL EQU $7E18
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EUDANDH EQU $7E19
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ESTAT EQU $7E1A
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ESTATL EQU $7E1A
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ESTATH EQU $7E1B
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EIR EQU $7E1C
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EIRL EQU $7E1C
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EIRH EQU $7E1D
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ECON1 EQU $7E1E
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ECON1L EQU $7E1E
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ECON1H EQU $7E1F
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; SPI Bank 1 registers -----
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EHT1 EQU $7E20
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EHT1L EQU $7E20
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EHT1H EQU $7E21
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EHT2 EQU $7E22
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EHT2L EQU $7E22
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EHT2H EQU $7E23
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EHT3 EQU $7E24
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EHT3L EQU $7E24
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EHT3H EQU $7E25
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EHT4 EQU $7E26
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EHT4L EQU $7E26
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EHT4H EQU $7E27
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EPMM1 EQU $7E28
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EPMM1L EQU $7E28
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EPMM1H EQU $7E29
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EPMM2 EQU $7E2A
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EPMM2L EQU $7E2A
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EPMM2H EQU $7E2B
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EPMM3 EQU $7E2C
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EPMM3L EQU $7E2C
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EPMM3H EQU $7E2D
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EPMM4 EQU $7E2E
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EPMM4L EQU $7E2E
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EPMM4H EQU $7E2F
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EPMCS EQU $7E30
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EPMCSL EQU $7E30
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EPMCSH EQU $7E31
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EPMO EQU $7E32
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EPMOL EQU $7E32
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EPMOH EQU $7E33
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ERXFCON EQU $7E34
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ERXFCONL EQU $7E34
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ERXFCONH EQU $7E35
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; SPI all bank registers from 0x36 to 0x3F
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; SPI Bank 2 registers -----
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MACON1 EQU $7E40
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MACON1L EQU $7E40
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MACON1H EQU $7E41
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MACON2 EQU $7E42
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MACON2L EQU $7E42
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MACON2H EQU $7E43
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MABBIPG EQU $7E44
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MABBIPGL EQU $7E44
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MABBIPGH EQU $7E45
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MAIPG EQU $7E46
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MAIPGL EQU $7E46
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MAIPGH EQU $7E47
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MACLCON EQU $7E48
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MACLCONL EQU $7E48
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MACLCONH EQU $7E49
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MAMXFL EQU $7E4A
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MAMXFLL EQU $7E4A
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MAMXFLH EQU $7E4B
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MICMD EQU $7E52
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MICMDL EQU $7E52
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MICMDH EQU $7E53
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MIREGADR EQU $7E54
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MIREGADRL EQU $7E54
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MIREGADRH EQU $7E55
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; SPI all bank registers from 0x56 to 0x5F
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; SPI Bank 3 registers -----
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MAADR3 EQU $7E60
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MAADR3L EQU $7E60
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MAADR3H EQU $7E61
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MAADR2 EQU $7E62
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MAADR2L EQU $7E62
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MAADR2H EQU $7E63
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MAADR1 EQU $7E64
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MAADR1L EQU $7E64
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MAADR1H EQU $7E65
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MIWR EQU $7E66
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MIWRL EQU $7E66
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MIWRH EQU $7E67
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MIRD EQU $7E68
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MIRDL EQU $7E68
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MIRDH EQU $7E69
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MISTAT EQU $7E6A
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MISTATL EQU $7E6A
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MISTATH EQU $7E6B
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EPAUS EQU $7E6C
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EPAUSL EQU $7E6C
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EPAUSH EQU $7E6D
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ECON2 EQU $7E6E
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ECON2L EQU $7E6E
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ECON2H EQU $7E6F
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ERXWM EQU $7E70
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ERXWML EQU $7E70
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ERXWMH EQU $7E71
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EIE EQU $7E72
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EIEL EQU $7E72
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EIEH EQU $7E73
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EIDLED EQU $7E74
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EIDLEDL EQU $7E74
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EIDLEDH EQU $7E75
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; SPI all bank registers from 0x66 to 0x6F
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; SPI Non-banked Special Function Registers
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EGPDATA EQU $7E80
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EGPDATAL EQU $7E80
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ERXDATA EQU $7E82
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ERXDATAL EQU $7E82
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EUDADATA EQU $7E84
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EUDADATAL EQU $7E84
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EGPRDPT EQU $7E86
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EGPRDPTL EQU $7E86
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EGPRDPTH EQU $7E87
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EGPWRPT EQU $7E88
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EGPWRPTL EQU $7E88
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EGPWRPTH EQU $7E89
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ERXRDPT EQU $7E8A
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ERXRDPTL EQU $7E8A
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ERXRDPTH EQU $7E8B
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ERXWRPT EQU $7E8C
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ERXWRPTL EQU $7E8C
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ERXWRPTH EQU $7E8D
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EUDARDPT EQU $7E8E
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EUDARDPTL EQU $7E8E
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EUDARDPTH EQU $7E8F
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EUDAWRPT EQU $7E90
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EUDAWRPTL EQU $7E90
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EUDAWRPTH EQU $7E91
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;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ENC424J600/624J600 register bits
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;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ESTAT bits ----------
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ESTAT_INT EQU (1<<15)
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ESTAT_FCIDLE EQU (1<<14)
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ESTAT_RXBUSY EQU (1<<13)
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ESTAT_CLKRDY EQU (1<<12)
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ESTAT_RSTDONE EQU (1<<11)
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ESTAT_PHYDPX EQU (1<<10)
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ESTAT_PHYRDY EQU (1<<9)
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ESTAT_PHYLNK EQU (1<<8)
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ESTAT_PKTCNT7 EQU (1<<7)
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ESTAT_PKTCNT6 EQU (1<<6)
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ESTAT_PKTCNT5 EQU (1<<5)
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ESTAT_PKTCNT4 EQU (1<<4)
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ESTAT_PKTCNT3 EQU (1<<3)
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ESTAT_PKTCNT2 EQU (1<<2)
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ESTAT_PKTCNT1 EQU (1<<1)
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ESTAT_PKTCNT0 EQU (1)
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; EIR bits ------------
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EIR_CRYPTEN EQU (1<<15)
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EIR_MODEXIF EQU (1<<14)
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EIR_HASHIF EQU (1<<13)
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EIR_AESIF EQU (1<<12)
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EIR_LINKIF EQU (1<<11)
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EIR_PRDYIF EQU (1<<10)
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EIR_r9 EQU (1<<9)
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EIR_r8 EQU (1<<8)
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EIR_r7 EQU (1<<7)
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EIR_PKTIF EQU (1<<6)
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EIR_DMAIF EQU (1<<5)
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EIR_r4 EQU (1<<4)
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EIR_TXIF EQU (1<<3)
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EIR_TXABTIF EQU (1<<2)
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EIR_RXABTIF EQU (1<<1)
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EIR_PCFULIF EQU (1)
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; ECON1 bits ----------
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ECON1_MODEXST EQU (1<<15)
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ECON1_HASHEN EQU (1<<14)
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ECON1_HASHOP EQU (1<<13)
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ECON1_HASHLST EQU (1<<12)
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ECON1_AESST EQU (1<<11)
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ECON1_AESOP1 EQU (1<<10)
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ECON1_AESOP0 EQU (1<<9)
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ECON1_PKTDEC EQU (1<<8)
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ECON1_FCOP1 EQU (1<<7)
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ECON1_FCOP0 EQU (1<<6)
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ECON1_DMAST EQU (1<<5)
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ECON1_DMACPY EQU (1<<4)
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ECON1_DMACSSD EQU (1<<3)
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ECON1_DMANOCS EQU (1<<2)
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ECON1_TXRTS EQU (1<<1)
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ECON1_RXEN EQU (1)
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; ETXSTAT bits --------
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ETXSTAT_r12 EQU (1<<12)
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ETXSTAT_r11 EQU (1<<11)
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ETXSTAT_LATECOL EQU (1<<10)
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ETXSTAT_MAXCOL EQU (1<<9)
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ETXSTAT_EXDEFER EQU (1<<8)
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ETXSTAT_DEFER EQU (1<<7)
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ETXSTAT_r6 EQU (1<<6)
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ETXSTAT_r5 EQU (1<<5)
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ETXSTAT_CRCBAD EQU (1<<4)
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ETXSTAT_COLCNT3 EQU (1<<3)
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ETXSTAT_COLCNT2 EQU (1<<2)
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ETXSTAT_COLCNT1 EQU (1<<1)
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ETXSTAT_COLCNT0 EQU (1)
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; ERXFCON bits --------
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ERXFCON_HTEN EQU (1<<15)
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ERXFCON_MPEN EQU (1<<14)
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ERXFCON_NOTPM EQU (1<<12)
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ERXFCON_PMEN3 EQU (1<<11)
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ERXFCON_PMEN2 EQU (1<<10)
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ERXFCON_PMEN1 EQU (1<<9)
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ERXFCON_PMEN0 EQU (1<<8)
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ERXFCON_CRCEEN EQU (1<<7)
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ERXFCON_CRCEN EQU (1<<6)
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ERXFCON_RUNTEEN EQU (1<<5)
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ERXFCON_RUNTEN EQU (1<<4)
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ERXFCON_UCEN EQU (1<<3)
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ERXFCON_NOTMEEN EQU (1<<2)
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ERXFCON_MCEN EQU (1<<1)
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ERXFCON_BCEN EQU (1)
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; MACON1 bits ---------
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MACON1_r15 EQU (1<<15)
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MACON1_r14 EQU (1<<14)
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MACON1_r11 EQU (1<<11)
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MACON1_r10 EQU (1<<10)
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MACON1_r9 EQU (1<<9)
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MACON1_r8 EQU (1<<8)
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MACON1_LOOPBK EQU (1<<4)
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MACON1_r3 EQU (1<<3)
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MACON1_RXPAUS EQU (1<<2)
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MACON1_PASSALL EQU (1<<1)
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MACON1_r0 EQU (1)
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; MACON2 bits ---------
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|
||||||
MACON2_DEFER EQU (1<<14)
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|
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MACON2_BPEN EQU (1<<13)
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MACON2_NOBKOFF EQU (1<<12)
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|
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MACON2_r9 EQU (1<<9)
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MACON2_r8 EQU (1<<8)
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|
||||||
MACON2_PADCFG2 EQU (1<<7)
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|
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MACON2_PADCFG1 EQU (1<<6)
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|
||||||
MACON2_PADCFG0 EQU (1<<5)
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||||||
MACON2_TXCRCEN EQU (1<<4)
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|
||||||
MACON2_PHDREN EQU (1<<3)
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MACON2_HFRMEN EQU (1<<2)
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|
||||||
MACON2_r1 EQU (1<<1)
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|
||||||
MACON2_FULDPX EQU (1)
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|
||||||
; MABBIPG bits --------
|
|
||||||
MABBIPG_BBIPG6 EQU (1<<6)
|
|
||||||
MABBIPG_BBIPG5 EQU (1<<5)
|
|
||||||
MABBIPG_BBIPG4 EQU (1<<4)
|
|
||||||
MABBIPG_BBIPG3 EQU (1<<3)
|
|
||||||
MABBIPG_BBIPG2 EQU (1<<2)
|
|
||||||
MABBIPG_BBIPG1 EQU (1<<1)
|
|
||||||
MABBIPG_BBIPG0 EQU (1)
|
|
||||||
|
|
||||||
; MAIPG bits ----------
|
|
||||||
MAIPG_r14 EQU (1<<14)
|
|
||||||
MAIPG_r13 EQU (1<<13)
|
|
||||||
MAIPG_r12 EQU (1<<12)
|
|
||||||
MAIPG_r11 EQU (1<<11)
|
|
||||||
MAIPG_r10 EQU (1<<10)
|
|
||||||
MAIPG_r9 EQU (1<<9)
|
|
||||||
MAIPG_r8 EQU (1<<8)
|
|
||||||
MAIPG_IPG6 EQU (1<<6)
|
|
||||||
MAIPG_IPG5 EQU (1<<5)
|
|
||||||
MAIPG_IPG4 EQU (1<<4)
|
|
||||||
MAIPG_IPG3 EQU (1<<3)
|
|
||||||
MAIPG_IPG2 EQU (1<<2)
|
|
||||||
MAIPG_IPG1 EQU (1<<1)
|
|
||||||
MAIPG_IPG0 EQU (1)
|
|
||||||
|
|
||||||
; MACLCON bits --------
|
|
||||||
MACLCON_r13 EQU (1<<13)
|
|
||||||
MACLCON_r12 EQU (1<<12)
|
|
||||||
MACLCON_r11 EQU (1<<11)
|
|
||||||
MACLCON_r10 EQU (1<<10)
|
|
||||||
MACLCON_r9 EQU (1<<9)
|
|
||||||
MACLCON_r8 EQU (1<<8)
|
|
||||||
MACLCON_MAXRET3 EQU (1<<3)
|
|
||||||
MACLCON_MAXRET2 EQU (1<<2)
|
|
||||||
MACLCON_MAXRET1 EQU (1<<1)
|
|
||||||
MACLCON_MAXRET0 EQU (1)
|
|
||||||
|
|
||||||
; MICMD bits ----------
|
|
||||||
MICMD_MIISCAN EQU (1<<1)
|
|
||||||
MICMD_MIIRD EQU (1)
|
|
||||||
|
|
||||||
; MIREGADR bits -------
|
|
||||||
MIREGADR_r12 EQU (1<<12)
|
|
||||||
MIREGADR_r11 EQU (1<<11)
|
|
||||||
MIREGADR_r10 EQU (1<<10)
|
|
||||||
MIREGADR_r9 EQU (1<<9)
|
|
||||||
MIREGADR_r8 EQU (1<<8)
|
|
||||||
MIREGADR_PHREG4 EQU (1<<4)
|
|
||||||
MIREGADR_PHREG3 EQU (1<<3)
|
|
||||||
MIREGADR_PHREG2 EQU (1<<2)
|
|
||||||
MIREGADR_PHREG1 EQU (1<<1)
|
|
||||||
MIREGADR_PHREG0 EQU (1)
|
|
||||||
|
|
||||||
; MISTAT bits ---------
|
|
||||||
MISTAT_r3 EQU (1<<3)
|
|
||||||
MISTAT_NVALID EQU (1<<2)
|
|
||||||
MISTAT_SCAN EQU (1<<1)
|
|
||||||
MISTAT_BUSY EQU (1)
|
|
||||||
|
|
||||||
; ECON2 bits ----------
|
|
||||||
ECON2_ETHEN EQU (1<<15)
|
|
||||||
ECON2_STRCH EQU (1<<14)
|
|
||||||
ECON2_TXMAC EQU (1<<13)
|
|
||||||
ECON2_SHA1MD5 EQU (1<<12)
|
|
||||||
ECON2_COCON3 EQU (1<<11)
|
|
||||||
ECON2_COCON2 EQU (1<<10)
|
|
||||||
ECON2_COCON1 EQU (1<<9)
|
|
||||||
ECON2_COCON0 EQU (1<<8)
|
|
||||||
ECON2_AUTOFC EQU (1<<7)
|
|
||||||
ECON2_TXRST EQU (1<<6)
|
|
||||||
ECON2_RXRST EQU (1<<5)
|
|
||||||
ECON2_ETHRST EQU (1<<4)
|
|
||||||
ECON2_MODLEN1 EQU (1<<3)
|
|
||||||
ECON2_MODLEN0 EQU (1<<2)
|
|
||||||
ECON2_AESLEN1 EQU (1<<1)
|
|
||||||
ECON2_AESLEN0 EQU (1)
|
|
||||||
|
|
||||||
; ERXWM bits ----------
|
|
||||||
ERXWM_RXFWM7 EQU (1<<15)
|
|
||||||
ERXWM_RXFWM6 EQU (1<<14)
|
|
||||||
ERXWM_RXFWM5 EQU (1<<13)
|
|
||||||
ERXWM_RXFWM4 EQU (1<<12)
|
|
||||||
ERXWM_RXFWM3 EQU (1<<11)
|
|
||||||
ERXWM_RXFWM2 EQU (1<<10)
|
|
||||||
ERXWM_RXFWM1 EQU (1<<9)
|
|
||||||
ERXWM_RXFWM0 EQU (1<<8)
|
|
||||||
ERXWM_RXEWM7 EQU (1<<7)
|
|
||||||
ERXWM_RXEWM6 EQU (1<<6)
|
|
||||||
ERXWM_RXEWM5 EQU (1<<5)
|
|
||||||
ERXWM_RXEWM4 EQU (1<<4)
|
|
||||||
ERXWM_RXEWM3 EQU (1<<3)
|
|
||||||
ERXWM_RXEWM2 EQU (1<<2)
|
|
||||||
ERXWM_RXEWM1 EQU (1<<1)
|
|
||||||
ERXWM_RXEWM0 EQU (1)
|
|
||||||
|
|
||||||
; EIE bits ------------
|
|
||||||
EIE_INTIE EQU (1<<15)
|
|
||||||
EIE_MODEXIE EQU (1<<14)
|
|
||||||
EIE_HASHIE EQU (1<<13)
|
|
||||||
EIE_AESIE EQU (1<<12)
|
|
||||||
EIE_LINKIE EQU (1<<11)
|
|
||||||
EIE_PRDYIE EQU (1<<10)
|
|
||||||
EIE_r9 EQU (1<<9)
|
|
||||||
EIE_r8 EQU (1<<8)
|
|
||||||
EIE_r7 EQU (1<<7)
|
|
||||||
EIE_PKTIE EQU (1<<6)
|
|
||||||
EIE_DMAIE EQU (1<<5)
|
|
||||||
EIE_r4 EQU (1<<4)
|
|
||||||
EIE_TXIE EQU (1<<3)
|
|
||||||
EIE_TXABTIE EQU (1<<2)
|
|
||||||
EIE_RXABTIE EQU (1<<1)
|
|
||||||
EIE_PCFULIE EQU (1)
|
|
||||||
|
|
||||||
; EIDLED bits ---------
|
|
||||||
EIDLED_LACFG3 EQU (1<<15)
|
|
||||||
EIDLED_LACFG2 EQU (1<<14)
|
|
||||||
EIDLED_LACFG1 EQU (1<<13)
|
|
||||||
EIDLED_LACFG0 EQU (1<<12)
|
|
||||||
EIDLED_LBCFG3 EQU (1<<11)
|
|
||||||
EIDLED_LBCFG2 EQU (1<<10)
|
|
||||||
EIDLED_LBCFG1 EQU (1<<9)
|
|
||||||
EIDLED_LBCFG0 EQU (1<<8)
|
|
||||||
EIDLED_DEVID2 EQU (1<<7)
|
|
||||||
EIDLED_DEVID1 EQU (1<<6)
|
|
||||||
EIDLED_DEVID0 EQU (1<<5)
|
|
||||||
EIDLED_REVID4 EQU (1<<4)
|
|
||||||
EIDLED_REVID3 EQU (1<<3)
|
|
||||||
EIDLED_REVID2 EQU (1<<2)
|
|
||||||
EIDLED_REVID1 EQU (1<<1)
|
|
||||||
EIDLED_REVID0 EQU (1)
|
|
||||||
|
|
||||||
; PHCON1 bits ---------
|
|
||||||
PHCON1_PRST EQU (1<<15)
|
|
||||||
PHCON1_PLOOPBK EQU (1<<14)
|
|
||||||
PHCON1_SPD100 EQU (1<<13)
|
|
||||||
PHCON1_ANEN EQU (1<<12)
|
|
||||||
PHCON1_PSLEEP EQU (1<<11)
|
|
||||||
PHCON1_r10 EQU (1<<10)
|
|
||||||
PHCON1_RENEG EQU (1<<9)
|
|
||||||
PHCON1_PFULDPX EQU (1<<8)
|
|
||||||
PHCON1_r7 EQU (1<<7)
|
|
||||||
PHCON1_r6 EQU (1<<6)
|
|
||||||
PHCON1_r5 EQU (1<<5)
|
|
||||||
PHCON1_r4 EQU (1<<4)
|
|
||||||
PHCON1_r3 EQU (1<<3)
|
|
||||||
PHCON1_r2 EQU (1<<2)
|
|
||||||
PHCON1_r1 EQU (1<<1)
|
|
||||||
PHCON1_r0 EQU (1)
|
|
||||||
|
|
||||||
; PHSTAT1 bits --------
|
|
||||||
PHSTAT1_r15 EQU (1<<15)
|
|
||||||
PHSTAT1_FULL100 EQU (1<<14)
|
|
||||||
PHSTAT1_HALF100 EQU (1<<13)
|
|
||||||
PHSTAT1_FULL10 EQU (1<<12)
|
|
||||||
PHSTAT1_HALF10 EQU (1<<11)
|
|
||||||
PHSTAT1_r10 EQU (1<<10)
|
|
||||||
PHSTAT1_r9 EQU (1<<9)
|
|
||||||
PHSTAT1_r8 EQU (1<<8)
|
|
||||||
PHSTAT1_r7 EQU (1<<7)
|
|
||||||
PHSTAT1_r6 EQU (1<<6)
|
|
||||||
PHSTAT1_ANDONE EQU (1<<5)
|
|
||||||
PHSTAT1_LRFAULT EQU (1<<4)
|
|
||||||
PHSTAT1_ANABLE EQU (1<<3)
|
|
||||||
PHSTAT1_LLSTAT EQU (1<<2)
|
|
||||||
PHSTAT1_r1 EQU (1<<1)
|
|
||||||
PHSTAT1_EXTREGS EQU (1)
|
|
||||||
|
|
||||||
; PHANA bits ----------
|
|
||||||
PHANA_ADNP EQU (1<<15)
|
|
||||||
PHANA_r14 EQU (1<<14)
|
|
||||||
PHANA_ADFAULT EQU (1<<13)
|
|
||||||
PHANA_r12 EQU (1<<12)
|
|
||||||
PHANA_ADPAUS1 EQU (1<<11)
|
|
||||||
PHANA_ADPAUS0 EQU (1<<10)
|
|
||||||
PHANA_r9 EQU (1<<9)
|
|
||||||
PHANA_AD100FD EQU (1<<8)
|
|
||||||
PHANA_AD100 EQU (1<<7)
|
|
||||||
PHANA_AD10FD EQU (1<<6)
|
|
||||||
PHANA_AD10 EQU (1<<5)
|
|
||||||
PHANA_ADIEEE4 EQU (1<<4)
|
|
||||||
PHANA_ADIEEE3 EQU (1<<3)
|
|
||||||
PHANA_ADIEEE2 EQU (1<<2)
|
|
||||||
PHANA_ADIEEE1 EQU (1<<1)
|
|
||||||
PHANA_ADIEEE0 EQU (1)
|
|
||||||
|
|
||||||
; PHANLPA bits --------
|
|
||||||
PHANLPA_LPNP EQU (1<<15)
|
|
||||||
PHANLPA_LPACK EQU (1<<14)
|
|
||||||
PHANLPA_LPFAULT EQU (1<<13)
|
|
||||||
PHANLPA_r12 EQU (1<<12)
|
|
||||||
PHANLPA_LPPAUS1 EQU (1<<11)
|
|
||||||
PHANLPA_LPPAUS0 EQU (1<<10)
|
|
||||||
PHANLPA_LP100T4 EQU (1<<9)
|
|
||||||
PHANLPA_LP100FD EQU (1<<8)
|
|
||||||
PHANLPA_LP100 EQU (1<<7)
|
|
||||||
PHANLPA_LP10FD EQU (1<<6)
|
|
||||||
PHANLPA_LP10 EQU (1<<5)
|
|
||||||
PHANLPA_LPIEEE4 EQU (1<<4)
|
|
||||||
PHANLPA_LPIEEE3 EQU (1<<3)
|
|
||||||
PHANLPA_LPIEEE2 EQU (1<<2)
|
|
||||||
PHANLPA_LPIEEE1 EQU (1<<1)
|
|
||||||
PHANLPA_LPIEEE0 EQU (1)
|
|
||||||
|
|
||||||
; PHANE bits ----------
|
|
||||||
PHANE_r15 EQU (1<<15)
|
|
||||||
PHANE_r14 EQU (1<<14)
|
|
||||||
PHANE_r13 EQU (1<<13)
|
|
||||||
PHANE_r12 EQU (1<<12)
|
|
||||||
PHANE_r11 EQU (1<<11)
|
|
||||||
PHANE_r10 EQU (1<<10)
|
|
||||||
PHANE_r9 EQU (1<<9)
|
|
||||||
PHANE_r8 EQU (1<<8)
|
|
||||||
PHANE_r7 EQU (1<<7)
|
|
||||||
PHANE_r6 EQU (1<<6)
|
|
||||||
PHANE_r5 EQU (1<<5)
|
|
||||||
PHANE_PDFLT EQU (1<<4)
|
|
||||||
PHANE_r3 EQU (1<<3)
|
|
||||||
PHANE_r2 EQU (1<<2)
|
|
||||||
PHANE_LPARCD EQU (1<<1)
|
|
||||||
PHANA_LPANABL EQU (1)
|
|
||||||
|
|
||||||
; PHCON2 bits ---------
|
|
||||||
PHCON2_r15 EQU (1<<15)
|
|
||||||
PHCON2_r14 EQU (1<<14)
|
|
||||||
PHCON2_EDPWRDN EQU (1<<13)
|
|
||||||
PHCON2_r12 EQU (1<<12)
|
|
||||||
PHCON2_EDTHRES EQU (1<<11)
|
|
||||||
PHCON2_r10 EQU (1<<10)
|
|
||||||
PHCON2_r9 EQU (1<<9)
|
|
||||||
PHCON2_r8 EQU (1<<8)
|
|
||||||
PHCON2_r7 EQU (1<<7)
|
|
||||||
PHCON2_r6 EQU (1<<6)
|
|
||||||
PHCON2_r5 EQU (1<<5)
|
|
||||||
PHCON2_r4 EQU (1<<4)
|
|
||||||
PHCON2_r3 EQU (1<<3)
|
|
||||||
PHCON2_FRCLNK EQU (1<<2)
|
|
||||||
PHCON2_EDSTAT EQU (1<<1)
|
|
||||||
PHCON2_r0 EQU (1)
|
|
||||||
|
|
||||||
; PHSTAT2 bits ---------
|
|
||||||
PHSTAT2_r15 EQU (1<<15)
|
|
||||||
PHSTAT2_r14 EQU (1<<14)
|
|
||||||
PHSTAT2_r13 EQU (1<<13)
|
|
||||||
PHSTAT2_r12 EQU (1<<12)
|
|
||||||
PHSTAT2_r11 EQU (1<<11)
|
|
||||||
PHSTAT2_r10 EQU (1<<10)
|
|
||||||
PHSTAT2_r9 EQU (1<<9)
|
|
||||||
PHSTAT2_r8 EQU (1<<8)
|
|
||||||
PHSTAT2_r7 EQU (1<<7)
|
|
||||||
PHSTAT2_r6 EQU (1<<6)
|
|
||||||
PHSTAT2_r5 EQU (1<<5)
|
|
||||||
PHSTAT2_PLRITY EQU (1<<4)
|
|
||||||
PHSTAT2_r3 EQU (1<<3)
|
|
||||||
PHSTAT2_r2 EQU (1<<2)
|
|
||||||
PHSTAT2_r1 EQU (1<<1)
|
|
||||||
PHSTAT2_r0 EQU (1)
|
|
||||||
|
|
||||||
; PHSTAT3 bits --------
|
|
||||||
PHSTAT3_r15 EQU (1<<15)
|
|
||||||
PHSTAT3_r14 EQU (1<<14)
|
|
||||||
PHSTAT3_r13 EQU (1<<13)
|
|
||||||
PHSTAT3_r12 EQU (1<<12)
|
|
||||||
PHSTAT3_r11 EQU (1<<11)
|
|
||||||
PHSTAT3_r10 EQU (1<<10)
|
|
||||||
PHSTAT3_r9 EQU (1<<9)
|
|
||||||
PHSTAT3_r8 EQU (1<<8)
|
|
||||||
PHSTAT3_r7 EQU (1<<7)
|
|
||||||
PHSTAT3_r6 EQU (1<<6)
|
|
||||||
PHSTAT3_r5 EQU (1<<5)
|
|
||||||
PHSTAT3_SPDDPX2 EQU (1<<4)
|
|
||||||
PHSTAT3_SPDDPX1 EQU (1<<3)
|
|
||||||
PHSTAT3_SPDDPX0 EQU (1<<2)
|
|
||||||
PHSTAT3_r1 EQU (1<<1)
|
|
||||||
PHSTAT3_r0 EQU (1)
|
|
||||||
|
|
||||||
;------------------------------ internal defaults ----------------------------------
|
|
||||||
;33.333Mhz clock out frequency
|
|
||||||
CLOCK_33_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) ;clr mask
|
|
||||||
CLOCK_33_SET EQU (ECON2_COCON0) ;set mask
|
|
||||||
;25 MHz
|
|
||||||
CLOCK_25_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) ;clr mask
|
|
||||||
CLOCK_25_SET EQU (ECON2_COCON1) ;set mask
|
|
||||||
;20 MHz
|
|
||||||
CLOCK_20_CLR EQU (ECON2_COCON3|ECON2_COCON2) ;clr mask
|
|
||||||
CLOCK_20_SET EQU (ECON2_COCON1|ECON2_COCON0) ;set mask
|
|
||||||
;16 MHz
|
|
||||||
CLOCK_16_CLR EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;clr mask
|
|
||||||
CLOCK_16_SET EQU (ECON2_COCON2) ;set mask
|
|
||||||
;4 MHz (after reset)
|
|
||||||
CLOCK_4_CLR EQU (ECON2_COCON2) ;clr mask
|
|
||||||
CLOCK_4_SET EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;set mask
|
|
||||||
|
|
||||||
CLOCK_DEF_CLR EQU CLOCK_33_CLR
|
|
||||||
CLOCK_DEF_SET EQU CLOCK_33_SET
|
|
||||||
|
|
||||||
;\1 register offset (without CLEAR offset)
|
|
||||||
;\2 address register of board I/O base
|
|
||||||
;\3 register with clear mask
|
|
||||||
ifne _OPT_REG_SWAP
|
|
||||||
|
|
||||||
CLRREG macro
|
|
||||||
rol.w #8,\3
|
|
||||||
move.w \3,\1+CLR_OFFSET(\2)
|
|
||||||
rol.w #8,\3
|
|
||||||
endm
|
|
||||||
;\1 register offset (without SET offset)
|
|
||||||
;\2 address register of board I/O base
|
|
||||||
;\3 register with set mask
|
|
||||||
SETREG macro
|
|
||||||
rol.w #8,\3
|
|
||||||
move.w \3,\1+SET_OFFSET(\2)
|
|
||||||
rol.w #8,\3
|
|
||||||
endm
|
|
||||||
;\1 register offset (e.g. ESTAT)
|
|
||||||
;\2 address register of board I/O base (e.g. a0)
|
|
||||||
;\3 destination register to be written (e.g. d0)
|
|
||||||
READREG macro
|
|
||||||
rol.w #8,\3
|
|
||||||
move.w \1(\2),\3
|
|
||||||
rol.w #8,\3
|
|
||||||
endm
|
|
||||||
;\1 register offset (e.g. ESTAT)
|
|
||||||
;\2 address register of board I/O base (e.g. a0)
|
|
||||||
;\3 soure register copied to HW register (e.g. d0)
|
|
||||||
WRITEREG macro
|
|
||||||
rol.w #8,\3
|
|
||||||
move.w \3,\1(\2)
|
|
||||||
rol.w #8,\3
|
|
||||||
endm
|
|
||||||
|
|
||||||
|
|
||||||
else
|
|
||||||
|
|
||||||
CLRREG macro
|
|
||||||
move.w \3,\1+CLR_OFFSET(\2)
|
|
||||||
endm
|
|
||||||
;\1 register offset (without SET offset)
|
|
||||||
;\2 address register of board I/O base
|
|
||||||
;\3 register with set mask
|
|
||||||
SETREG macro
|
|
||||||
move.w \3,\1+SET_OFFSET(\2)
|
|
||||||
endm
|
|
||||||
;\1 register offset (e.g. ESTAT)
|
|
||||||
;\2 address register of board I/O base (e.g. a0)
|
|
||||||
;\3 destination register to be written (e.g. d0)
|
|
||||||
READREG macro
|
|
||||||
move.w \1(\2),\3
|
|
||||||
endm
|
|
||||||
;\1 register offset (e.g. ESTAT)
|
|
||||||
;\2 address register of board I/O base (e.g. a0)
|
|
||||||
;\3 soure register copied to HW register (e.g. d0)
|
|
||||||
WRITEREG macro
|
|
||||||
move.w \3,\1(\2)
|
|
||||||
endm
|
|
||||||
|
|
||||||
endc
|
|
||||||
|
|
||||||
;read with address shuffling or direct from SRAM (affects $2000-$5000)
|
|
||||||
ifne _OPT_ADR_QUIRK
|
|
||||||
;\1 = address register
|
|
||||||
;\2 = data register, offset
|
|
||||||
;\3 = destination
|
|
||||||
READSRAM macro
|
|
||||||
eor.w #$6000,\2
|
|
||||||
move.w (\1,\2.w),\3
|
|
||||||
eor.w #$6000,\2
|
|
||||||
endm
|
|
||||||
else
|
|
||||||
READSRAM macro
|
|
||||||
move.w (\1,\2),\3
|
|
||||||
endm
|
|
||||||
endc
|
|
||||||
|
|
||||||
;read with address shuffling or direct from SRAM (affects $2000-$5000)
|
|
||||||
ifne _OPT_ADR_QUIRK
|
|
||||||
;\1 = address register
|
|
||||||
;\2 = data register, offset
|
|
||||||
;\3 = destination
|
|
||||||
READSRAM_LONG macro
|
|
||||||
eor.w #$6000,\2
|
|
||||||
move.l (\1,\2.w),\3
|
|
||||||
eor.w #$6000,\2
|
|
||||||
endm
|
|
||||||
else
|
|
||||||
READSRAM_LONG macro
|
|
||||||
move.l (\1,\2),\3
|
|
||||||
endm
|
|
||||||
endc
|
|
||||||
|
|
||||||
|
|
||||||
; wrap position index (in bytes) \1 (data register .w)
|
|
||||||
;
|
|
||||||
; if position >RXSTOP_INIT-1
|
|
||||||
; position = (position-RXSTOP_INIT+RXSTART_INIT)
|
|
||||||
; endif
|
|
||||||
WRAPINDEX macro
|
|
||||||
cmp.w #RXSTOP_INIT&$fffe,\1 ;wrap Dn if beyond buffer
|
|
||||||
ble.s .nowrap\0\@
|
|
||||||
add.w #RXSTART_INIT-RXSTOP_INIT,\1
|
|
||||||
.nowrap\0\@
|
|
||||||
endm
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -0,0 +1,119 @@
|
|||||||
|
; ------------------------------------------------------------------------------
|
||||||
|
; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
|
||||||
|
; | Henryk Richter <henryk.richter@gmx.net> |
|
||||||
|
; ------------------------------------------------------------------------------
|
||||||
|
; macro section
|
||||||
|
|
||||||
|
;------------------ options, some depend on hardware (CPLD) configuration -------------------------
|
||||||
|
_OPT_BUFFER_SWAP EQU 0 ;perform byte swap on buffer ops (1) or assume native endian (0)
|
||||||
|
_OPT_REG_SWAP EQU 0 ;perform byte swap on register ops (1) or assume native endian (0)
|
||||||
|
_OPT_ADR_QUIRK EQU 0 ;address lines 12/13 are swapped (1) or linear addressing (0)
|
||||||
|
_OPT_FLOWCONTROL EQU 0 ;perform flow control on RX (1) or not (0)
|
||||||
|
_OPT_RECV EQU 1 ;faster recv (1) or generic (0)
|
||||||
|
|
||||||
|
;\1 register offset (without CLEAR offset)
|
||||||
|
;\2 address register of board I/O base
|
||||||
|
;\3 register with clear mask
|
||||||
|
ifne _OPT_REG_SWAP
|
||||||
|
|
||||||
|
CLRREG macro
|
||||||
|
rol.w #8,\3
|
||||||
|
move.w \3,\1+CLR_OFFSET(\2)
|
||||||
|
rol.w #8,\3
|
||||||
|
endm
|
||||||
|
;\1 register offset (without SET offset)
|
||||||
|
;\2 address register of board I/O base
|
||||||
|
;\3 register with set mask
|
||||||
|
SETREG macro
|
||||||
|
rol.w #8,\3
|
||||||
|
move.w \3,\1+SET_OFFSET(\2)
|
||||||
|
rol.w #8,\3
|
||||||
|
endm
|
||||||
|
;\1 register offset (e.g. ESTAT)
|
||||||
|
;\2 address register of board I/O base (e.g. a0)
|
||||||
|
;\3 destination register to be written (e.g. d0)
|
||||||
|
READREG macro
|
||||||
|
rol.w #8,\3
|
||||||
|
move.w \1(\2),\3
|
||||||
|
rol.w #8,\3
|
||||||
|
endm
|
||||||
|
;\1 register offset (e.g. ESTAT)
|
||||||
|
;\2 address register of board I/O base (e.g. a0)
|
||||||
|
;\3 soure register copied to HW register (e.g. d0)
|
||||||
|
WRITEREG macro
|
||||||
|
rol.w #8,\3
|
||||||
|
move.w \3,\1(\2)
|
||||||
|
rol.w #8,\3
|
||||||
|
endm
|
||||||
|
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
CLRREG macro
|
||||||
|
move.w \3,\1+CLR_OFFSET(\2)
|
||||||
|
endm
|
||||||
|
;\1 register offset (without SET offset)
|
||||||
|
;\2 address register of board I/O base
|
||||||
|
;\3 register with set mask
|
||||||
|
SETREG macro
|
||||||
|
move.w \3,\1+SET_OFFSET(\2)
|
||||||
|
endm
|
||||||
|
;\1 register offset (e.g. ESTAT)
|
||||||
|
;\2 address register of board I/O base (e.g. a0)
|
||||||
|
;\3 destination register to be written (e.g. d0)
|
||||||
|
READREG macro
|
||||||
|
move.w \1(\2),\3
|
||||||
|
endm
|
||||||
|
;\1 register offset (e.g. ESTAT)
|
||||||
|
;\2 address register of board I/O base (e.g. a0)
|
||||||
|
;\3 soure register copied to HW register (e.g. d0)
|
||||||
|
WRITEREG macro
|
||||||
|
move.w \3,\1(\2)
|
||||||
|
endm
|
||||||
|
|
||||||
|
endc
|
||||||
|
|
||||||
|
;read with address shuffling or direct from SRAM (affects $2000-$5000)
|
||||||
|
ifne _OPT_ADR_QUIRK
|
||||||
|
;\1 = address register
|
||||||
|
;\2 = data register, offset
|
||||||
|
;\3 = destination
|
||||||
|
READSRAM macro
|
||||||
|
eor.w #$6000,\2
|
||||||
|
move.w (\1,\2.w),\3
|
||||||
|
eor.w #$6000,\2
|
||||||
|
endm
|
||||||
|
else
|
||||||
|
READSRAM macro
|
||||||
|
move.w (\1,\2),\3
|
||||||
|
endm
|
||||||
|
endc
|
||||||
|
|
||||||
|
;read with address shuffling or direct from SRAM (affects $2000-$5000)
|
||||||
|
ifne _OPT_ADR_QUIRK
|
||||||
|
;\1 = address register
|
||||||
|
;\2 = data register, offset
|
||||||
|
;\3 = destination
|
||||||
|
READSRAM_LONG macro
|
||||||
|
eor.w #$6000,\2
|
||||||
|
move.l (\1,\2.w),\3
|
||||||
|
eor.w #$6000,\2
|
||||||
|
endm
|
||||||
|
else
|
||||||
|
READSRAM_LONG macro
|
||||||
|
move.l (\1,\2),\3
|
||||||
|
endm
|
||||||
|
endc
|
||||||
|
|
||||||
|
|
||||||
|
; wrap position index (in bytes) \1 (data register .w)
|
||||||
|
;
|
||||||
|
; if position >RXSTOP_INIT-1
|
||||||
|
; position = (position-RXSTOP_INIT+RXSTART_INIT)
|
||||||
|
; endif
|
||||||
|
WRAPINDEX macro
|
||||||
|
cmp.w #RXSTOP_INIT&$fffe,\1 ;wrap Dn if beyond buffer
|
||||||
|
ble.s .nowrap\0\@
|
||||||
|
add.w #RXSTART_INIT-RXSTOP_INIT-1,\1
|
||||||
|
.nowrap\0\@
|
||||||
|
endm
|
||||||
@@ -1,6 +1,14 @@
|
|||||||
////////////////////////////////////////////////////
|
; ------------------------------------------------------------------------------
|
||||||
// ENC424J600/624J600 register addresses //
|
; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
|
||||||
////////////////////////////////////////////////////
|
; | Henryk Richter <henryk.richter@gmx.net> |
|
||||||
|
; ------------------------------------------------------------------------------
|
||||||
|
; register definition section
|
||||||
|
|
||||||
|
; set/clr register offsets
|
||||||
|
SET_OFFSET EQU $0100
|
||||||
|
CLR_OFFSET EQU $0180
|
||||||
|
|
||||||
|
; Register definitions
|
||||||
|
|
||||||
; SPI Bank 0 registers --------
|
; SPI Bank 0 registers --------
|
||||||
ETXST EQU $7E00
|
ETXST EQU $7E00
|
||||||
@@ -181,7 +189,6 @@ EUDAWRPT EQU $7E90
|
|||||||
EUDAWRPTL EQU $7E90
|
EUDAWRPTL EQU $7E90
|
||||||
EUDAWRPTH EQU $7E91
|
EUDAWRPTH EQU $7E91
|
||||||
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
; ENC424J600/624J600 register bits
|
; ENC424J600/624J600 register bits
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
@@ -280,24 +287,24 @@ MACON1_r9 EQU (1<<9)
|
|||||||
MACON1_r8 EQU (1<<8)
|
MACON1_r8 EQU (1<<8)
|
||||||
MACON1_LOOPBK EQU (1<<4)
|
MACON1_LOOPBK EQU (1<<4)
|
||||||
MACON1_r3 EQU (1<<3)
|
MACON1_r3 EQU (1<<3)
|
||||||
#define MACON1_RXPAUS EQU (1<<2)
|
MACON1_RXPAUS EQU (1<<2)
|
||||||
#define MACON1_PASSALL EQU (1<<1)
|
MACON1_PASSALL EQU (1<<1)
|
||||||
MACON1_r0 EQU (1)
|
MACON1_r0 EQU (1)
|
||||||
|
|
||||||
; MACON2 bits ---------
|
; MACON2 bits ---------
|
||||||
#define MACON2_DEFER EQU (1<<14)
|
MACON2_DEFER EQU (1<<14)
|
||||||
#define MACON2_BPEN EQU (1<<13)
|
MACON2_BPEN EQU (1<<13)
|
||||||
#define MACON2_NOBKOFF EQU (1<<12)
|
MACON2_NOBKOFF EQU (1<<12)
|
||||||
MACON2_r9 EQU (1<<9)
|
MACON2_r9 EQU (1<<9)
|
||||||
MACON2_r8 EQU (1<<8)
|
MACON2_r8 EQU (1<<8)
|
||||||
#define MACON2_PADCFG2 EQU (1<<7)
|
MACON2_PADCFG2 EQU (1<<7)
|
||||||
#define MACON2_PADCFG1 EQU (1<<6)
|
MACON2_PADCFG1 EQU (1<<6)
|
||||||
#define MACON2_PADCFG0 EQU (1<<5)
|
MACON2_PADCFG0 EQU (1<<5)
|
||||||
#define MACON2_TXCRCEN EQU (1<<4)
|
MACON2_TXCRCEN EQU (1<<4)
|
||||||
#define MACON2_PHDREN EQU (1<<3)
|
MACON2_PHDREN EQU (1<<3)
|
||||||
#define MACON2_HFRMEN EQU (1<<2)
|
MACON2_HFRMEN EQU (1<<2)
|
||||||
MACON2_r1 EQU (1<<1)
|
MACON2_r1 EQU (1<<1)
|
||||||
#define MACON2_FULDPX EQU (1)
|
MACON2_FULDPX EQU (1)
|
||||||
|
|
||||||
; MABBIPG bits --------
|
; MABBIPG bits --------
|
||||||
MABBIPG_BBIPG6 EQU (1<<6)
|
MABBIPG_BBIPG6 EQU (1<<6)
|
||||||
@@ -337,8 +344,8 @@ MACLCON_MAXRET1 EQU (1<<1)
|
|||||||
MACLCON_MAXRET0 EQU (1)
|
MACLCON_MAXRET0 EQU (1)
|
||||||
|
|
||||||
; MICMD bits ----------
|
; MICMD bits ----------
|
||||||
#define MICMD_MIISCAN EQU (1<<1)
|
MICMD_MIISCAN EQU (1<<1)
|
||||||
#define MICMD_MIIRD EQU (1)
|
MICMD_MIIRD EQU (1)
|
||||||
|
|
||||||
; MIREGADR bits -------
|
; MIREGADR bits -------
|
||||||
MIREGADR_r12 EQU (1<<12)
|
MIREGADR_r12 EQU (1<<12)
|
||||||
@@ -354,9 +361,9 @@ MIREGADR_PHREG0 EQU (1)
|
|||||||
|
|
||||||
; MISTAT bits ---------
|
; MISTAT bits ---------
|
||||||
MISTAT_r3 EQU (1<<3)
|
MISTAT_r3 EQU (1<<3)
|
||||||
#define MISTAT_NVALID EQU (1<<2)
|
MISTAT_NVALID EQU (1<<2)
|
||||||
#define MISTAT_SCAN EQU (1<<1)
|
MISTAT_SCAN EQU (1<<1)
|
||||||
#define MISTAT_BUSY EQU (1)
|
MISTAT_BUSY EQU (1)
|
||||||
|
|
||||||
; ECON2 bits ----------
|
; ECON2 bits ----------
|
||||||
ECON2_ETHEN EQU (1<<15)
|
ECON2_ETHEN EQU (1<<15)
|
||||||
@@ -573,3 +580,23 @@ PHSTAT3_SPDDPX1 EQU (1<<3)
|
|||||||
PHSTAT3_SPDDPX0 EQU (1<<2)
|
PHSTAT3_SPDDPX0 EQU (1<<2)
|
||||||
PHSTAT3_r1 EQU (1<<1)
|
PHSTAT3_r1 EQU (1<<1)
|
||||||
PHSTAT3_r0 EQU (1)
|
PHSTAT3_r0 EQU (1)
|
||||||
|
|
||||||
|
;------------------------------ internal defaults ----------------------------------
|
||||||
|
;33.333Mhz clock out frequency
|
||||||
|
CLOCK_33_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) ;clr mask
|
||||||
|
CLOCK_33_SET EQU (ECON2_COCON0) ;set mask
|
||||||
|
;25 MHz
|
||||||
|
CLOCK_25_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) ;clr mask
|
||||||
|
CLOCK_25_SET EQU (ECON2_COCON1) ;set mask
|
||||||
|
;20 MHz
|
||||||
|
CLOCK_20_CLR EQU (ECON2_COCON3|ECON2_COCON2) ;clr mask
|
||||||
|
CLOCK_20_SET EQU (ECON2_COCON1|ECON2_COCON0) ;set mask
|
||||||
|
;16 MHz
|
||||||
|
CLOCK_16_CLR EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;clr mask
|
||||||
|
CLOCK_16_SET EQU (ECON2_COCON2) ;set mask
|
||||||
|
;4 MHz (after reset)
|
||||||
|
CLOCK_4_CLR EQU (ECON2_COCON2) ;clr mask
|
||||||
|
CLOCK_4_SET EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;set mask
|
||||||
|
|
||||||
|
CLOCK_DEF_CLR EQU CLOCK_33_CLR
|
||||||
|
CLOCK_DEF_SET EQU CLOCK_33_SET
|
||||||
|
|||||||
+30
-34
@@ -345,30 +345,22 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
return ok;
|
return ok;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
** reading packets
|
** reading packets
|
||||||
*/
|
*/
|
||||||
/*F*/ PRIVATE REGARGS VOID doreadreqs(BASEPTR)
|
/*F*/ PRIVATE REGARGS VOID doreadreqs(BASEPTR)
|
||||||
{
|
{
|
||||||
LONG datasize,haverec;
|
LONG datasize;
|
||||||
struct IOSana2Req *got;
|
struct IOSana2Req *got;
|
||||||
ULONG pkttyp = 0; /* just to avoid warning with opt build, irrelevant otherwise */
|
ULONG pkttyp = 0; /* just to avoid warning with opt build, irrelevant otherwise */
|
||||||
BOOL rv;
|
BOOL rv;
|
||||||
struct HWFrame *frame = pb->pb_Frame;
|
struct HWFrame *frame = pb->pb_Frame;
|
||||||
|
|
||||||
haverec = hw_recv_pending(pb);
|
|
||||||
/*allow only a certain number of packets to be serverd per interrupt*/
|
|
||||||
|
|
||||||
if(haverec>MAX_READ_PACKAGE){
|
|
||||||
haverec = MAX_READ_PACKAGE;
|
|
||||||
}
|
|
||||||
while(haverec--){
|
|
||||||
d8(("+hw_recv\n"));
|
d8(("+hw_recv\n"));
|
||||||
rv = hw_recv_frame(pb, frame);
|
rv = hw_recv_frame(pb, frame);
|
||||||
d8(("-hw_recv\n"));
|
d8(("-hw_recv\n"));
|
||||||
if (rv)
|
if (rv)
|
||||||
{
|
{
|
||||||
BOOL ok;
|
|
||||||
pb->pb_DevStats.PacketsReceived++;
|
pb->pb_DevStats.PacketsReceived++;
|
||||||
|
|
||||||
pkttyp = frame->hwf_Type;
|
pkttyp = frame->hwf_Type;
|
||||||
@@ -388,13 +380,13 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
datasize = frame->hwf_Size - HW_ETH_HDR_SIZE;
|
datasize = frame->hwf_Size - HW_ETH_HDR_SIZE;
|
||||||
|
|
||||||
dotracktype(pb, pkttyp, 0, 1, 0, datasize, 0);
|
dotracktype(pb, pkttyp, 0, 1, 0, datasize, 0);
|
||||||
|
|
||||||
d(("packet %08lx, size %ld received\n",pkttyp,datasize));
|
d(("packet %08lx, size %ld received\n",pkttyp,datasize));
|
||||||
|
|
||||||
ok = FALSE;
|
|
||||||
ObtainSemaphore(&pb->pb_ReadListSem);
|
ObtainSemaphore(&pb->pb_ReadListSem);
|
||||||
|
|
||||||
/* traverse the list of read-requests */
|
/* traverse the list of read-requests */
|
||||||
@@ -405,15 +397,10 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
/* check if this one requests for the new packet we got */
|
/* check if this one requests for the new packet we got */
|
||||||
if (got->ios2_PacketType == pkttyp )
|
if (got->ios2_PacketType == pkttyp )
|
||||||
{
|
{
|
||||||
|
BOOL ok;
|
||||||
|
|
||||||
Remove((struct Node*)got);
|
Remove((struct Node*)got);
|
||||||
ok=TRUE; /* mark, that we found the package and quit list traversing */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ReleaseSemaphore(&pb->pb_ReadListSem);
|
|
||||||
|
|
||||||
if(ok){
|
|
||||||
/* deliver packet */
|
/* deliver packet */
|
||||||
ok = read_frame(got, frame);
|
ok = read_frame(got, frame);
|
||||||
if(!ok) {
|
if(!ok) {
|
||||||
@@ -422,13 +409,28 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
|
|
||||||
d(("packet received, satisfying S2Request\n"));
|
d(("packet received, satisfying S2Request\n"));
|
||||||
DevTermIO(pb, got);
|
DevTermIO(pb, got);
|
||||||
got = NULL; /* delete the request to indicate that we served it*/
|
got = NULL;
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
else {
|
}
|
||||||
|
|
||||||
|
ReleaseSemaphore(&pb->pb_ReadListSem);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
d(("Error receiving (%ld. len=%ld)\n", rv, frame->hwf_Size));
|
||||||
|
/* something went wrong during receipt */
|
||||||
|
DoEvent(pb, S2EVENT_HARDWARE | S2EVENT_ERROR | S2EVENT_RX);
|
||||||
|
got = NULL;
|
||||||
|
pb->pb_DevStats.BadData++;
|
||||||
|
}
|
||||||
|
|
||||||
/* If no one wanted this packet explicitely, there is one chance
|
/* If no one wanted this packet explicitely, there is one chance
|
||||||
** left: somebody waiting for orphaned packets. If this fails, too,
|
** left: somebody waiting for orphaned packets. If this fails, too,
|
||||||
** we will drop it.
|
** we will drop it.
|
||||||
*/
|
*/
|
||||||
|
if (got)
|
||||||
|
{
|
||||||
d(("unknown packet\n"));
|
d(("unknown packet\n"));
|
||||||
|
|
||||||
pb->pb_DevStats.UnknownTypesReceived++;
|
pb->pb_DevStats.UnknownTypesReceived++;
|
||||||
@@ -439,7 +441,7 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
|
|
||||||
if (got)
|
if (got)
|
||||||
{
|
{
|
||||||
ok = read_frame(got, frame);
|
BOOL ok = read_frame(got, frame);
|
||||||
if(!ok) {
|
if(!ok) {
|
||||||
DoEvent(pb, S2EVENT_ERROR | S2EVENT_BUFF | S2EVENT_SOFTWARE);
|
DoEvent(pb, S2EVENT_ERROR | S2EVENT_BUFF | S2EVENT_SOFTWARE);
|
||||||
}
|
}
|
||||||
@@ -454,16 +456,6 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
d(("packet thrown away...\n"));
|
d(("packet thrown away...\n"));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
d(("Error receiving (%ld. len=%ld)\n", rv, frame->hwf_Size));
|
|
||||||
/* something went wrong during receipt */
|
|
||||||
DoEvent(pb, S2EVENT_HARDWARE | S2EVENT_ERROR | S2EVENT_RX);
|
|
||||||
got = NULL;
|
|
||||||
pb->pb_DevStats.BadData++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
/*E*/
|
/*E*/
|
||||||
|
|
||||||
@@ -737,8 +729,12 @@ PRIVATE REGARGS BOOL read_frame(struct IOSana2Req *req, struct HWFrame *frame)
|
|||||||
}
|
}
|
||||||
hw_disable_global_int(pb);
|
hw_disable_global_int(pb);
|
||||||
|
|
||||||
|
/*allow only a certain number of packets to be serverd per interrupt*/
|
||||||
|
if(haverec>MAX_READ_PACKAGE)
|
||||||
|
haverec = MAX_READ_PACKAGE;
|
||||||
|
|
||||||
/* accept pending receive and start reading */
|
/* accept pending receive and start reading */
|
||||||
if( haverec>0 )
|
while( haverec-- )
|
||||||
{
|
{
|
||||||
d2(("*+ do_read\n"));
|
d2(("*+ do_read\n"));
|
||||||
doreadreqs(pb);
|
doreadreqs(pb);
|
||||||
|
|||||||
Reference in New Issue
Block a user