Z3-config-try
This commit is contained in:
MHeinrichs
@@ -0,0 +1,737 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:08:29 12/13/2016
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-- Design Name:
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-- Module Name: LAN_IDE_CP - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- directory cleanup hint:
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-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LAN_IDE_CP is
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Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
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D : inout STD_LOGIC_VECTOR (15 downto 0);
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DQ : inout STD_LOGIC_VECTOR (15 downto 0);
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A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
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OWN : out STD_LOGIC;
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SLAVE : out STD_LOGIC;
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CFOUT : out STD_LOGIC;
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CFIN : in STD_LOGIC;
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C1 : in STD_LOGIC;
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C3 : in STD_LOGIC;
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MTCR : in STD_LOGIC;
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OVR : out STD_LOGIC;
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BERR : in STD_LOGIC;
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MTACK : out STD_LOGIC;
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DS0 : in STD_LOGIC;
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DTACK : out STD_LOGIC;
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UDS : in STD_LOGIC;
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LDS : in STD_LOGIC;
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AS : in STD_LOGIC;
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RW : in STD_LOGIC;
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Z3 : in STD_LOGIC;
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DS1 : in STD_LOGIC;
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FCS : in STD_LOGIC;
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RESET : in STD_LOGIC;
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INT_OUT : out STD_LOGIC;
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INT_CP_OUT : out STD_LOGIC;
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AUTOBOOT_OFF : in STD_LOGIC;
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ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
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ROM_OE : out STD_LOGIC;
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IDE_WAIT : in STD_LOGIC;
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CLK_EXT : in STD_LOGIC;
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IDE_W : out STD_LOGIC;
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IDE_R : out STD_LOGIC;
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IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
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IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
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LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
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LAN_RD : out STD_LOGIC;
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LAN_CS : out STD_LOGIC;
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LAN_WRH : out STD_LOGIC;
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LAN_WRL : out STD_LOGIC;
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LAN_INT : in STD_LOGIC;
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CP_RD : out STD_LOGIC;
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CP_WE : out STD_LOGIC;
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CP_CS : out STD_LOGIC;
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CP_IRQ : in STD_LOGIC);
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end LAN_IDE_CP;
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architecture Behavioral of LAN_IDE_CP is
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TYPE lan_reset IS (
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nop,
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wait0,
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clr,
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clr_commit,
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wait1,
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set,
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set_commit,
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done
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);
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TYPE lan_bus_sm IS (
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nop,
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start_read_upper,
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wait_read_upper,
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end_read_upper,
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start_read_lower,
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wait_read_lower,
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end_read_lower,
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start_write_upper,
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wait_write_upper,
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end_write_upper,
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start_write_lower,
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wait_write_lower,
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end_write_lower
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);
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signal LAN_RST_SM: lan_reset :=nop;
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signal LAN_SM: lan_bus_sm :=nop;
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signal AUTOCONFIG_Z3_ACCESS: STD_LOGIC;
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signal AUTOCONFIG_Z2_ACCESS: STD_LOGIC;
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signal IDE_ACCESS: STD_LOGIC;
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signal IDE_ENABLE: STD_LOGIC;
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signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
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signal IDE_R_S: STD_LOGIC;
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signal IDE_W_S: STD_LOGIC;
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signal ROM_OE_S: STD_LOGIC;
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signal CP_ACCESS: STD_LOGIC;
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signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
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signal LAN_ACCESS: STD_LOGIC;
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signal DQ_SWAP: STD_LOGIC;
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signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
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signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(2 downto 0):="000";
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signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0):="000";
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signal SHUT_UP_Z2:STD_LOGIC_VECTOR(2 downto 0):="111";
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signal LAN_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
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signal LAN_INT_ENABLE: std_logic;
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signal LAN_RD_S: std_logic;
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signal LAN_WRH_S: std_logic;
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signal LAN_WRL_S: std_logic;
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signal LAN_READY: std_logic;
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signal CONFIG_READY: std_logic;
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signal LAN_IRQ_D0: std_logic;
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signal LAN_IRQ_OUT: std_logic;
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signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
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signal Z3_DATA_IN:STD_LOGIC_VECTOR(31 downto 0);
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signal Z3_DATA:STD_LOGIC_VECTOR(31 downto 0);
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signal DQ_DATA:STD_LOGIC_VECTOR(15 downto 0);
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signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
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signal Z3_A_LOW:STD_LOGIC;
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signal LAN_SM_RST:STD_LOGIC;
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signal CP_RD_S: std_logic;
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signal CP_WE_S: std_logic;
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signal CP_WE_QUIRK: std_logic;
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signal AMIGA_CLK:STD_LOGIC;
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signal DS:STD_LOGIC;
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signal LAN_CS_RST: std_logic;
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signal LAN_WR_RST: std_logic;
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signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
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signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
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constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
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constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
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constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000001000010010"; --25MHz SET-MASK
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constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000110100000000"; --25MHz CLEAR-MASK
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Function to_std_logic(X: in Boolean) return Std_Logic is
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variable ret : std_logic;
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begin
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if x then ret := '1'; else ret := '0'; end if;
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return ret;
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end to_std_logic;
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begin
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Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
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Z3_DS <= UDS & LDS & DS1 & DS0;
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AMIGA_CLK <= not (C1 xor C3);
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DS <= UDS and LDS;
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clock_init: process(reset,CLK_EXT)
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begin
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if(reset='1')then
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--default values
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=nop;
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LAN_A_INIT<="11"&x"FFF";
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LAN_D_INIT<= x"0000";
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elsif(rising_edge(CLK_EXT))then --reset is low!
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case LAN_RST_SM is
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when nop=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait0;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when wait0=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=clr;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when clr=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=clr_commit;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when clr_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait1;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when wait1=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=set;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when set=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=set_commit;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when set_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when done=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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end case;
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end if;
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end process clock_init;
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ADDRESS_Z3_DECODE: process(AS,reset,FCS)
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begin
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if(--AS ='0' or
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reset='0')then
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AUTOCONFIG_Z3_ACCESS <= '0';
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LAN_ACCESS <= '0';
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DQ_SWAP <= '1';
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Z3_ADR <= (others => '1');
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elsif(falling_edge(FCS))then
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Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
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--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
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--lan base
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if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
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if(A(14 downto 13)<"11")then
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DQ_SWAP <= '1';
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else
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DQ_SWAP <= '0';
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end if;
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LAN_ACCESS <= '1';
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else
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LAN_ACCESS <= '0';
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DQ_SWAP <= '1';
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end if;
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end if;
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end process ADDRESS_Z3_DECODE;
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ADDRESS_Z2_DECODE: process(FCS,reset,AS)
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begin
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if(--FCS ='0' or
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reset='0')then
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AUTOCONFIG_Z2_ACCESS <= '0';
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IDE_ACCESS <= '0';
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CP_ACCESS <= '0';
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elsif(falling_edge(AS))then
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if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
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AUTOCONFIG_Z2_ACCESS <= '1';
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else
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AUTOCONFIG_Z2_ACCESS <= '0';
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end if;
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--CP base
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if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(0)='0' )then
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CP_ACCESS <= '1';
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else
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CP_ACCESS <= '0';
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end if;
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--IDE base
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if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(1)='0' )then
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IDE_ACCESS <= '1';
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else
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IDE_ACCESS <= '0';
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end if;
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end if;
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end process ADDRESS_Z2_DECODE;
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--LAN interrupt enable
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lan_int_proc: process (CLK_EXT,reset)
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begin
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if(reset ='0') then
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LAN_INT_ENABLE <='0';
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LAN_IRQ_D0 <='1';
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LAN_IRQ_OUT <='1';
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CONFIG_READY <='0';
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elsif rising_edge(CLK_EXT) then
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LAN_IRQ_D0 <= LAN_INT;
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--set/deassert the LAN-interrupt bit
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if( LAN_INT ='1' --or --no interupt
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--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
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-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
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)then
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LAN_IRQ_OUT <='1';
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elsif(
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(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
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--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
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-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
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) then
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LAN_IRQ_OUT <='0';
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end if;
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--bus acknowledge if a access to A15=1 occurred
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if(LAN_ACCESS = '1' and FCS ='0' and Z3_ADR(15)='1') then
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CONFIG_READY <='1';
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else
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CONFIG_READY <='0';
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end if;
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--set int enable and config ready flags
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if(LAN_ACCESS = '1' and FCS ='0' and RW='0' and Z3_ADR(15)='1') then --enable if a write to A15 occured
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if(Z3_DS(3) ='0')then
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LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
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elsif(Z3_DS(2) ='0')then
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LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
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end if;
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end if;
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end if;
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end process lan_int_proc;
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--clock this signal to avoid glitches due to short resets
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lan_rst_gen: process (CLK_EXT)
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begin
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if falling_edge(CLK_EXT) then
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if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0' or Z3_ADR(15)='1') then
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LAN_SM_RST <='1';
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else
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LAN_SM_RST <='0';
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end if;
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end if;
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end process lan_rst_gen;
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--lan signal generation: all Signals are HIGH active!
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lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
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begin
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if(LAN_SM_RST ='1' ) then
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LAN_SM <=nop;
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LAN_RD_S <= '0';
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LAN_WRH_S <= '0';
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LAN_WRL_S <= '0';
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Z3_A_LOW <= '0';
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LAN_READY <= '0';
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Z3_DATA(31 downto 0) <= x"FFFFFFFF";
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DQ_DATA(15 downto 0) <= x"FFFF";
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elsif rising_edge(CLK_EXT) then
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--default values
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LAN_RD_S <= '0';
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LAN_WRH_S <= '0';
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LAN_WRL_S <= '0';
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Z3_A_LOW <= '0';
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LAN_READY <= '0';
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case LAN_SM is
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when nop=>
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--cycle start!
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-- prepare the data for write
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-- this is a quite complex thing for a cpld
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-- so I have to move this out of the cycle start condition and prepare it for every loop
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if(Z3_DS(3 downto 2) < "11")then
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if(DQ_SWAP='0') then
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
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else
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
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end if;
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else -- lower word!
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Z3_A_LOW <= '1';
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if(DQ_SWAP='0') then
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
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else
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DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
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end if;
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end if;
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if(RW='1')then --read from MSB
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if(Z3_DS(3 downto 2) < "11")then --determine bushalf
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_upper;
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else
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_lower;
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end if;
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else
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if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
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LAN_SM <= start_write_upper;
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else
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LAN_SM <= start_write_lower;
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end if;
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end if;
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when start_read_upper=>
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_upper;
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when wait_read_upper=>
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LAN_RD_S <= '1';
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LAN_SM<=end_read_upper;
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when end_read_upper=>
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--fetch data
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if(DQ_SWAP='0') then
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Z3_DATA(31 downto 16) <= DQ;
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else
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Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
end if;
|
||||
if(Z3_DS(1 downto 0) = "11")then -- no lower half
|
||||
LAN_READY <='1';
|
||||
LAN_SM <= end_read_upper; -- stay here until cylce end
|
||||
else
|
||||
Z3_A_LOW <= '1';
|
||||
LAN_SM <= start_read_lower;
|
||||
end if;
|
||||
when start_read_lower=>
|
||||
Z3_A_LOW <= '1';
|
||||
LAN_RD_S <= '1';
|
||||
LAN_SM <= wait_read_lower;
|
||||
when wait_read_lower=>
|
||||
Z3_A_LOW <= '1';
|
||||
LAN_RD_S <= '1';
|
||||
LAN_READY <= '1';
|
||||
LAN_SM<=end_read_lower;
|
||||
when end_read_lower=>
|
||||
--fetch data
|
||||
if(DQ_SWAP='0') then
|
||||
Z3_DATA(15 downto 0) <= DQ;
|
||||
else
|
||||
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
|
||||
end if;
|
||||
LAN_READY <='1';
|
||||
LAN_SM<=end_read_lower; -- stay here until cylce end
|
||||
when start_write_upper=>
|
||||
-- swapped DS3/DS2 here: ENC624 is little endian
|
||||
LAN_WRH_S <= not Z3_DS(2);
|
||||
LAN_WRL_S <= not Z3_DS(3);
|
||||
LAN_SM <= wait_write_upper;
|
||||
when wait_write_upper=>
|
||||
LAN_SM<=end_write_upper;
|
||||
when end_write_upper=>
|
||||
-- prepare the data for write
|
||||
if(DQ_SWAP='0') then
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
||||
else
|
||||
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
|
||||
end if;
|
||||
|
||||
if(Z3_DS(1 downto 0) = "11")then -- no lower half
|
||||
LAN_READY <='1';
|
||||
LAN_SM <= end_write_upper; -- stay here until cylce end
|
||||
else
|
||||
Z3_A_LOW <= '1';
|
||||
LAN_SM <= start_write_lower;
|
||||
end if;
|
||||
when start_write_lower=>
|
||||
Z3_A_LOW <= '1';
|
||||
-- swapped DS0/DS1 here: ENC624 is little endian
|
||||
LAN_WRH_S <= not Z3_DS(0);
|
||||
LAN_WRL_S <= not Z3_DS(1);
|
||||
LAN_SM <= wait_write_lower;
|
||||
when wait_write_lower=>
|
||||
Z3_A_LOW <= '1';
|
||||
LAN_READY <='1';
|
||||
LAN_SM<=end_write_lower;
|
||||
when end_write_lower=>
|
||||
LAN_READY <='1';
|
||||
LAN_SM<=end_write_lower; -- stay here until cylce end
|
||||
end case;
|
||||
end if;
|
||||
end process lan_rw_gen;
|
||||
|
||||
--autoconfig
|
||||
autoconfig_proc: process (reset, AMIGA_CLK)
|
||||
begin
|
||||
if reset = '0' then
|
||||
-- reset active ...
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE <="000";
|
||||
D_Z2_OUT<="1111";
|
||||
SHUT_UP_Z2 <="111";
|
||||
IDE_BASEADR<=x"FF";
|
||||
CP_BASEADR<=x"FF";
|
||||
AUTO_CONFIG_Z2_DONE <="000";
|
||||
LAN_BASEADR<=x"FFFF";
|
||||
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
|
||||
D_Z2_OUT<="1111";
|
||||
if(AS='1')then
|
||||
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE;
|
||||
elsif(AUTOCONFIG_Z2_ACCESS= '1' and DS='0') then
|
||||
case A(6 downto 1) is
|
||||
when "000000" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
|
||||
else
|
||||
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
|
||||
end if;
|
||||
when "000001" => D_Z2_OUT <= "0001" ; --one Card, 64KB =001
|
||||
when "000010" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1000" ; --ProductID high nibble : 7->1000
|
||||
else
|
||||
D_Z2_OUT <= "1111" ; --ProductID high nibble : 0->1111
|
||||
end if;
|
||||
when "000011" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
D_Z2_OUT <= "0100" ; --ProductID low nibble: B->0100
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0011" ; --ProductID low nibble: C->0011
|
||||
else
|
||||
D_Z2_OUT <= "1001" ; --ProductID low nibble: 6->1001
|
||||
end if;
|
||||
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
|
||||
when "001001" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0101" ; --Ventor ID 1
|
||||
else
|
||||
D_Z2_OUT <= "0111" ; --Ventor ID 1
|
||||
end if;
|
||||
when "001010" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1110" ; --Ventor ID 2
|
||||
else
|
||||
D_Z2_OUT <= "1101" ; --Ventor ID 2
|
||||
end if;
|
||||
when "001011" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
|
||||
else
|
||||
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $082C: BSC
|
||||
end if;
|
||||
when "001100" => D_Z2_OUT <= "0100" ; --Serial byte 0 (msb) high nibble
|
||||
when "001101" => D_Z2_OUT <= "1110" ; --Serial byte 0 (msb) low nibble
|
||||
when "001110" => D_Z2_OUT <= "1001" ; --Serial byte 1 high nibble
|
||||
when "001111" => D_Z2_OUT <= "0100" ; --Serial byte 1 low nibble
|
||||
when "010000" => D_Z2_OUT <= "1111" ; --Serial byte 2 high nibble
|
||||
when "010001" => D_Z2_OUT <= "1111" ; --Serial byte 2 low nibble
|
||||
when "010010" => D_Z2_OUT <= "0100" ; --Serial byte 3 (lsb) high nibble
|
||||
when "010011" => D_Z2_OUT <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
|
||||
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
|
||||
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
|
||||
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
|
||||
when "010111" =>
|
||||
if(AUTO_CONFIG_Z2_DONE = 1)then
|
||||
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
|
||||
else
|
||||
D_Z2_OUT <= "1111" ; --Rom vector low byte low nibble
|
||||
end if;
|
||||
when "100010" =>
|
||||
if(RW='0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
|
||||
end if;
|
||||
end if;
|
||||
when "100100" =>
|
||||
if(RW='0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(0) <='0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(1) <='0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(2) <= '0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||
end if;
|
||||
end if;
|
||||
when "100110" =>
|
||||
D_Z2_OUT <= "1111" ;
|
||||
if(RW='0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||
end if;
|
||||
end if;
|
||||
when others => D_Z2_OUT <= "1111" ;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process autoconfig_proc; --- that's all
|
||||
|
||||
|
||||
|
||||
LAN_CS <= LAN_ACCESS when reset='1' else LAN_CS_RST;
|
||||
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_WRH <= LAN_WRH_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_RD <= LAN_RD_S when FCS='0' and reset = '1' else '0';
|
||||
LAN_CFG <= "ZZZZ";
|
||||
|
||||
|
||||
A_LAN(13 downto 6)<= LAN_A_INIT(13 downto 6) when reset ='0' else
|
||||
Z3_ADR(14 downto 7);
|
||||
A_LAN(5 downto 2) <= LAN_A_INIT(5 downto 2) when reset ='0' else
|
||||
A(5 downto 2) when CP_ACCESS='1' else --mux the clock-port adresses!
|
||||
Z3_ADR(6 downto 3);
|
||||
A_LAN(1 downto 0)<= LAN_A_INIT(1 downto 0) when reset ='0' else
|
||||
Z3_ADR(2) & Z3_A_LOW;
|
||||
|
||||
|
||||
|
||||
--signal assignment
|
||||
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
|
||||
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
|
||||
(others => 'Z');
|
||||
|
||||
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||
(others => 'Z');
|
||||
|
||||
A(7 downto 1) <= (others => 'Z');
|
||||
|
||||
--defined lancp signal that matches both LAN and CP addresses
|
||||
DQ <= LAN_D_INIT when reset='0' else
|
||||
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
|
||||
D when RW='0' and AS='0' and CP_ACCESS ='1' else
|
||||
(others => 'Z');
|
||||
|
||||
--
|
||||
-- --defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
|
||||
-- DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
-- LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
-- D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
|
||||
-- D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
|
||||
-- D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
|
||||
-- D when RW='0' and AS='0' and lancp ='1'
|
||||
-- else (others => 'Z');
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
INT_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
|
||||
'Z';
|
||||
INT_CP_OUT <= '0' when CP_IRQ = '0' else
|
||||
'Z';
|
||||
OWN <= 'Z';
|
||||
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
|
||||
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
|
||||
|
||||
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
|
||||
|
||||
DTACK <= '0' when FCS='0' and (LAN_READY = '1' or CONFIG_READY='1') else 'Z';
|
||||
|
||||
MTACK <= 'Z';
|
||||
|
||||
|
||||
--ide signal generation
|
||||
ide_rw_gen: process (reset,AMIGA_CLK)
|
||||
begin
|
||||
if (reset = '0') then
|
||||
IDE_ENABLE <= '1';
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
elsif falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
if(IDE_ACCESS='1' and AS='0')then
|
||||
if(RW='0')then
|
||||
--the write goes to the hdd!
|
||||
IDE_ENABLE <= '0'; -- enable IDE on first read
|
||||
IDE_W_S <= '0';
|
||||
else
|
||||
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
|
||||
ROM_OE_S <= not IDE_ENABLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process ide_rw_gen;
|
||||
|
||||
IDE_W <= IDE_W_S when AS='0' else '1';
|
||||
IDE_R <= IDE_R_S when AS='0' else '1';
|
||||
ROM_OE<= ROM_OE_S when AS='0' and AUTOBOOT_OFF ='0' else '1';
|
||||
IDE_CS(0)<= not(A(12));
|
||||
IDE_CS(1)<= not(A(13));
|
||||
IDE_A(2 downto 0) <= A(11 downto 9);
|
||||
ROM_B <= "00";
|
||||
|
||||
|
||||
--cp signal generation
|
||||
cp_rw_gen: process (AMIGA_CLK)
|
||||
begin
|
||||
if falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
CP_RD_S <= '1';
|
||||
CP_WE_S <= '1';
|
||||
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
|
||||
CP_RD_S <= not RW;
|
||||
CP_WE_S <= RW;
|
||||
end if;
|
||||
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
|
||||
end if;
|
||||
end process cp_rw_gen;
|
||||
|
||||
--for the future
|
||||
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||
CP_CS <= not CP_ACCESS;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,501 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 22:08:29 12/13/2016
|
||||
-- Design Name:
|
||||
-- Module Name: LAN_IDE_CP - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- directory cleanup hint:
|
||||
-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity LAN_IDE_CP is
|
||||
Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
|
||||
D : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||
DQ : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||
A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
|
||||
OWN : out STD_LOGIC;
|
||||
SLAVE : out STD_LOGIC;
|
||||
CFOUT : out STD_LOGIC;
|
||||
CFIN : in STD_LOGIC;
|
||||
C1 : in STD_LOGIC;
|
||||
C3 : in STD_LOGIC;
|
||||
MTCR : in STD_LOGIC;
|
||||
OVR : out STD_LOGIC;
|
||||
BERR : in STD_LOGIC;
|
||||
MTACK : out STD_LOGIC;
|
||||
DS0 : in STD_LOGIC;
|
||||
DTACK : out STD_LOGIC;
|
||||
UDS : in STD_LOGIC;
|
||||
LDS : in STD_LOGIC;
|
||||
AS : in STD_LOGIC;
|
||||
RW : in STD_LOGIC;
|
||||
Z3 : in STD_LOGIC;
|
||||
DS1 : in STD_LOGIC;
|
||||
FCS : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
INT2_OUT : out STD_LOGIC;
|
||||
INT6_OUT : out STD_LOGIC;
|
||||
AUTOBOOT_OFF : in STD_LOGIC;
|
||||
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
|
||||
ROM_OE : out STD_LOGIC;
|
||||
IDE_WAIT : in STD_LOGIC;
|
||||
CLK_EXT : in STD_LOGIC;
|
||||
IDE_W : out STD_LOGIC;
|
||||
IDE_R : out STD_LOGIC;
|
||||
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
|
||||
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
|
||||
LAN_RD : out STD_LOGIC;
|
||||
LAN_CS : out STD_LOGIC;
|
||||
LAN_WRH : out STD_LOGIC;
|
||||
LAN_WRL : out STD_LOGIC;
|
||||
LAN_INT : in STD_LOGIC;
|
||||
CP_RD : out STD_LOGIC;
|
||||
CP_WE : out STD_LOGIC;
|
||||
CP_CS : out STD_LOGIC;
|
||||
CP_IRQ : in STD_LOGIC);
|
||||
end LAN_IDE_CP;
|
||||
|
||||
architecture Behavioral of LAN_IDE_CP is
|
||||
|
||||
TYPE lan_reset IS (
|
||||
nop,
|
||||
wait0,
|
||||
clr,
|
||||
clr_commit,
|
||||
wait1,
|
||||
set,
|
||||
set_commit,
|
||||
done
|
||||
);
|
||||
|
||||
SIGNAL LAN_RST_SM: lan_reset :=nop;
|
||||
SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
|
||||
SIGNAL ide: STD_LOGIC;
|
||||
SIGNAL autoconfig: STD_LOGIC;
|
||||
SIGNAL lan_adr: STD_LOGIC;
|
||||
SIGNAL lan_adr_sw: STD_LOGIC;
|
||||
SIGNAL cp: STD_LOGIC;
|
||||
signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
|
||||
signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(1 downto 0);
|
||||
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
|
||||
signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
|
||||
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal IDE_ENABLE:STD_LOGIC;
|
||||
signal ROM_OE_S:STD_LOGIC;
|
||||
signal IDE_R_S:STD_LOGIC;
|
||||
signal IDE_W_S:STD_LOGIC;
|
||||
signal DTACK_S:STD_LOGIC;
|
||||
signal AMIGA_CLK: std_logic;
|
||||
signal LAN_INT_ENABLE: std_logic;
|
||||
signal DECODE_RESET: std_logic;
|
||||
signal LAN_INT_D0: std_logic;
|
||||
signal DS: std_logic;
|
||||
signal DS_D: std_logic;
|
||||
signal LAN_RD_S: std_logic;
|
||||
signal LAN_WRH_S: std_logic;
|
||||
signal LAN_WRL_S: std_logic;
|
||||
signal LAN_IRQ_D0: std_logic;
|
||||
signal LAN_IRQ_OUT: std_logic;
|
||||
signal CP_RD_S: std_logic;
|
||||
signal CP_WE_S: std_logic;
|
||||
signal CP_WE_QUIRK: std_logic;
|
||||
|
||||
signal LAN_CS_RST: std_logic;
|
||||
signal LAN_WR_RST: std_logic;
|
||||
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
|
||||
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
|
||||
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000";
|
||||
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000";
|
||||
|
||||
Function to_std_logic(X: in Boolean) return Std_Logic is
|
||||
variable ret : std_logic;
|
||||
begin
|
||||
if x then ret := '1'; else ret := '0'; end if;
|
||||
return ret;
|
||||
end to_std_logic;
|
||||
|
||||
begin
|
||||
|
||||
AMIGA_CLK <= not (C1 xor C3);
|
||||
DECODE_RESET <= BERR and reset;
|
||||
|
||||
DS <= UDS and LDS;
|
||||
|
||||
clock_init: process(CLK_EXT)
|
||||
begin
|
||||
if(rising_edge(CLK_EXT))then
|
||||
if(reset = '0')then
|
||||
--init the clock!
|
||||
case LAN_RST_SM is
|
||||
when nop=>
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=wait0;
|
||||
when wait0=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=clr;
|
||||
when clr=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='1';
|
||||
LAN_RST_SM<=clr_commit;
|
||||
when clr_commit=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=wait1;
|
||||
when wait1=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=set;
|
||||
when set=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='1';
|
||||
LAN_RST_SM<=set_commit;
|
||||
when set_commit=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=done;
|
||||
when done=>
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=done;
|
||||
end case;
|
||||
else
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=nop;
|
||||
end if;
|
||||
end if;
|
||||
end process clock_init;
|
||||
|
||||
ADDRESS_DECODE: process(DECODE_RESET,AS)
|
||||
begin
|
||||
if(DECODE_RESET ='0')then
|
||||
autoconfig <= '0';
|
||||
ide <= '0';
|
||||
lan_adr <= '0';
|
||||
lan_adr_sw <= '0';
|
||||
cp <= '0';
|
||||
lancp <= '0';
|
||||
elsif(falling_edge(AS))then
|
||||
--default values
|
||||
autoconfig <= '0';
|
||||
ide <= '0';
|
||||
lan_adr <= '0';
|
||||
lan_adr_sw <= '0';
|
||||
cp <= '0';
|
||||
lancp <= '0';
|
||||
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
|
||||
autoconfig <= '1';
|
||||
elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
|
||||
if(A(14 downto 13)<"11")then
|
||||
lan_adr_sw <= '1';
|
||||
end if;
|
||||
lan_adr <= '1';
|
||||
lancp <= '1';
|
||||
elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
|
||||
cp <= '1';
|
||||
lancp <= '1';
|
||||
elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
|
||||
ide <= '1';
|
||||
lancp <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process ADDRESS_DECODE;
|
||||
|
||||
--LAN interrupt enable
|
||||
lan_int_proc: process (AMIGA_CLK,reset)
|
||||
begin
|
||||
if(reset ='0') then
|
||||
LAN_INT_ENABLE <='0';
|
||||
LAN_IRQ_D0 <='1';
|
||||
LAN_IRQ_OUT <='1';
|
||||
elsif falling_edge(AMIGA_CLK) then
|
||||
LAN_IRQ_D0 <= LAN_INT;
|
||||
if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
|
||||
LAN_IRQ_OUT <='0';
|
||||
elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then
|
||||
LAN_IRQ_OUT <='1';
|
||||
elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
|
||||
LAN_IRQ_OUT <= D(14); --controll lan irq
|
||||
end if;
|
||||
|
||||
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
|
||||
LAN_INT_ENABLE <= D(15);
|
||||
end if;
|
||||
end if;
|
||||
end process lan_int_proc;
|
||||
|
||||
--lan signal generation: all Signals are HIGH active!
|
||||
lan_rw_gen: process (AMIGA_CLK)
|
||||
begin
|
||||
if falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
LAN_RD_S <= '0';
|
||||
LAN_WRH_S <= '0';
|
||||
LAN_WRL_S <= '0';
|
||||
|
||||
if(lan_adr='1' and DS='0' and A(15)='0')then
|
||||
LAN_RD_S <= RW;
|
||||
-- swapped LDS/UDS here: ENC624 is little endian
|
||||
LAN_WRH_S <= not LDS and not RW;
|
||||
LAN_WRL_S <= not UDS and not RW;
|
||||
end if;
|
||||
end if;
|
||||
end process lan_rw_gen;
|
||||
|
||||
--cp signal generation
|
||||
cp_rw_gen: process (AMIGA_CLK)
|
||||
begin
|
||||
if falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
CP_RD_S <= '1';
|
||||
CP_WE_S <= '1';
|
||||
if(cp = '1' and DS='0')then --datastrobe instead of AS!
|
||||
CP_RD_S <= not RW;
|
||||
CP_WE_S <= RW;
|
||||
end if;
|
||||
CP_WE_QUIRK <= CP_WE_S;
|
||||
end if;
|
||||
end process cp_rw_gen;
|
||||
|
||||
--ide signal generation
|
||||
ide_rw_gen: process (reset,AMIGA_CLK)
|
||||
begin
|
||||
if (reset = '0') then
|
||||
IDE_ENABLE <= '1';
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
elsif falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
if(ide='1' and AS='0')then
|
||||
if(RW='0')then
|
||||
--the write goes to the hdd!
|
||||
IDE_ENABLE <= '0'; -- enable IDE on first read
|
||||
IDE_W_S <= '0';
|
||||
else
|
||||
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
|
||||
ROM_OE_S <= not IDE_ENABLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process ide_rw_gen;
|
||||
|
||||
|
||||
--autoconfig
|
||||
autoconfig_proc: process (reset, AMIGA_CLK)
|
||||
begin
|
||||
if reset = '0' then
|
||||
-- reset active ...
|
||||
AUTO_CONFIG_DONE_CYCLE <="00";
|
||||
Dout1<="1111";
|
||||
--Dout2<="1111";
|
||||
SHUT_UP <="111";
|
||||
IDE_BASEADR<=x"FF";
|
||||
LAN_BASEADR<=x"FF";
|
||||
CP_BASEADR<=x"FF";
|
||||
AUTO_CONFIG_DONE <="00";
|
||||
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
|
||||
DS_D <= DS;
|
||||
if(AS='1')then
|
||||
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
|
||||
elsif(autoconfig= '1' and DS='0') then
|
||||
case A(6 downto 1) is
|
||||
when "000000" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
|
||||
else
|
||||
Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
|
||||
end if;
|
||||
when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
|
||||
when "000010" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1000" ; --ProductID high nibble : 7->1000
|
||||
else
|
||||
Dout1 <= "1111" ; --ProductID high nibble : 0->1111
|
||||
end if;
|
||||
when "000011" =>
|
||||
if(AUTO_CONFIG_DONE = 0)then
|
||||
Dout1 <= "0100" ; --ProductID low nibble: B->0100
|
||||
elsif(AUTO_CONFIG_DONE = 1)then
|
||||
Dout1 <= "0011" ; --ProductID low nibble: C->0011
|
||||
else
|
||||
Dout1 <= "1001" ; --ProductID low nibble: 6->1001
|
||||
end if;
|
||||
when "001000" => Dout1 <= "1111" ; --Ventor ID 0
|
||||
when "001001" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "0101" ; --Ventor ID 1
|
||||
else
|
||||
Dout1 <= "0111" ; --Ventor ID 1
|
||||
end if;
|
||||
when "001010" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1110" ; --Ventor ID 2
|
||||
else
|
||||
Dout1 <= "1101" ; --Ventor ID 2
|
||||
end if;
|
||||
when "001011" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
|
||||
else
|
||||
Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC
|
||||
end if;
|
||||
when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble
|
||||
when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble
|
||||
when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble
|
||||
when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble
|
||||
when "010000" => Dout1 <= "1111" ; --Serial byte 2 high nibble
|
||||
when "010001" => Dout1 <= "1111" ; --Serial byte 2 low nibble
|
||||
when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble
|
||||
when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
|
||||
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
|
||||
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
|
||||
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
|
||||
when "010111" =>
|
||||
if(AUTO_CONFIG_DONE = 2)then
|
||||
Dout1 <= "1110" ; --Rom vector low byte low nibble
|
||||
else
|
||||
Dout1 <= "1111" ; --Rom vector low byte low nibble
|
||||
end if;
|
||||
when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero
|
||||
when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero
|
||||
when "100100" =>
|
||||
Dout1 <= "1111" ;
|
||||
if(RW='0' and DS_D='1')then
|
||||
if(AUTO_CONFIG_DONE = 0)then
|
||||
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(0) <='0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= "01"; --done here
|
||||
elsif(AUTO_CONFIG_DONE = 1)then
|
||||
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(1) <= '0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part!
|
||||
elsif(AUTO_CONFIG_DONE = 2)then
|
||||
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(2) <= '0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= "11"; --done here
|
||||
end if;
|
||||
end if;
|
||||
when "100110" =>
|
||||
Dout1 <= "1111" ;
|
||||
if(RW='0' and DS_D='1')then
|
||||
AUTO_CONFIG_DONE_CYCLE <= AUTO_CONFIG_DONE_CYCLE+1; --done here
|
||||
end if;
|
||||
when others => Dout1 <= "1111" ;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process autoconfig_proc; --- that's all
|
||||
|
||||
LAN_CS <= lan_adr when reset='1' else LAN_CS_RST;
|
||||
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
|
||||
LAN_CFG <= "0010"; -- "ZZZZ";
|
||||
|
||||
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||
CP_CS <= not cp;
|
||||
|
||||
--the lanport is shifted by one adress line but I forgot to adopt the clockport address!
|
||||
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip
|
||||
A(14 downto 7);
|
||||
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
|
||||
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(2 downto 1);
|
||||
|
||||
|
||||
|
||||
--signal assignment
|
||||
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
|
||||
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else
|
||||
DQ when RW='1' and ide = '1' and AS='0' else
|
||||
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
|
||||
(others => 'Z');
|
||||
|
||||
--defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
|
||||
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
|
||||
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
|
||||
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
|
||||
D when RW='0' and AS='0' and lancp ='1'
|
||||
else (others => 'Z');
|
||||
|
||||
IDE_W <= IDE_W_S when AS='0' else '1';
|
||||
IDE_R <= IDE_R_S when AS='0' else '1';
|
||||
IDE_CS(0)<= not(A(12));
|
||||
IDE_CS(1)<= not(A(13));
|
||||
IDE_A(2 downto 0) <= A(11 downto 9);
|
||||
ROM_B <= "00";
|
||||
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
|
||||
|
||||
-- INT_OUT <= 'Z';
|
||||
INT2_OUT <= '0' when
|
||||
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
|
||||
else 'Z';
|
||||
|
||||
INT6_OUT <= '0' when
|
||||
CP_IRQ = '0'
|
||||
else 'Z';
|
||||
|
||||
|
||||
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
|
||||
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
|
||||
|
||||
-- OVR <= 'Z';
|
||||
OVR <= '0' when ide='1' and AS='0' else 'Z';
|
||||
|
||||
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or
|
||||
-- AUTOCONFIG_IN_PROGRES ='1'
|
||||
-- else 'Z';
|
||||
|
||||
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
|
||||
-- DTACK <= 'Z';
|
||||
A <= (others => 'Z');
|
||||
MTACK <= 'Z';
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -29,10 +29,10 @@ NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 4418716 kilobytes
|
||||
Total memory usage is 4418708 kilobytes
|
||||
|
||||
Writing NGD file "LAN_IDE_CP.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 5 sec
|
||||
Total CPU time to NGDBUILD completion: 5 sec
|
||||
Total REAL time to NGDBUILD completion: 6 sec
|
||||
Total CPU time to NGDBUILD completion: 6 sec
|
||||
|
||||
Writing NGDBUILD log file "LAN_IDE_CP.bld"...
|
||||
|
||||
@@ -625,3 +625,9 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
|
||||
@@ -53,11 +53,9 @@ DQ<15> S:PIN112
|
||||
DQ<1> S:PIN117
|
||||
DQ<2> S:PIN120
|
||||
DQ<3> S:PIN119
|
||||
DQ<4> S:PIN124
|
||||
DQ<5> S:PIN121
|
||||
DQ<6> S:PIN126
|
||||
DQ<7> S:PIN125
|
||||
DQ<8> S:PIN128
|
||||
DQ<9> S:PIN116
|
||||
D<0> S:PIN2
|
||||
D<10> S:PIN41
|
||||
@@ -116,91 +114,91 @@ A<20> S:PIN91
|
||||
A<21> S:PIN88
|
||||
A<22> S:PIN87
|
||||
A<23> S:PIN86
|
||||
DQ<8> S:PIN128
|
||||
DQ<4> S:PIN124
|
||||
|
||||
|
||||
;The remaining section of the .gyd file is for documentation purposes only.
|
||||
;It shows where your internal equations were placed in the last successful fit.
|
||||
|
||||
PARTITION FB1_1 EXP22_ EXP23_ Z3_ADR<9> Z3_ADR<8>
|
||||
D_5_IOBUFE D_4_IOBUFE Z3_ADR<7> IDE_CS_0_OBUF
|
||||
Z3_ADR<12> IDE_CS_1_OBUF Z3_ADR<11> IDE_A_0_OBUF$BUF0
|
||||
Z3_ADR<10> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 DQ_SWAP
|
||||
IDE_R_OBUF IDE_ACCESS
|
||||
PARTITION FB2_1 $OpTx$FX_DC$74 A_LAN_4_OBUF A_LAN_7_OBUF $OpTx$FX_DC$73
|
||||
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 $OpTx$FX_DC$72 ROM_B_0_OBUF$BUF5
|
||||
SHUT_UP_Z2<2> D_6_IOBUFE SHUT_UP_Z2<1> D_3_IOBUFE
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE<2> D_7_IOBUFE D_1_IOBUFE AUTO_CONFIG_Z2_DONE_CYCLE<1>
|
||||
D_8_IOBUFE AUTO_CONFIG_Z2_DONE_CYCLE<0>
|
||||
PARTITION FB1_1 LAN_BASEADR<9> SHUT_UP_Z2<1> LAN_BASEADR<8> LAN_BASEADR<7>
|
||||
D_5_IOBUFE D_4_IOBUFE LAN_BASEADR<6> IDE_CS_0_OBUF
|
||||
LAN_BASEADR<5> IDE_CS_1_OBUF LAN_BASEADR<3> IDE_A_0_OBUF$BUF0
|
||||
LAN_BASEADR<15> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 LAN_BASEADR<13>
|
||||
IDE_R_OBUF LAN_BASEADR<11>
|
||||
PARTITION FB2_1 IDE_BASEADR<2> A_LAN_4_OBUF A_LAN_7_OBUF IDE_BASEADR<1>
|
||||
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<0> ROM_B_0_OBUF$BUF5
|
||||
DQ_5_IOBUFE/DQ_5_IOBUFE_TRST D_6_IOBUFE DQ<8>_BUFR.MC D_3_IOBUFE
|
||||
EXP24_ D_7_IOBUFE D_1_IOBUFE EXP25_
|
||||
D_8_IOBUFE EXP26_
|
||||
PARTITION FB3_2 IDE_W_OBUF
|
||||
PARTITION FB3_14 ROM_B_0_OBUF$BUF8 ROM_B_0_OBUF$BUF0
|
||||
PARTITION FB3_18 $OpTx$FX_DC$49
|
||||
PARTITION FB4_1 D_Z2_OUT<1> D_0_IOBUFE BUF_D_Z2_OUT<0> BUF_D_Z2_OUT<2>
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF BUF_D_Z2_OUT<3> A_LAN_3_OBUF
|
||||
AUTO_CONFIG_Z2_DONE<0> AUTO_CONFIG_Z2_DONE<1> IDE_ENABLE A_LAN_2_OBUF
|
||||
IDE_R_S A_LAN_5_OBUF IDE_W_S ROM_OE_S
|
||||
CP_RD_S $OpTx$FX_DC$77
|
||||
PARTITION FB5_1 EXP24_ CP_CS_OBUF EXP25_ EXP26_
|
||||
ROM_OE_OBUF
|
||||
PARTITION FB5_9 Z3_DATA<6>/Z3_DATA<6>_TRST D_2_IOBUFE $OpTx$FX_SC$85 D_9_IOBUFE
|
||||
$OpTx$FX_DC$86 D_10_IOBUFE D_11_IOBUFE D_9_IOBUFE/D_9_IOBUFE_TRST
|
||||
D_12_IOBUFE AUTOCONFIG_Z2_ACCESS
|
||||
PARTITION FB6_1 EXP27_ ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF
|
||||
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF
|
||||
PARTITION FB6_8 A_LAN_11_OBUF
|
||||
PARTITION FB6_10 A_LAN_8_OBUF
|
||||
PARTITION FB6_13 $OpTx$FX_DC$46 A_LAN_9_OBUF EXP28_ EXP29_
|
||||
Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2 EXP30_
|
||||
PARTITION FB7_2 D_Z2_OUT<0> D_13_IOBUFE IDE_BASEADR<4> D_14_IOBUFE
|
||||
IDE_BASEADR<3> IDE_BASEADR<2> IDE_BASEADR<1> IDE_BASEADR<0>
|
||||
CP_BASEADR<7> CP_BASEADR<6> D_15_IOBUFE CP_BASEADR<5>
|
||||
CP_BASEADR<4> CP_BASEADR<3> CP_BASEADR<2> CP_BASEADR<1>
|
||||
CP_BASEADR<0>
|
||||
PARTITION FB8_2 DQ_12_IOBUFE DQ_14_IOBUFE
|
||||
PARTITION FB8_5 LAN_WRH_OBUF
|
||||
PARTITION FB8_7 LAN_BASEADR<6> LAN_CS_OBUF LAN_BASEADR<5> LAN_RD_OBUF
|
||||
LAN_BASEADR<4> LAN_BASEADR<3> LAN_BASEADR<2> LAN_BASEADR<15>
|
||||
LAN_BASEADR<14> LAN_BASEADR<13> LAN_BASEADR<11> LAN_BASEADR<10>
|
||||
PARTITION FB3_8 EXP27_ EXP28_ EXP29_ Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000/Mcompar_LAN_ACCESS_cmp_eq0000_AEB_or0000_D2
|
||||
EXP30_ EXP31_ ROM_B_0_OBUF$BUF8 ROM_B_0_OBUF$BUF0
|
||||
|
||||
PARTITION FB9_1 LAN_SM_RST LAN_READY LAN_IRQ_D0 LAN_D_INIT<8>
|
||||
LAN_D_INIT<1> LAN_A_INIT<6> CP_WE_S BUF_LAN_D_INIT<1>
|
||||
LAN_WR_RST LAN_RST_SM_FSM_FFd3 Z3_DATA<0> LAN_RST_SM_FSM_FFd2
|
||||
LAN_RST_SM_FSM_FFd1 Z3_DATA<1> LAN_IRQ_OUT LAN_CS_RST
|
||||
Z3_DATA<2> AUTO_CONFIG_Z2_DONE<2>
|
||||
PARTITION FB10_1 LAN_A_INIT<3> DQ_1_IOBUFE DQ_0_IOBUFE $OpTx$FX_DC$65
|
||||
DQ_3_IOBUFE DQ_2_IOBUFE $OpTx$FX_SC$67 DQ_5_IOBUFE
|
||||
$OpTx$FX_DC$78 DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
DQ_DATA<8> DQ_8_IOBUFE DQ_DATA<2> DQ_DATA<10>
|
||||
DQ_10_IOBUFE DQ_DATA<0>
|
||||
|
||||
PARTITION FB4_1 EXP32_ D_0_IOBUFE IDE_BASEADR<7> IDE_BASEADR<6>
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<5> A_LAN_3_OBUF
|
||||
IDE_BASEADR<4> IDE_BASEADR<3> CP_BASEADR<7> A_LAN_2_OBUF
|
||||
CP_BASEADR<6> A_LAN_5_OBUF CP_BASEADR<5> CP_BASEADR<4>
|
||||
CP_BASEADR<3> SHUT_UP_Z2<2>
|
||||
PARTITION FB5_1 AUTOCONFIG_Z2_ACCESS CP_CS_OBUF EXP33_ EXP34_
|
||||
ROM_OE_OBUF EXP35_ ROM_OE_S IDE_W_S
|
||||
IDE_R_S D_2_IOBUFE IDE_ENABLE D_9_IOBUFE
|
||||
EXP36_ D_10_IOBUFE D_11_IOBUFE D_8_IOBUFE/D_8_IOBUFE_TRST
|
||||
D_12_IOBUFE EXP37_
|
||||
PARTITION FB6_1 LAN_A_INIT<3> ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
||||
A_LAN_13_OBUF A_LAN_10_OBUF LAN_IRQ_D0 A_LAN_11_OBUF
|
||||
CP_WE_QUIRK A_LAN_8_OBUF LAN_WR_RST LAN_RST_SM_FSM_FFd3
|
||||
LAN_RST_SM_FSM_FFd2 A_LAN_9_OBUF LAN_RST_SM_FSM_FFd1 LAN_IRQ_OUT
|
||||
LAN_D_INIT<8> LAN_D_INIT<1>
|
||||
PARTITION FB7_1 D_Z2_OUT<1> EXP38_ D_13_IOBUFE EXP39_
|
||||
D_14_IOBUFE EXP40_ SHUT_UP_Z2<0> EXP41_
|
||||
D_Z2_OUT<0> EXP42_ EXP43_ D_15_IOBUFE
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE<1> EXP44_ D_Z2_OUT<2> EXP45_
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE<2> EXP46_
|
||||
PARTITION FB8_1 EXP47_ DQ_12_IOBUFE DQ_14_IOBUFE EXP48_
|
||||
LAN_WRH_OBUF LAN_BASEADR<2> LAN_BASEADR<1> LAN_CS_OBUF
|
||||
LAN_BASEADR<14> LAN_RD_OBUF LAN_BASEADR<12> LAN_BASEADR<10>
|
||||
LAN_BASEADR<0> CP_BASEADR<2> CP_BASEADR<1> CP_BASEADR<0>
|
||||
LAN_BASEADR<4> EXP49_
|
||||
PARTITION FB9_1 D_Z2_OUT<3> EXP50_ AUTO_CONFIG_Z2_DONE<0> AUTO_CONFIG_Z2_DONE<1>
|
||||
AUTO_CONFIG_Z2_DONE<2> AUTO_CONFIG_Z2_DONE_CYCLE<0> CP_RD_S CP_WE_S
|
||||
DQ_SWAP LAN_ACCESS Z3_DATA<0> Z3_ADR<2>
|
||||
Z3_ADR<3> Z3_DATA<1> Z3_ADR<4> Z3_ADR_0
|
||||
Z3_DATA<2> Z3_ADR_1
|
||||
PARTITION FB10_1 DQ<4>_BUFR.MC DQ_1_IOBUFE DQ_0_IOBUFE EXP51_
|
||||
DQ_3_IOBUFE DQ_2_IOBUFE EXP52_ DQ_5_IOBUFE
|
||||
EXP53_ _19_ DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
EXP54_ _18_ EXP55_ EXP56_
|
||||
DQ_10_IOBUFE EXP57_
|
||||
PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<28>
|
||||
Z3_DATA<4> Z3_DATA<27> Z3_DATA<23> Z3_DATA<22>
|
||||
Z3_DATA<21> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF9
|
||||
Z3_DATA<20> ROM_B_0_OBUF Z3_DATA<19> LAN_SM_FSM_FFd3
|
||||
CP_WE_OBUF Z3_DATA<31>
|
||||
PARTITION FB12_1 LAN_WRL_S ROM_B_0_OBUF$BUF4
|
||||
PARTITION FB12_5 DQ_15_IOBUFE
|
||||
PARTITION FB12_8 DQ_13_IOBUFE
|
||||
PARTITION FB12_10 DQ_11_IOBUFE
|
||||
PARTITION FB12_12 DQ_9_IOBUFE LAN_INT_ENABLE DQ_DATA<9> DQ_DATA<7>
|
||||
DQ_DATA<3> DQ_DATA<1> DQ_DATA<15>
|
||||
PARTITION FB13_2 CP_RD_OBUF
|
||||
PARTITION FB13_4 $OpTx$FX_DC$114 SHUT_UP_Z2<0> LAN_ACCESS D_Z2_OUT<3>
|
||||
Z3_DATA<7> LAN_BASEADR<9> LAN_BASEADR<8> LAN_BASEADR<7>
|
||||
LAN_BASEADR<1> LAN_BASEADR<12> LAN_WRL_OBUF LAN_BASEADR<0>
|
||||
IDE_BASEADR<7> IDE_BASEADR<6> IDE_BASEADR<5>
|
||||
PARTITION FB14_1 ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST $OpTx$FX_DC$95 ROM_B_0_OBUF$BUF2 SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
||||
DQ_8_IOBUFE/DQ_8_IOBUFE_TRST CP_WE_QUIRK Z3_ADR_1 Z3_ADR_0
|
||||
Z3_ADR<6> Z3_ADR<5> CFOUT_OBUF Z3_ADR<4>
|
||||
Z3_ADR<3> SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR<2>
|
||||
Z3_ADR<13> D_Z2_OUT<2>
|
||||
PARTITION FB15_1 DQ_DATA<12> DQ_DATA<13> DQ_DATA<14> DQ_DATA<4>
|
||||
DQ_DATA<5> DQ_DATA<6> BUF_LAN_READY LAN_WRH_S
|
||||
$OpTx$FX_DC$59 $OpTx$FX_DC$106 $OpTx$FX_DC$99 ROM_B_0_OBUF$BUF10
|
||||
|
||||
PARTITION FB15_14 Z3_DATA<15> Z3_DATA<14>
|
||||
PARTITION FB15_17 Z3_DATA<13> EXP31_
|
||||
Z3_DATA<4> Z3_DATA<27> Z3_DATA<22> Z3_DATA<21>
|
||||
Z3_DATA<20> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF9
|
||||
Z3_DATA<19> ROM_B_0_OBUF EXP58_ DQ_DATA<8>
|
||||
CP_WE_OBUF DQ_DATA<0>
|
||||
PARTITION FB12_1 DQ_DATA<11> ROM_B_0_OBUF$BUF4 LAN_SM_RST EXP59_
|
||||
DQ_15_IOBUFE LAN_RD_S EXP60_ DQ_13_IOBUFE
|
||||
EXP61_ DQ_11_IOBUFE EXP62_ DQ_9_IOBUFE
|
||||
LAN_INT_ENABLE LAN_SM_FSM_FFd3 LAN_SM_FSM_FFd2 EXP63_
|
||||
EXP64_ DQ_DATA<3>
|
||||
PARTITION FB13_1 EXP65_ CP_RD_OBUF EXP66_ EXP67_
|
||||
DQ_DATA<7> DQ_DATA<6> EXP68_ Z3_DATA<7>
|
||||
Z3_DATA<31> EXP69_ DQ_DATA<15> DQ_DATA<5>
|
||||
EXP70_ LAN_WRL_OBUF Z3_DATA<23> EXP71_
|
||||
DQ_DATA<13> DQ_DATA<14>
|
||||
PARTITION FB14_1 IDE_ACCESS EXP72_ ROM_B_0_OBUF$BUF2 Z3_ADR<9>
|
||||
Z3_ADR<8> Z3_ADR<7> Z3_ADR<6> Z3_ADR<5>
|
||||
Z3_ADR<13> Z3_ADR<12> CFOUT_OBUF Z3_ADR<11>
|
||||
Z3_ADR<10> SLAVE_OBUF ROM_B_0_OBUF$BUF1 LAN_CS_RST
|
||||
LAN_A_INIT<6> EXP73_
|
||||
PARTITION FB15_1 EXP74_ EXP75_ LAN_WRL_S LAN_READY
|
||||
EXP76_ LAN_SM_FSM_FFd4 LAN_SM_FSM_FFd1 EXP77_
|
||||
DQ_DATA<4> DQ_DATA<9> EXP78_ ROM_B_0_OBUF$BUF10
|
||||
LAN_WRH_S Z3_DATA<15> Z3_DATA<14> Z3_A_LOW
|
||||
Z3_DATA<13> DQ_DATA<1>
|
||||
PARTITION FB16_1 Z3_DATA<26> Z3_DATA<12> Z3_DATA<11> Z3_DATA<25>
|
||||
Z3_DATA<24> Z3_DATA<10> Z3_DATA<18> Z3_DATA<9>
|
||||
Z3_DATA<17> ROM_B_0_OBUF$BUF3 Z3_DATA<8> LAN_RD_S
|
||||
LAN_SM_FSM_FFd2 Z3_A_LOW DQ_DATA<11> LAN_SM_FSM_FFd4
|
||||
LAN_SM_FSM_FFd1 Z3_DATA<16>
|
||||
Z3_DATA<17> ROM_B_0_OBUF$BUF3 Z3_DATA<8> DQ_DATA<2>
|
||||
EXP79_ Z3_DATA<16> EXP80_ EXP81_
|
||||
DQ_DATA<12> DQ_DATA<10>
|
||||
|
||||
|
||||
+1433
-1433
File diff suppressed because it is too large
Load Diff
+4378
-2186
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
2-21-2019 11:26AM
|
||||
2-21-2019 2:00PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
||||
File diff suppressed because one or more lines are too long
+2413
-1723
File diff suppressed because it is too large
Load Diff
@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.14 secs
|
||||
Total CPU time to Xst completion: 0.15 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.14 secs
|
||||
Total CPU time to Xst completion: 0.15 secs
|
||||
|
||||
--> Reading design: LAN_IDE_CP.prj
|
||||
|
||||
@@ -176,7 +176,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found 1-bit register for signal <CP_WE_QUIRK>.
|
||||
Found 1-bit register for signal <CP_WE_S>.
|
||||
Found 4-bit register for signal <D_Z2_OUT>.
|
||||
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 638.
|
||||
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 636.
|
||||
Found 16-bit register for signal <DQ_DATA>.
|
||||
Found 1-bit register for signal <DQ_SWAP>.
|
||||
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 261.
|
||||
@@ -397,21 +397,21 @@ Design Statistics
|
||||
# IOs : 117
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 989
|
||||
# AND2 : 369
|
||||
# AND3 : 16
|
||||
# BELS : 973
|
||||
# AND2 : 363
|
||||
# AND3 : 15
|
||||
# GND : 1
|
||||
# INV : 288
|
||||
# OR2 : 263
|
||||
# OR3 : 16
|
||||
# INV : 284
|
||||
# OR2 : 259
|
||||
# OR3 : 15
|
||||
# OR4 : 3
|
||||
# XOR2 : 33
|
||||
# FlipFlops/Latches : 141
|
||||
# FD : 4
|
||||
# FDC : 20
|
||||
# FDCE : 7
|
||||
# FDP : 42
|
||||
# FDPE : 68
|
||||
# FDP : 41
|
||||
# FDPE : 69
|
||||
# IO Buffers : 115
|
||||
# IBUF : 24
|
||||
# IOBUFE : 48
|
||||
@@ -420,12 +420,12 @@ Cell Usage :
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 19.00 secs
|
||||
Total CPU time to Xst completion: 18.77 secs
|
||||
Total REAL time to Xst completion: 20.00 secs
|
||||
Total CPU time to Xst completion: 20.12 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 4534808 kilobytes
|
||||
Total memory usage is 4534764 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 46 ( 0 filtered)
|
||||
|
||||
@@ -284,6 +284,14 @@ TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<30>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:Z3_DATA<30>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:Z3_DATA<30>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:Z3_DATA<30>.CE:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<31>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:Z3_DATA<31>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:Z3_DATA<31>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:Z3_DATA<31>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_SM_FSM_FFd2.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_SM_FSM_FFd2.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd2.D:400
|
||||
@@ -294,16 +302,16 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd4.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_SM_FSM_FFd4.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_SM_FSM_FFd4.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd4.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd1.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd3.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_SM_FSM_FFd1.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_SM_FSM_FFd1.RSTF:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
|
||||
@@ -485,29 +493,9 @@ TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<9>.SETF:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_WR_RST.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_WR_RST.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<15>.Q:TO:Z3_DATA<31>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:Z3_DATA<31>.SETF:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_A_INIT<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_A_INIT<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_A_INIT<6>.D:400
|
||||
@@ -520,6 +508,16 @@ TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_D_INIT<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_D_INIT<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_D_INIT<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_D_INIT<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:DQ_DATA<7>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:LAN_RD_S.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:LAN_RD_S.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:LAN_RD_S.D:400
|
||||
|
||||
@@ -473,11 +473,9 @@ begin
|
||||
LAN_SM<=end_write_lower; -- stay here until cylce end
|
||||
when config_rw=>
|
||||
LAN_READY <='1';
|
||||
if(RW='1')then
|
||||
Z3_DATA(31) <= LAN_INT_ENABLE;
|
||||
elsif(Z3_DS(3) ='0')then
|
||||
if(Z3_DS(3) ='0' and RW='0')then
|
||||
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
|
||||
elsif(Z3_DS(1) ='0')then
|
||||
elsif(Z3_DS(1) ='0' and RW='0')then
|
||||
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
|
||||
end if;
|
||||
LAN_SM<=config_rw; -- stay here until cylce end
|
||||
|
||||
+13712
-8092
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -1,10 +1,10 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE document SYSTEM 'file:///c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
|
||||
<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
|
||||
|
||||
<document>
|
||||
<design name='LAN_IDE_CP'/>
|
||||
<rptdir name='LAN_IDE_CP'/>
|
||||
<xilinx path='c:/Xilinx/14.7/ISE_DS/ISE;'/>
|
||||
<xilinx path='C:/Xilinx/14.7/ISE_DS/ISE;'/>
|
||||
<projDir path='C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE'/>
|
||||
<xslDir path='chipviewer/data/xsl'/>
|
||||
<fileDir path='/chipviewer/data/html'/>
|
||||
@@ -259,7 +259,7 @@
|
||||
<output file='fbs_FB16.htm'/>
|
||||
</xslFile>
|
||||
</xmlFile>
|
||||
<xmlFile file='c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
|
||||
<xmlFile file='C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
|
||||
<xslFile file='legend.xsl'>
|
||||
<param name='device' value='XC95288XL-10-TQ144'/>
|
||||
<param name='verOn' value='0'/>
|
||||
@@ -271,7 +271,7 @@
|
||||
<output file='pinlegendV.htm'/>
|
||||
</xslFile>
|
||||
</xmlFile>
|
||||
<xmlFile file='c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
|
||||
<xmlFile file='C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
|
||||
<xslFile file='legend.xsl'>
|
||||
<param name='device' value='XC95288XL-10-TQ144'/>
|
||||
<param name='verOn' value='0'/>
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Thu Feb 21 11:11:00 2019">
|
||||
<application stringID="NgdBuild" timeStamp="Thu Feb 21 13:59:34 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -70,31 +70,31 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="369"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="363"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="42"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="68"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="24"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="288"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="284"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="263"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="259"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="369"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="67"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="363"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="66"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="288"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="284"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="263"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="259"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
2-21-2019 11:26AM
|
||||
2-21-2019 2:00PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
||||
|
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Thu Feb 21 11:10:34 2019">
|
||||
<application stringID="Xst" timeStamp="Thu Feb 21 13:59:05 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -119,20 +119,20 @@
|
||||
<item stringID="XST_IOS" value="117"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="989">
|
||||
<item dataType="int" stringID="XST_AND2" value="369"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="16"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="973">
|
||||
<item dataType="int" stringID="XST_AND2" value="363"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="15"/>
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="288"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="263"/>
|
||||
<item dataType="int" stringID="XST_INV" value="284"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="259"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="33"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="141">
|
||||
<item dataType="int" stringID="XST_FD" value="4"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="20"/>
|
||||
<item dataType="int" stringID="XST_FDCE" value="7"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="42"/>
|
||||
<item dataType="int" stringID="XST_FDPE" value="68"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="41"/>
|
||||
<item dataType="int" stringID="XST_FDPE" value="69"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="115">
|
||||
<item dataType="int" stringID="XST_IBUF" value="24"/>
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1550743853
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1550753965
|
||||
OK
|
||||
|
||||
@@ -17,5 +17,11 @@
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">MTCR</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ<8></arg> to allow all signals assigned to this function block to be placed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ<4></arg> to allow all signals assigned to this function block to be placed.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Thu Feb 21 11:10:33 2019">
|
||||
<application name="pn" timeStamp="Thu Feb 21 13:59:04 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user