intermediate
This commit is contained in:
@@ -3,14 +3,14 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.14 secs
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.14 secs
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Reading design: LAN_IDE_CP.prj
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@@ -111,7 +111,6 @@ Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <CONFIG_READY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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-----------------------------------------------------------------------
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@@ -166,30 +165,30 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 178.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 176.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
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Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
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Found 1-bit register for signal <CP_ACCESS>.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 291.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 289.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_QUIRK>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <D_Z2_OUT>.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 638.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 629.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 260.
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Found 1-bit register for signal <IDE_ACCESS>.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 298.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 296.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 261.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 259.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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@@ -198,7 +197,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 388.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 386.
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Found 1-bit register for signal <LAN_SM_RST>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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@@ -210,7 +209,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 32-bit register for signal <Z3_DATA>.
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 74 D-type flip-flop(s).
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inferred 58 D-type flip-flop(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 58 Tristate(s).
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@@ -221,10 +220,10 @@ Unit <LAN_IDE_CP> synthesized.
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HDL Synthesis Report
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Macro Statistics
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# Registers : 85
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1-bit register : 77
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# Registers : 70
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1-bit register : 61
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14-bit register : 2
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16-bit register : 2
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16-bit register : 3
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3-bit register : 1
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4-bit register : 1
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8-bit register : 2
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@@ -305,8 +304,8 @@ Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# Registers : 74
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Flip-Flops : 74
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# Registers : 58
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Flip-Flops : 58
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# Comparators : 3
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16-bit comparator equal : 1
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8-bit comparator equal : 2
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@@ -342,12 +341,12 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
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implementation constraint: INIT=r : LAN_INT_ENABLE
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
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implementation constraint: INIT=s : D_Z2_OUT_3
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implementation constraint: INIT=s : LAN_A_INIT_3
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implementation constraint: INIT=s : D_Z2_OUT_2
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@@ -358,8 +357,8 @@ Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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@@ -398,14 +397,14 @@ Design Statistics
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# IOs : 117
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Cell Usage :
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# BELS : 975
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# AND2 : 364
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# BELS : 966
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# AND2 : 362
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# AND3 : 15
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# GND : 1
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# INV : 285
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# INV : 280
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# OR2 : 259
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# OR3 : 15
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# OR4 : 3
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# OR3 : 14
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# OR4 : 2
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# XOR2 : 33
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# FlipFlops/Latches : 141
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# FD : 4
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@@ -422,13 +421,13 @@ Cell Usage :
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Total REAL time to Xst completion: 19.00 secs
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Total CPU time to Xst completion: 18.75 secs
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Total CPU time to Xst completion: 18.56 secs
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-->
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Total memory usage is 4534744 kilobytes
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Total memory usage is 4534820 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 47 ( 0 filtered)
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Number of warnings : 46 ( 0 filtered)
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Number of infos : 10 ( 0 filtered)
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