Dominick.Vansevenant/Zorro-LAN-IDE
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intermediate

Browse Source
This commit is contained in:
MHeinrichs
2019-02-21 14:47:36 +01:00
parent 18ab58e394
commit b1854c3f8c
23 changed files with 10961 additions and 10976 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE/LAN_IDE_CP.bld
+1 -1
View File
@@ -29,7 +29,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 4418688 kilobytes
Total memory usage is 4418712 kilobytes
Writing NGD file "LAN_IDE_CP.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Logic/LAN_IDE/LAN_IDE_CP.cmd_log
+18
View File
@@ -11,3 +11,21 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE/LAN_IDE_CP.gyd
+9 -9
View File
@@ -121,11 +121,11 @@ DQ<4> S:PIN124
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 AUTO_CONFIG_Z2_DONE_CYCLE<2> AUTO_CONFIG_Z2_DONE_CYCLE<1> LAN_BASEADR<9> LAN_BASEADR<7>
D_5_IOBUFE D_4_IOBUFE LAN_BASEADR<5> IDE_CS_0_OBUF
LAN_BASEADR<2> IDE_CS_1_OBUF LAN_BASEADR<1> IDE_A_0_OBUF$BUF0
LAN_BASEADR<15> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 LAN_BASEADR<13>
IDE_R_OBUF LAN_BASEADR<10>
PARTITION FB1_1 SHUT_UP_Z2<0> AUTO_CONFIG_Z2_DONE_CYCLE<2> LAN_BASEADR<9> LAN_BASEADR<8>
D_5_IOBUFE D_4_IOBUFE LAN_BASEADR<7> IDE_CS_0_OBUF
LAN_BASEADR<6> IDE_CS_1_OBUF LAN_BASEADR<5> IDE_A_0_OBUF$BUF0
LAN_BASEADR<4> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 LAN_BASEADR<3>
IDE_R_OBUF LAN_BASEADR<2>
PARTITION FB2_1 DQ<8>_BUFR.MC A_LAN_4_OBUF A_LAN_7_OBUF IDE_BASEADR<3>
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<2> ROM_B_0_OBUF$BUF5
IDE_BASEADR<1> D_6_IOBUFE EXP24_ D_3_IOBUFE
@@ -151,15 +151,15 @@ PARTITION FB6_1 LAN_IRQ_D0 ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF CP_WE_QUIRK
Z3_ADR<4> A_LAN_8_OBUF Z3_ADR<13> Z3_ADR<12>
Z3_ADR<11> A_LAN_9_OBUF LAN_IRQ_OUT LAN_A_INIT<6>
LAN_ACCESS DQ_SWAP
PARTITION FB7_1 SHUT_UP_Z2<0> EXP39_ D_13_IOBUFE
PARTITION FB7_1 AUTO_CONFIG_Z2_DONE_CYCLE<1> EXP39_ D_13_IOBUFE
PARTITION FB7_5 D_14_IOBUFE EXP40_ EXP41_ EXP42_
D_Z2_OUT<1> EXP43_ EXP44_ D_15_IOBUFE
EXP45_ D_Z2_OUT<2> EXP46_ EXP47_
D_Z2_OUT<0> EXP48_
PARTITION FB8_1 EXP49_ DQ_12_IOBUFE DQ_14_IOBUFE EXP50_
LAN_WRH_OBUF LAN_BASEADR<8> LAN_BASEADR<6> LAN_CS_OBUF
LAN_BASEADR<4> LAN_RD_OBUF LAN_BASEADR<3> LAN_BASEADR<14>
LAN_BASEADR<12> LAN_BASEADR<11> LAN_BASEADR<0> CP_BASEADR<3>
LAN_WRH_OBUF LAN_BASEADR<1> LAN_BASEADR<15> LAN_CS_OBUF
LAN_BASEADR<14> LAN_RD_OBUF LAN_BASEADR<13> LAN_BASEADR<12>
LAN_BASEADR<11> LAN_BASEADR<10> LAN_BASEADR<0> CP_BASEADR<3>
EXP51_ SHUT_UP_Z2<1>
PARTITION FB9_1 D_Z2_OUT<3> EXP52_ AUTOCONFIG_Z2_ACCESS AUTO_CONFIG_Z2_DONE<0>
AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<2> AUTO_CONFIG_Z2_DONE_CYCLE<0> CP_RD_S
Logic/LAN_IDE/LAN_IDE_CP.jed
+1049 -1049
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.mfd
+801 -800
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.nga
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.ngc
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.ngd
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.ngr
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.pad
+1 -1
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-21-2019 2:29PM
2-21-2019 2:45PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
Logic/LAN_IDE/LAN_IDE_CP.pnx
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.rpt
+341 -339
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.syr
+31 -32
View File
@@ -3,14 +3,14 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: LAN_IDE_CP.prj
@@ -111,7 +111,6 @@ Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <CONFIG_READY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
@@ -166,30 +165,30 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 178.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 176.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CP_ACCESS>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 291.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 289.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 638.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 629.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 260.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 298.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 296.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 261.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 259.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
@@ -198,7 +197,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 388.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 386.
Found 1-bit register for signal <LAN_SM_RST>.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
@@ -210,7 +209,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 32-bit register for signal <Z3_DATA>.
Summary:
inferred 2 Finite State Machine(s).
inferred 74 D-type flip-flop(s).
inferred 58 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
inferred 58 Tristate(s).
@@ -221,10 +220,10 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Registers : 85
1-bit register : 77
# Registers : 70
1-bit register : 61
14-bit register : 2
16-bit register : 2
16-bit register : 3
3-bit register : 1
4-bit register : 1
8-bit register : 2
@@ -305,8 +304,8 @@ Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 74
Flip-Flops : 74
# Registers : 58
Flip-Flops : 58
# Comparators : 3
16-bit comparator equal : 1
8-bit comparator equal : 2
@@ -342,12 +341,12 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=s : D_Z2_OUT_2
@@ -358,8 +357,8 @@ Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
@@ -398,14 +397,14 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 975
# AND2 : 364
# BELS : 966
# AND2 : 362
# AND3 : 15
# GND : 1
# INV : 285
# INV : 280
# OR2 : 259
# OR3 : 15
# OR4 : 3
# OR3 : 14
# OR4 : 2
# XOR2 : 33
# FlipFlops/Latches : 141
# FD : 4
@@ -422,13 +421,13 @@ Cell Usage :
Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 18.75 secs
Total CPU time to Xst completion: 18.56 secs
-->
Total memory usage is 4534744 kilobytes
Total memory usage is 4534820 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 47 ( 0 filtered)
Number of warnings : 46 ( 0 filtered)
Number of infos : 10 ( 0 filtered)
Logic/LAN_IDE/LAN_IDE_CP.vhd
+2 -11
View File
@@ -135,7 +135,6 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
@@ -173,7 +172,6 @@ architecture Behavioral of LAN_IDE_CP is
begin
Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
Z3_DS <= UDS & LDS & DS1 & DS0;
AMIGA_CLK <= not (C1 xor C3);
DS <= UDS and LDS;
@@ -562,19 +560,12 @@ begin
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
Logic/LAN_IDE/LAN_IDE_CP.vm6
+8680 -8703
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.xml
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
+9 -9
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Feb 21 14:29:22 2019">
<application stringID="NgdBuild" timeStamp="Thu Feb 21 14:45:11 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -70,7 +70,7 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="364"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="362"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="20"/>
@@ -79,23 +79,23 @@
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="285"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="280"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="259"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="364"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="362"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="285"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="280"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="259"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
</section>
Logic/LAN_IDE/LAN_IDE_CP_pad.csv
+1 -1
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-21-2019 2:29PM
2-21-2019 2:45PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 2-21-2019 2:29PM 2-21-2019 2:45PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
+10 -10
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Feb 21 14:28:56 2019">
<application stringID="Xst" timeStamp="Thu Feb 21 14:44:46 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -79,10 +79,10 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="85">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="77"/>
<item dataType="int" stringID="XST_REGISTERS" value="70">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="61"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
@@ -97,8 +97,8 @@
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_REGISTERS" value="74">
<item dataType="int" stringID="XST_FLIPFLOPS" value="74"/>
<item dataType="int" stringID="XST_REGISTERS" value="58">
<item dataType="int" stringID="XST_FLIPFLOPS" value="58"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
</section>
@@ -119,11 +119,11 @@
<item stringID="XST_IOS" value="117"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="975">
<item dataType="int" stringID="XST_AND2" value="364"/>
<item dataType="int" stringID="XST_BELS" value="966">
<item dataType="int" stringID="XST_AND2" value="362"/>
<item dataType="int" stringID="XST_AND3" value="15"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="285"/>
<item dataType="int" stringID="XST_INV" value="280"/>
<item dataType="int" stringID="XST_OR2" value="259"/>
<item dataType="int" stringID="XST_XOR2" value="33"/>
</item>
@@ -142,7 +142,7 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="47"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="46"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
</section>
</application>
Logic/LAN_IDE/_ngo/netlist.lst
+1 -1
View File
@@ -1,2 +1,2 @@
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1550755755
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1550756704
OK
Logic/LAN_IDE/_xmsgs/xst.xmsgs
-3
View File
@@ -32,9 +32,6 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">CONFIG_READY</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="1799" delta="old" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM &lt;<arg fmt="%s" index="2">LAN_SM</arg>&gt;.
</msg>
Logic/LAN_IDE/webtalk_pn.xml
+1 -1
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Feb 21 14:28:55 2019">
<application name="pn" timeStamp="Thu Feb 21 14:44:45 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd
BIN
View File
Binary file not shown.