Updated LAN driver
- changed directory layout - Multicast support (automatic RX filter adjustment) - MC68000 target in Makefile - clarified licensing (GPLv3) - README files
This commit is contained in:
Henryk Richter
@@ -0,0 +1,733 @@
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/*
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Microchip ENC28J60 Ethernet Interface Driver
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Author: Henryk Richter
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Copyright: GPL V2
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Notes: when I ran into timing issues in early development, I moved over to quickly
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testable ASM code for SPI communication. I didn't bother porting that stuff
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back into C code. So this file now references enc28j60l.asm for lowlevel direct
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hardware access.
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As a consequence, the only functions needed from spi.c are the spi_init() and
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spi_disable_eth().
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TODO: - support for power down when unused, i.e. offline
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- replace busy waiting loop after reset
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Based on work by
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Christian Vogelgsaang
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Guido Socher
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Pascal Stang (see enc28j60.c in AVRlib library for the original file)
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*/
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#undef _DO_DUMP
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/* used for Delay() */
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#include <dos/dos.h>
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#include <proto/dos.h>
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#ifdef _DO_DUMP
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#include <stdio.h>
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#endif
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#include "compiler.h"
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#include "enc28j60.h"
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#include "enc28j60l.h" /* import lowlevel asm functions */
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/* #include "spi.h" */ /* no direct use anymore, just for init purposes) */
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#include "device.h"
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/*
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The RXSTART_INIT must be zero. See Rev. B4 Silicon Errata point 5.
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Buffer boundaries applied to internal 8K ram
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the entire available packet buffer space is allocated
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rx packet layout
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6 byte heaader
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1518
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sum: 1524
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*/
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#define RXSTART_INIT 0x0000 /* start of RX buffer, room for 4 packets */
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#define RXSTOP_INIT 0x19FF /* end of RX buffer */
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#define TXSTART_INIT 0x1A00 /* start of TX buffer, room for 1 packet */
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#define TXSTOP_INIT 0x1FFF /* end of TX buffer */
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/* max frame length which the conroller will accept: */
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/* (note: maximum ethernet frame length would be 1518 when VLAN tagging is unused) */
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#define MAX_FRAMELEN 1518
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static u16 gNextPacketPtr;
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static u08 is_full_duplex;
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static u08 rev;
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struct enc28j60_initvars {
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u16 have_recv;
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u08 last_mac[6];
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u08 macon1;
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u08 macon2;
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u08 macon3;
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u08 macon4;
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};
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static struct enc28j60_initvars initvars;
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static void enc28j60_recv_reset( struct enc28j60_initvars *iv, u08 restart );
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static int enc28j60_check_config( struct enc28j60_initvars *iv );
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static uint8_t readOp (uint8_t op, uint8_t address)
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{
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return enc28j60l_ReadOp( op, address );
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}
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static void writeOp (uint8_t op, uint8_t address, uint8_t data)
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{
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enc28j60l_WriteOp( op, address,data );
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}
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static void readBuf(uint16_t len, uint8_t* data)
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{
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enc28j60l_ReadBuffer( data, (unsigned int)len );
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}
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void SetBank (uint8_t address)
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{
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enc28j60l_SetBank(address);
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}
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static uint8_t readRegByte (uint8_t address)
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{
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return enc28j60l_ReadRegByte( address );
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}
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#if 0
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static uint16_t readReg(uint8_t address) {
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return readRegByte(address) + (readRegByte(address+1) << 8);
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}
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#endif
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static void writeRegByte (uint8_t address, uint8_t data)
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{
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enc28j60l_WriteRegByte( address, data );
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}
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static void writeReg(uint8_t address, uint16_t data)
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{
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enc28j60l_WriteReg( address, data );
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}
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/*
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the PHY registers require special care
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*/
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static uint16_t readPhyByte (uint8_t address) {
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writeRegByte(MIREGADR, address);
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writeRegByte(MICMD, MICMD_MIIRD);
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while (readRegByte(MISTAT) & MISTAT_BUSY)
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;
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writeRegByte(MICMD, 0x00);
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return readRegByte(MIRD+1);
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}
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static void writePhy (uint8_t address, uint16_t data) {
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writeRegByte(MIREGADR, address);
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writeReg(MIWR, data);
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while (readRegByte(MISTAT) & MISTAT_BUSY)
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;
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}
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/* just a pass-through to the lowlevel routines */
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void enc28j60_SetSPISpeed( unsigned long clock_divider )
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{
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enc28j60l_SetSPISpeed( clock_divider );
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}
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/* ---------- init ---------- */
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/* Functions to enable/disable broadcast filter bits */
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/* With the bit set, broadcast packets are filtered. */
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void enc28j60_broadcast_multicast_filter( u08 flags )
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{
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u08 val = ERXFCON_UCEN|ERXFCON_CRCEN; /* default: crc check and unicast */
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if( flags & PIO_INIT_PROMISC )
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{
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val = 0;
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}
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else
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{
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if( flags & PIO_INIT_BROAD_CAST )
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val |= ERXFCON_BCEN;
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if( flags & PIO_INIT_MULTI_CAST )
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val |= ERXFCON_MCEN;
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}
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writeRegByte(ERXFCON, val );
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}
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static void enc28j60_recv_reset( struct enc28j60_initvars *iv, u08 restart )
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{
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXRST);
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXRST);
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writeOp(ENC28J60_BIT_FIELD_CLR, ESTAT, ESTAT_TXABRT);
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gNextPacketPtr = RXSTART_INIT;
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writeReg(ERXST, RXSTART_INIT);
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writeReg(ERXRDPT, RXSTOP_INIT );
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writeReg(ERXND, RXSTOP_INIT);
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writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF|EIR_RXERIF );
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writeReg(MAMXFL, MAX_FRAMELEN);
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writeRegByte(MACON4, iv->macon4 ); /* DEFER bit */
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writeRegByte(MACON3, iv->macon3 );
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writeRegByte(MACON2, iv->macon2 );
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writeRegByte(MACON1, iv->macon1 );
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enc28j60_setMAC( iv->last_mac );
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writePhy(PHIE, PHIE_PGEIE|PHIE_LNKIE );
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writePhy(PHLCON, 0x3c12 ); /* 3(fixed) C(LinkStat+RX Act) 1(TX Act) 2(Stretch enable) */
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/* prepare flow control */
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writeReg(EPAUS, 20 * 100); /* 100ms */
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if( restart )
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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iv->have_recv = 0;
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}
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static int enc28j60_check_config( struct enc28j60_initvars *iv )
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{
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int ret = 1; /* def: be optimistic */
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/* check RX registers */
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if( !(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_RXEN ) )
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ret = 0;
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if( (readRegByte(MACON1)&iv->macon1) != iv->macon1 )
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ret = 0;
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if( (readRegByte(MACON2)&iv->macon2) != iv->macon2 )
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ret = 0;
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if( (readRegByte(MACON3)&iv->macon3) != iv->macon3 )
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ret = 0;
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/* check TX problems */
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if( readRegByte(ESTAT) & ESTAT_TXABRT )
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ret = 0;
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if( readRegByte(EIR) & EIR_TXERIF )
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ret = 0;
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/* Verify MAC */
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if( readRegByte(MAADR5) != iv->last_mac[0] )
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ret = 0;
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if( readRegByte(MAADR4) != iv->last_mac[1] )
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ret = 0;
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if( readRegByte(MAADR3) != iv->last_mac[2] )
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ret = 0;
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if( readRegByte(MAADR2) != iv->last_mac[3] )
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ret = 0;
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if( readRegByte(MAADR1) != iv->last_mac[4] )
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ret = 0;
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if( readRegByte(MAADR0) != iv->last_mac[5] )
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ret = 0;
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return ret;
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}
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u08 enc28j60_init(const u08 macaddr[6], u08 flags)
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{
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unsigned int count;
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u08 mac3val;
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struct enc28j60_initvars *iv = &initvars;
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enc28j60l_Init(); /* spi_init(); spi_disable_eth(); */
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{
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int i;
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for(i=0 ; i < 6 ; i++ )
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iv->last_mac[i] = macaddr[i];
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}
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is_full_duplex = (flags & PIO_INIT_FULL_DUPLEX) == PIO_INIT_FULL_DUPLEX;
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/* soft reset cpu */
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writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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#if 1
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enc28j60l_UMinDelay( 2000 ); /* wait 2 ms */
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#else
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/* Delay(1);*/ /* _delay_ms(2); // errata B7/2 */
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/* hard-coded delay right now (TODO: import timer functions) */
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for( count = 0 ; count < 20000 ; count++ )
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{
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mac3val |= (u08)*((volatile unsigned short*)(0x00DE0004));
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}
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#endif
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/* wait or error */
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count = 0;
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while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY) {
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count ++;
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if(count == 0xfff) {
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return PIO_NOT_FOUND;
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}
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}
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writeOp(ENC28J60_WRITE_CTRL_REG, ECON1, 0);
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/* return rev */
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rev = readRegByte(EREVID);
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/* microchip forgot to step the number on the silcon when they */
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/* released the revision B7. 6 is now rev B7. We still have */
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/* to see what they do when they release B8. At the moment */
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/* there is no B8 out yet */
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if ( (rev < 1) || (rev > 10) ) /* I don't expect a rev > 10 (+1), so I use it to check for module presence */
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return PIO_NOT_FOUND; /* important: check this before any writePhy -> no module gets us 0xff back */
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if (rev > 5) ++rev;
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writeReg(ETXST, TXSTART_INIT);
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writeReg(ETXND, TXSTOP_INIT);
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/* set packet filter */
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enc28j60_broadcast_multicast_filter( flags );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
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/* BIST pattern generator? */
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writeReg(EPMM0, 0x303f);
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writeReg(EPMCS, 0xf7f9);
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if(is_full_duplex) {
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writeRegByte(MABBIPG, 0x15);
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writeReg(MAIPG, 0x0012);
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} else {
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writeRegByte(MABBIPG, 0x12);
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writeReg(MAIPG, 0x0C12);
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}
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/* MAC init (with flow control) */
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mac3val = MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN;
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if(is_full_duplex) {
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mac3val |= MACON3_FULDPX;
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iv->macon4=0;
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}
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else
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{
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iv->macon4 = 1<<6; /* DEFER bit */
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}
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iv->macon3 = mac3val;
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iv->macon2 = 0x00;
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iv->macon1 = MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS;
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/* set packet pointers */
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enc28j60_recv_reset( iv, 0 );
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/* PHY init */
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if(is_full_duplex) {
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writePhy(PHCON1, PHCON1_PDPXMD);
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writePhy(PHCON2, 0);
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} else {
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writePhy(PHCON1, 0);
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writePhy(PHCON2, PHCON2_HDLDIS);
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}
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writePhy(PHLCON, 0x3c12 ); /* 3(fixed) C(LinkStat+RX Act) 1(TX Act) 2(Stretch enable) */
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SetBank(EIR);
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writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF|EIR_LINKIF|EIR_TXIF|EIR_TXERIF|EIR_RXERIF|EIR_PKTIF);
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writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE|EIE_LINKIE|EIE_TXIE|EIE_TXERIE|EIE_RXERIE);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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/* wait a while for "LINK UP" -> break after 200 ms */
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{
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unsigned char status;
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int runs = 100;
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while( runs-- )
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{
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enc28j60_status( PIO_STATUS_LINK_UP, &status );
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if( status )
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break;
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enc28j60l_UMinDelay( 2000 ); /* wait 2+ ms */
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}
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}
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return PIO_OK;
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}
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/* ---------- exit ---------- */
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void enc28j60_exit(void)
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{
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enc28j60_setOffline();
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enc28j60l_Shutdown();
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}
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u08 enc28j60_setOnline( void )
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{
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SetBank(EIR);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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return 1;
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}
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u08 enc28j60_setOffline( void )
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{
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SetBank(EIR);
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
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return 1;
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}
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void enc28j60_setMAC( const u08 macaddr[6] )
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{
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/* set mac */
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writeRegByte(MAADR5, macaddr[0]);
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writeRegByte(MAADR4, macaddr[1]);
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writeRegByte(MAADR3, macaddr[2]);
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writeRegByte(MAADR2, macaddr[3]);
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writeRegByte(MAADR1, macaddr[4]);
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writeRegByte(MAADR0, macaddr[5]);
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SetBank(EIR);
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}
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void enc28j60_getMAC( u08 macaddr[6] ) /* mainly for debug */
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{
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/* set mac */
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macaddr[0] = readRegByte(MAADR5);
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macaddr[1] = readRegByte(MAADR4);
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macaddr[2] = readRegByte(MAADR3);
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macaddr[3] = readRegByte(MAADR2);
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macaddr[4] = readRegByte(MAADR1);
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macaddr[5] = readRegByte(MAADR0);
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}
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/* ---------- control ---------- */
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u08 enc28j60_control(u08 control_id, u08 value)
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{
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switch(control_id) {
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case PIO_CONTROL_FLOW:
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{
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u08 flag;
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if(is_full_duplex) {
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flag = value ? 2 : 3;
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} else {
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flag = value ? 1 : 0;
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}
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writeRegByte(EFLOCON, flag);
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return PIO_OK;
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}
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default:
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return PIO_NOT_FOUND;
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}
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}
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/* ---------- status ---------- */
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u08 enc28j60_status(u08 status_id, u08 *value)
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{
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switch(status_id) {
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case PIO_STATUS_VERSION:
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*value = rev;
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return PIO_OK;
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case PIO_STATUS_LINK_UP:
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*value = (readPhyByte(PHSTAT2) >> 2) & 1;
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return PIO_OK;
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default:
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*value = 0;
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return PIO_NOT_FOUND;
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}
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}
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/* ---------- send ---------- */
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u08 enc28j60_send(const u08 *data, u16 size)
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{
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/* wait for tx ready */
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/* We can't do it here like on ATMEL MCUs, simply because
|
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the Vampire SPI is way faster than 10 MBit/s so that
|
||||
we would overwrite a frame still being sent out
|
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-> wait first, then fill buffer
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*/
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while (readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_TXRTS)
|
||||
{
|
||||
/* errata sheet issue 12 -> TXRTS never becomes 0 */
|
||||
/* ignores errata issue 13 -> frame loss due to late collision */
|
||||
/* eworks around errata sheet issue 15 -> ESTAT.LATECOL not set */
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||||
if (readRegByte(EIR) & EIR_TXERIF) {
|
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
|
||||
}
|
||||
}
|
||||
|
||||
/* write buffer */
|
||||
enc28j60l_WriteBuffer( (u08*)data, size, TXSTART_INIT );
|
||||
|
||||
/* initiate send */
|
||||
writeReg(ETXND, TXSTART_INIT+size);
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
|
||||
return PIO_OK;
|
||||
}
|
||||
|
||||
/* ---------- recv ---------- */
|
||||
|
||||
/*
|
||||
unrecoverable error in receiving, bad pointer or other causes
|
||||
- reset the complete receive logic in order to start receiving anew
|
||||
|
||||
input: restart - 0 = don't re-enable RX automatically
|
||||
1 = re-enable RX after resetting
|
||||
*/
|
||||
|
||||
INLINE void next_pkt(void)
|
||||
{
|
||||
|
||||
if (gNextPacketPtr - 1 > RXSTOP_INIT)
|
||||
{
|
||||
#if 1
|
||||
enc28j60_recv_reset( &initvars, 1 );
|
||||
#else
|
||||
writeReg(ERXRDPT, RXSTOP_INIT);
|
||||
gNextPacketPtr = 0;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
writeReg(ERXRDPT, gNextPacketPtr - 1);
|
||||
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
|
||||
}
|
||||
|
||||
/* endian agnostic version of header read */
|
||||
static u08 read_hdr(u16 *got_size)
|
||||
{
|
||||
struct {
|
||||
uint8_t nextPacketL;
|
||||
uint8_t nextPacketH;
|
||||
uint8_t byteCountL;
|
||||
uint8_t byteCountH;
|
||||
uint8_t statusL;
|
||||
uint8_t statusH;
|
||||
} header;
|
||||
|
||||
readBuf(sizeof header, (uint8_t*) &header);
|
||||
|
||||
gNextPacketPtr = (u16)header.nextPacketL + (((u16)header.nextPacketH)<<8);
|
||||
*got_size = (u16)header.byteCountL + (((u16)header.byteCountH)<<8); /* - 4;*//* -4: remove the CRC count */
|
||||
|
||||
return header.statusL;
|
||||
}
|
||||
|
||||
|
||||
u08 enc28j60_recv(u08 *data, u16 max_size, u16 *got_size)
|
||||
{
|
||||
u08 status,result;
|
||||
u16 len;
|
||||
|
||||
/* EIR->PKTIF would be faster but errata sheet says "unreliable" */
|
||||
u08 pcnt = 1+readRegByte(EPKTCNT); /* wraps to 0 for 0xff = unconnected module */
|
||||
if( pcnt < 2 ) /* 0xff+1=0x00, 0x00+1=0x01, 0x01+1=0x02 */
|
||||
return PIO_NOT_FOUND;
|
||||
|
||||
writeReg(ERDPT, gNextPacketPtr);
|
||||
|
||||
/* read chip's packet header */
|
||||
status = read_hdr(got_size);
|
||||
|
||||
/* was a receive error? */
|
||||
if ((status & 0x80)==0)
|
||||
{
|
||||
/* TODO: recv reset ? */
|
||||
next_pkt();
|
||||
return PIO_IO_ERR;
|
||||
}
|
||||
|
||||
/* check size */
|
||||
len = *got_size;
|
||||
result = PIO_OK;
|
||||
if(len > max_size) {
|
||||
len = max_size;
|
||||
result = PIO_TOO_LARGE;
|
||||
}
|
||||
|
||||
/* read packet */
|
||||
readBuf(len, data);
|
||||
|
||||
next_pkt();
|
||||
return result;
|
||||
}
|
||||
|
||||
/* ---------- has_recv ---------- */
|
||||
|
||||
u08 enc28j60_has_recv(void)
|
||||
{
|
||||
u08 ret = readRegByte(EPKTCNT);
|
||||
|
||||
if( !ret )
|
||||
{
|
||||
initvars.have_recv++;
|
||||
if( initvars.have_recv > 10 )
|
||||
{
|
||||
/* check for bad config vars and reset hw if that is the case */
|
||||
if( !enc28j60_check_config( &initvars ) )
|
||||
{
|
||||
enc28j60_recv_reset( &initvars, 1 );
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
initvars.have_recv = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void enc28j60_dump_regs(void)
|
||||
{
|
||||
/* this will work only with DOSBase known globally, not when it's redirected to Plipbase */
|
||||
#ifdef _DO_DUMP
|
||||
u08 val,eir,eie,econ1,econ2,estat;
|
||||
u16 erxrdpt,erxwrpt,erxst,erxnd,mamxfll;
|
||||
u16 macon1,macon3,macon4;
|
||||
|
||||
eir = readRegByte(EIR);
|
||||
eie = readRegByte(EIE);
|
||||
econ1 = readRegByte(ECON1);
|
||||
econ2 = readRegByte(ECON2);
|
||||
estat = readRegByte(ESTAT);
|
||||
printf("EIR EIE ECON1 ECON2 ESTAT\n");
|
||||
printf("%02x %02x %02x %02x %02x\n",
|
||||
eir,eie,econ1,econ2,estat);
|
||||
|
||||
erxrdpt = readRegByte(ERXRDPT) + (((u16)readRegByte(ERXRDPT+1))<<8);
|
||||
erxwrpt = readRegByte(ERXWRPT) + (((u16)readRegByte(ERXWRPT+1))<<8);
|
||||
erxst = readRegByte(ERXST) + (((u16)readRegByte(ERXST+1))<<8);
|
||||
erxnd = readRegByte(ERXND) + (((u16)readRegByte(ERXND+1))<<8);
|
||||
mamxfll = readRegByte(MAMXFL) + (((u16)readRegByte(MAMXFL+1))<<8);
|
||||
printf("ERXRDPT ERXWRPT ERXST ERXND MAMXFL\n");
|
||||
printf("%04x %04x %04x %04x %04x\n",
|
||||
erxrdpt,erxwrpt,erxst,erxnd,mamxfll);
|
||||
|
||||
macon1 = readRegByte(MACON1);/* + (((u16)readRegByte(MACON1+1))<<8); */
|
||||
macon3 = readRegByte(MACON3);/* + (((u16)readRegByte(MACON1+3))<<8); */
|
||||
macon4 = readRegByte(MACON4);/* + (((u16)readRegByte(MACON1+4))<<8); */
|
||||
printf("MACON1 MACON3 MACON4\n");
|
||||
printf("%02x %02x %02x\n",
|
||||
macon1,macon3,macon4);
|
||||
printf("MAADR\n");
|
||||
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
(int)readRegByte(MAADR5),
|
||||
(int)readRegByte(MAADR4),
|
||||
(int)readRegByte(MAADR3),
|
||||
(int)readRegByte(MAADR2),
|
||||
(int)readRegByte(MAADR1),
|
||||
(int)readRegByte(MAADR0) );
|
||||
|
||||
val = readRegByte(EIR);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Contributed by Alex M. Based on code from: http://blog.derouineau.fr */
|
||||
/* /2011/07/putting-enc28j60-ethernet-controler-in-sleep-mode/ */
|
||||
void enc28j60_power_down( void )
|
||||
{
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
|
||||
while(readRegByte(ESTAT) & ESTAT_RXBUSY);
|
||||
while(readRegByte(ECON1) & ECON1_TXRTS);
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
|
||||
}
|
||||
|
||||
void enc28j60_power_up( void )
|
||||
{
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
|
||||
while(!readRegByte(ESTAT) & ESTAT_CLKRDY);
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
||||
}
|
||||
|
||||
uint8_t enc28j60_do_BIST ( void )
|
||||
{
|
||||
#define RANDOM_FILL 0b0000
|
||||
#define ADDRESS_FILL 0b0100
|
||||
#define PATTERN_SHIFT 0b1000
|
||||
#define RANDOM_RACE 0b1100
|
||||
|
||||
/* init */
|
||||
spi_disable_eth();
|
||||
|
||||
writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
|
||||
_delay_ms(2); /* errata B7/2 */
|
||||
while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY) ;
|
||||
|
||||
/* now we can start the memory test */
|
||||
uint16_t macResult;
|
||||
uint16_t bitsResult;
|
||||
|
||||
/* clear some of the registers registers */
|
||||
writeRegByte(ECON1, 0);
|
||||
writeReg(EDMAST, 0);
|
||||
|
||||
/* Set up necessary pointers for the DMA to calculate over the entire memory */
|
||||
writeReg(EDMAND, 0x1FFFu);
|
||||
writeReg(ERXND, 0x1FFFu);
|
||||
|
||||
/* Enable Test Mode and do an Address Fill */
|
||||
SetBank(EBSTCON);
|
||||
writeRegByte(EBSTCON, EBSTCON_TME | EBSTCON_BISTST | ADDRESS_FILL);
|
||||
|
||||
/* wait for BISTST to be reset, only after that are we actually ready to */
|
||||
/* start the test */
|
||||
/* this was undocumented :( */
|
||||
while (readOp(ENC28J60_READ_CTRL_REG, EBSTCON) & EBSTCON_BISTST);
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
|
||||
|
||||
/* now start the actual reading an calculating the checksum until the end is */
|
||||
/* reached */
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST | ECON1_CSUMEN);
|
||||
SetBank(EDMACS);
|
||||
while(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST);
|
||||
macResult = readReg(EDMACS);
|
||||
bitsResult = readReg(EBSTCS);
|
||||
/* Compare the results */
|
||||
/* 0xF807 should always be generated in Address fill mode */
|
||||
if ((macResult != bitsResult) || (bitsResult != 0xF807)) {
|
||||
return 0;
|
||||
}
|
||||
/* reset test flag */
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
|
||||
|
||||
|
||||
/* Now start the BIST with random data test, and also keep on swapping the */
|
||||
/* DMA/BIST memory ports. */
|
||||
writeRegByte(EBSTSD, 0b10101010 /* | millis()*/);
|
||||
writeRegByte(EBSTCON, EBSTCON_TME | EBSTCON_PSEL | EBSTCON_BISTST | RANDOM_FILL);
|
||||
|
||||
|
||||
/* wait for BISTST to be reset, only after that are we actually ready to */
|
||||
/* start the test */
|
||||
/* this was undocumented :( */
|
||||
while (readOp(ENC28J60_READ_CTRL_REG, EBSTCON) & EBSTCON_BISTST);
|
||||
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
|
||||
|
||||
|
||||
/* now start the actual reading an calculating the checksum until the end is */
|
||||
/* reached */
|
||||
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST | ECON1_CSUMEN);
|
||||
SetBank(EDMACS);
|
||||
while(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST);
|
||||
|
||||
macResult = readReg(EDMACS);
|
||||
bitsResult = readReg(EBSTCS);
|
||||
/* The checksum should be equal */
|
||||
return macResult == bitsResult;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user