Dominick.Vansevenant/Zorro-LAN-IDE
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Working! Use "fit.bat 54 35"

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MHeinrichs
2019-01-02 11:11:42 +01:00
parent 1ec3fe8e97
commit ace45ad182
30 changed files with 13044 additions and 11639 deletions
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Logic/LAN_IDE/LAN_IDE_CP.syr
+40 -49
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.14 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.14 secs
--> Reading design: LAN_IDE_CP.prj
@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Encoding Algorithm : Gray
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -71,6 +71,8 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : Gray
=========================================================================
* HDL Compilation *
@@ -126,7 +128,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | automatic |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
@@ -140,7 +142,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | automatic |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16x8-bit ROM for signal <D_OUT$mux0004>.
@@ -173,7 +175,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <AUTOCONFIG_ACCESS>.
Found 1-bit register for signal <CONFIG_READY>.
Found 8-bit register for signal <D_OUT>.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 533.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 518.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 249.
@@ -188,7 +190,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 367.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 360.
Found 1-bit register for signal <LAN_SM_RST>.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
@@ -231,7 +233,6 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
------------------------
State | Encoding
@@ -245,25 +246,24 @@ Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
set_commit | 101
done | 100
------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:12]> with one-hot encoding.
-----------------------------------
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with gray encoding.
-------------------------------
State | Encoding
-----------------------------------
nop | 000000000001
-------------------------------
nop | 0000
start_read_upper | unreached
wait_read_upper | 000000000010
end_read_upper | 000000100000
start_read_lower | 000001000000
wait_read_lower | 000000000100
end_read_lower | 000010000000
start_write_upper | 000000001000
wait_write_upper | 000100000000
end_write_upper | 001000000000
start_write_lower | 000000010000
wait_write_lower | 010000000000
end_write_lower | 100000000000
-----------------------------------
wait_read_upper | 0001
end_read_upper | 0111
start_read_lower | 0101
wait_read_lower | 0011
end_read_lower | 0100
start_write_upper | 0010
wait_write_upper | 1100
end_write_upper | 1101
start_write_lower | 0110
wait_write_lower | 1111
end_write_lower | 1110
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <11>. This FF/Latch will be trimmed during the optimization process.
@@ -330,7 +330,6 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : LAN_SM_FSM_FFd12
implementation constraint: INIT=s : D_OUT_7
implementation constraint: INIT=s : D_OUT_6
implementation constraint: INIT=s : D_OUT_5
@@ -350,13 +349,6 @@ Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_SM_FSM_FFd5
implementation constraint: INIT=r : LAN_SM_FSM_FFd6
implementation constraint: INIT=r : LAN_SM_FSM_FFd7
implementation constraint: INIT=r : LAN_SM_FSM_FFd8
implementation constraint: INIT=r : LAN_SM_FSM_FFd9
implementation constraint: INIT=r : LAN_SM_FSM_FFd10
implementation constraint: INIT=r : LAN_SM_FSM_FFd11
=========================================================================
* Partition Report *
@@ -388,24 +380,23 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 759
# AND2 : 249
# AND3 : 28
# AND4 : 5
# BELS : 1038
# AND2 : 344
# AND3 : 50
# AND4 : 7
# AND8 : 4
# GND : 1
# INV : 220
# OR2 : 190
# OR3 : 25
# OR4 : 3
# OR8 : 16
# INV : 382
# OR2 : 205
# OR3 : 10
# OR4 : 17
# VCC : 1
# XOR2 : 17
# FlipFlops/Latches : 123
# FlipFlops/Latches : 115
# FD : 1
# FDC : 24
# FDCE : 4
# FDP : 44
# FDC : 19
# FDCE : 3
# FDP : 42
# FDPE : 50
# IO Buffers : 109
# IBUF : 19
@@ -415,12 +406,12 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.22 secs
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.42 secs
-->
Total memory usage is 4534788 kilobytes
Total memory usage is 4534740 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 51 ( 0 filtered)