Reset in hardware and clock set to 33mhz

2017-01-26 22:03:20 +01:00
parent 69ed2e6ebd
commit 9d64477682
63 changed files with 18866 additions and 17920 deletions
@@ -8,5 +8,8 @@
 <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->

 <messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd&quot; into library work</arg>
+</msg>
+
 </messages>