Reset in hardware and clock set to 33mhz
This commit is contained in:
MHeinrichs
@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.11 secs
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Total CPU time to Xst completion: 0.10 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.11 secs
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Total CPU time to Xst completion: 0.10 secs
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--> Reading design: LAN_IDE_CP.prj
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@@ -104,54 +104,73 @@ Synthesizing Unit <LAN_IDE_CP>.
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WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1306 - Output <MTACK> is never assigned.
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WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst - You have specified state <nop> as a recovery-only state for the safe implementation of FSM <LAN_RST_SM>. Due to a limitation in this version of the software, the logic required to implement this recovery-only state might not be properly generated. Please refer to the Xilinx Answers Database for more details.
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Found finite state machine <FSM_0> for signal <LAN_RST_SM>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 8 |
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| Inputs | 0 |
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| Outputs | 8 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (positive) |
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| Reset type | synchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Recovery State | nop |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 16-bit tristate buffer for signal <D>.
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Found 16-bit tristate buffer for signal <DQ>.
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Found 1-bit tristate buffer for signal <OWN>.
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Found 1-bit tristate buffer for signal <CFOUT>.
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Found 1-bit tristate buffer for signal <OVR>.
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Found 1-bit tristate buffer for signal <MTACK>.
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Found 1-bit tristate buffer for signal <DTACK>.
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Found 1-bit tristate buffer for signal <INT_OUT>.
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Found 4-bit tristate buffer for signal <LAN_CFG>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 120.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 139.
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Found 2-bit register for signal <AUTO_CONFIG_DONE>.
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Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 253.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 319.
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Found 1-bit register for signal <autoconfig>.
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Found 1-bit register for signal <cp>.
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Found 8-bit comparator equal for signal <cp$cmp_eq0001> created at line 137.
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Found 8-bit comparator equal for signal <cp$cmp_eq0002> created at line 142.
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Found 2-bit comparator less for signal <cp$cmp_lt0000> created at line 133.
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Found 8-bit comparator equal for signal <cp$cmp_eq0001> created at line 203.
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Found 8-bit comparator equal for signal <cp$cmp_eq0002> created at line 208.
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Found 2-bit comparator less for signal <cp$cmp_lt0000> created at line 199.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <Dout1>.
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Found 3-bit comparator less for signal <Dout1$cmp_lt0000> created at line 255.
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Found 3-bit comparator less for signal <Dout1$cmp_lt0000> created at line 321.
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Found 1-bit register for signal <DS_D>.
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Found 1-bit register for signal <ide>.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 147.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 213.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 1-bit register for signal <lan_adr>.
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Found 8-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 3-bit register for signal <SHUT_UP>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 6 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 5 Comparator(s).
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inferred 1 Xor(s).
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inferred 40 Tristate(s).
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inferred 42 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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@@ -161,8 +180,8 @@ HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 24
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1-bit register : 18
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# Registers : 26
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1-bit register : 20
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2-bit register : 2
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4-bit register : 1
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8-bit register : 3
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@@ -170,8 +189,8 @@ Macro Statistics
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2-bit comparator less : 1
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3-bit comparator less : 1
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8-bit comparator equal : 3
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# Tristates : 10
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1-bit tristate buffer : 8
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# Tristates : 12
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1-bit tristate buffer : 10
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16-bit tristate buffer : 2
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# Xors : 1
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1-bit xor2 : 1
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@@ -182,11 +201,26 @@ Macro Statistics
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
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------------------------
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State | Encoding
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------------------------
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nop | 000
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wait0 | 001
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clr | 011
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clr_commit | 010
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wait1 | 110
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set | 111
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set_commit | 101
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done | 100
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------------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 1
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 6
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@@ -201,6 +235,9 @@ Macro Statistics
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=========================================================================
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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=========================================================================
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* Partition Report *
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@@ -232,36 +269,36 @@ Design Statistics
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# IOs : 116
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Cell Usage :
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# BELS : 438
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# AND2 : 102
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# AND3 : 12
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# BELS : 552
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# AND2 : 156
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# AND3 : 13
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# AND4 : 1
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# GND : 1
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# INV : 165
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# OR2 : 125
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# OR3 : 4
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# INV : 203
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# OR2 : 130
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# OR3 : 20
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# OR4 : 2
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# XOR2 : 26
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# FlipFlops/Latches : 50
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# FD : 9
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# FlipFlops/Latches : 55
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# FD : 14
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# FDC : 4
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# FDCE : 37
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# IO Buffers : 109
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# IBUF : 36
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# IO Buffers : 111
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# IBUF : 37
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# IOBUFE : 32
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# OBUF : 33
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# OBUFE : 8
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# OBUF : 32
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# OBUFE : 10
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=========================================================================
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Total REAL time to Xst completion: 8.00 secs
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Total CPU time to Xst completion: 7.90 secs
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Total CPU time to Xst completion: 8.01 secs
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-->
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Total memory usage is 293732 kilobytes
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Total memory usage is 306240 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 9 ( 0 filtered)
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Number of warnings : 8 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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