Switched Driver to baxnet-structure
This commit is contained in:
MHeinrichs
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/*
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enc28j60l.h
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author: Henryk Richter <henryk.richter@gmx.net>
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purpose: header for low-level register and SPI access
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to ENC28J60 networking device
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*/
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#ifndef _INC_ENC28J60L_H
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#define _INC_ENC28J60L_H
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#include "compiler.h"
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/*
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Purpose: prepare SPI for use
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input: -
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output: success/failure
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>0 - all fine, ready to work
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<=0 - init problem (codes undefined yet)
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*/
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ASM SAVEDS int enc28j60l_Init( void );
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/*
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Purpose: shutdown SPI
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input: -
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output: -
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*/
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ASM SAVEDS void enc28j60l_Shutdown( void );
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/*
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Purpose: delay at least the given amount of microseconds
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input: delay time in microseconds
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output: -
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*/
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ASM SAVEDS void enc28j60l_UMinDelay(
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ASMR(d0) unsigned long udelay ASMREG(d0) );
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/*
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Purpose: set SPI clock divider
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input: clock divider 1...n
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output: -
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*/
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ASM SAVEDS void enc28j60l_SetSPISpeed(
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ASMR(d0) unsigned long divider ASMREG(d0) );
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/*
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purpose: read one byte from a custom register
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input: op = ENC28J60_READ_CTRL_REG
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address = register address, including bits denoting the bank
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data = data byte
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*/
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ASM SAVEDS unsigned char enc28j60l_ReadOp(
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ASMR(d3) unsigned char op ASMREG(d3),
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ASMR(d0) unsigned char address ASMREG(d0) );
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/*
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purpose: write one byte to a custom register
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input: op = ENC28J60_WRITE_CTRL_REG,
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ENC28J60_BIT_FIELD_SET,
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ENC28J60_BIT_FIELD_CLR
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address = register address, including bits denoting the bank
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data = data byte
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*/
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ASM void enc28j60l_WriteOp( ASMR(d3) unsigned char op ASMREG(d3),
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ASMR(d0) unsigned char address ASMREG(d0),
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ASMR(d1) unsigned char data ASMREG(d1));
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/*
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purpose: select register bank based on given address
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input:
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address = register address, including bits denoting the bank
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*/
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ASM SAVEDS void enc28j60l_SetBank( ASMR(d0) unsigned char address ASMREG(d0) );
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/*
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purpose: read one short from a custom register
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input: address = register address, including bits denoting the bank
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data = data word (unsigned short)
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*/
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ASM SAVEDS unsigned short enc28j60l_ReadReg( ASMR(d0) unsigned char address ASMREG(d0) );
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/*
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purpose: write one short to a custom register
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input: address = register address, including bits denoting the bank
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data = data word (unsigned short)
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*/
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ASM void enc28j60l_WriteReg( ASMR(d0) unsigned char address ASMREG(d0),
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ASMR(d1) unsigned short data ASMREG(d1));
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/*
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purpose: read one byte from a custom register
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input: address = register address, including bits denoting the bank
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*/
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ASM SAVEDS unsigned char enc28j60l_ReadRegByte(
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ASMR(d0) unsigned char address ASMREG(d0));
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/*
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purpose: write one byte to a custom register
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input: address = register address, including bits denoting the bank
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data = data word (unsigned short)
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*/
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ASM void enc28j60l_WriteRegByte( ASMR(d0) unsigned char address ASMREG(d0),
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ASMR(d1) unsigned char data ASMREG(d1));
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/*
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purpose: Read buffer from device to computer
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input: buffer = buffer to read into
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size = length of buffer
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*/
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ASM void enc28j60l_ReadBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1),
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ASMR(d0) unsigned int size ASMREG(d0));
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/*
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purpose: Write buffer from computer to device
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input: buffer = buffer to write
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size = length of buffer
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destptr = destination pointer in device
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*/
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ASM void enc28j60l_WriteBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1),
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ASMR(d0) unsigned int size ASMREG(d0),
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ASMR(d1) unsigned short destptr ASMREG(d1));
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/*
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Definitions based on the enc28j60.c file from the AVRlib library by Pascal Stang.
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ENC28J60 Control Registers
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Control register definitions are a combination of address,
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bank number, and Ethernet/MAC/PHY indicator bits.
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- Register address (bits 0-4)
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- Bank number (bits 5-6)
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- MAC/PHY indicator (bit 7)
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*/
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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/* All-bank registers */
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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/* Bank 0 registers */
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#define ERDPT (0x00|0x00)
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#define EWRPT (0x02|0x00)
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#define ETXST (0x04|0x00)
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#define ETXND (0x06|0x00)
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#define ERXST (0x08|0x00)
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#define ERXND (0x0A|0x00)
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#define ERXRDPT (0x0C|0x00)
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#define ERXWRPT (0x0E|0x00)
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#define EDMAST (0x10|0x00)
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#define EDMAND (0x12|0x00)
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/* #define EDMADST (0x14|0x00) */
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#define EDMACS (0x16|0x00)
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/* Bank 1 registers */
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCS (0x10|0x20)
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/* #define EPMO (0x14|0x20) */
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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/* Bank 2 registers */
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#define MACON1 (0x00|0x40|0x80)
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#define MACON2 (0x01|0x40|0x80)
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#define MACON3 (0x02|0x40|0x80)
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#define MACON4 (0x03|0x40|0x80)
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#define MABBIPG (0x04|0x40|0x80)
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#define MAIPG (0x06|0x40|0x80)
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#define MACLCON1 (0x08|0x40|0x80)
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#define MACLCON2 (0x09|0x40|0x80)
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#define MAMXFL (0x0A|0x40|0x80)
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#define MAPHSUP (0x0D|0x40|0x80)
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#define MICON (0x11|0x40|0x80)
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#define MICMD (0x12|0x40|0x80)
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#define MIREGADR (0x14|0x40|0x80)
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#define MIWR (0x16|0x40|0x80)
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#define MIRD (0x18|0x40|0x80)
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/* Bank 3 registers */
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#define MAADR1 (0x00|0x60|0x80)
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#define MAADR0 (0x01|0x60|0x80)
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#define MAADR3 (0x02|0x60|0x80)
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#define MAADR2 (0x03|0x60|0x80)
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#define MAADR5 (0x04|0x60|0x80)
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#define MAADR4 (0x05|0x60|0x80)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCS (0x08|0x60)
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#define MISTAT (0x0A|0x60|0x80)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUS (0x18|0x60)
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/* ENC28J60 ERXFCON Register Bit Definitions */
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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/* ENC28J60 EIE Register Bit Definitions */
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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#define EIE_WOLIE 0x04
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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/* ENC28J60 EIR Register Bit Definitions */
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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#define EIR_WOLIF 0x04
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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/* ENC28J60 ESTAT Register Bit Definitions */
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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/* ENC28J60 ECON2 Register Bit Definitions */
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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/* ENC28J60 ECON1 Register Bit Definitions */
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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/* ENC28J60 MACON1 Register Bit Definitions */
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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/* ENC28J60 MACON2 Register Bit Definitions */
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#define MACON2_MARST 0x80
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#define MACON2_RNDRST 0x40
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#define MACON2_MARXRST 0x08
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#define MACON2_RFUNRST 0x04
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#define MACON2_MATXRST 0x02
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#define MACON2_TFUNRST 0x01
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/* ENC28J60 MACON3 Register Bit Definitions */
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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/* ENC28J60 MICMD Register Bit Definitions */
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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/* ENC28J60 MISTAT Register Bit Definitions */
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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/* ENC28J60 EBSTCON Register Bit Definitions */
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#define EBSTCON_PSV2 0x80
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#define EBSTCON_PSV1 0x40
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#define EBSTCON_PSV0 0x20
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#define EBSTCON_PSEL 0x10
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#define EBSTCON_TMSEL1 0x08
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#define EBSTCON_TMSEL0 0x04
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#define EBSTCON_TME 0x02
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#define EBSTCON_BISTST 0x01
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/* PHY registers */
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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/* ENC28J60 PHY PHCON1 Register Bit Definitions */
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
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#define PHSTAT1_JBSTAT 0x0002
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/* ENC28J60 PHY PHCON2 Register Bit Definitions */
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#define PHCON2_FRCLINK 0x4000
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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/* PHIE Register */
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#define PHIE_PGEIE (1<<1)
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#define PHIE_LNKIE (1<<4)
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/* ENC28J60 Packet Control Byte Bit Definitions */
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#define PKTCTRL_PHUGEEN 0x08
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#define PKTCTRL_PPADEN 0x04
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#define PKTCTRL_PCRCEN 0x02
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#define PKTCTRL_POVERRIDE 0x01
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/* SPI operation codes */
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#define ENC28J60_READ_CTRL_REG 0x00
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#define ENC28J60_READ_BUF_MEM 0x3A
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#define ENC28J60_WRITE_CTRL_REG 0x40
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#define ENC28J60_WRITE_BUF_MEM 0x7A
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#define ENC28J60_BIT_FIELD_SET 0x80
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#define ENC28J60_BIT_FIELD_CLR 0xA0
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#define ENC28J60_SOFT_RESET 0xFF
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#endif /* _INC_ENC28J60L_H */
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