Dominick.Vansevenant/Zorro-LAN-IDE
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fully clocked z3-statemachine for lan without reset-hack

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This commit is contained in:
MHeinrichs
2019-02-27 23:06:45 +01:00
parent 8230e4fca2
commit 95630fdcf7
34 changed files with 24894 additions and 28495 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE/LAN_IDE.gise
+6 -3
View File
@@ -65,7 +65,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551017609" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="8912034895357830792" xil_pn:start_ts="1551017597">
<transform xil_pn:end_ts="1551216000" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5899415373064323687" xil_pn:start_ts="1551215987">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -86,7 +86,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551017872" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551017865">
<transform xil_pn:end_ts="1551216008" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551216000">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
@@ -95,13 +95,16 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1551017937" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551017872">
<transform xil_pn:end_ts="1551216058" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551216008">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
<outfile xil_pn:name="LAN_IDE_CP.tim"/>
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
<outfile xil_pn:name="LAN_IDE_CP.xml"/>
<outfile xil_pn:name="LAN_IDE_CP_html"/>
</transform>
<transform xil_pn:end_ts="1550787397" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1550787395">
Logic/LAN_IDE/LAN_IDE.xise
+6 -6
View File
@@ -41,7 +41,7 @@
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="Full" xil_pn:valueState="non-default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Johnson" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Sequential" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -97,7 +97,7 @@
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -111,8 +111,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -155,7 +155,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE/LAN_IDE_CP.bld
+1 -1
View File
@@ -29,7 +29,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 4418684 kilobytes
Total memory usage is 4418680 kilobytes
Writing NGD file "LAN_IDE_CP.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Logic/LAN_IDE/LAN_IDE_CP.cmd_log
+38
View File
@@ -234,3 +234,41 @@ xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/L
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE/LAN_IDE_CP.gyd
+79 -81
View File
@@ -10,7 +10,6 @@ A<4> S:PIN50
A<5> S:PIN49
A<6> S:PIN51
A<7> S:PIN53
BERR S:PIN98
C1 S:PIN103
C3 S:PIN102
CFIN S:PIN104
@@ -121,84 +120,83 @@ DQ<4> S:PIN124
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 SHUT_UP_Z2<1> LAN_BASEADR<8> D_9_IOBUFE/D_9_IOBUFE_TRST LAN_BASEADR<3>
D_5_IOBUFE D_4_IOBUFE LAN_BASEADR<2> IDE_CS_0_OBUF
LAN_BASEADR<12> IDE_CS_1_OBUF LAN_BASEADR<11> IDE_A_0_OBUF$BUF0
LAN_BASEADR<10> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 LAN_BASEADR<0>
IDE_R_OBUF CP_BASEADR<3>
PARTITION FB2_1 DQ<8>_BUFR.MC A_LAN_4_OBUF A_LAN_7_OBUF IDE_BASEADR<3>
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<2> ROM_B_0_OBUF$BUF5
IDE_BASEADR<1> D_6_IOBUFE EXP24_ D_3_IOBUFE
IDE_BASEADR<0> D_7_IOBUFE D_1_IOBUFE DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
D_8_IOBUFE EXP25_
PARTITION FB3_1 $OpTx$INV$438 IDE_W_OBUF SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF CP_WE_QUIRK
$OpTx$FX_DC$463 $OpTx$FX_DC$462 $OpTx$FX_DC$461 Z3_ADR<8>
Z3_ADR<7> Z3_ADR<6> Z3_ADR<5> Z3_ADR<4>
Z3_ADR<3> ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 Z3_ADR<2>
Z3_ADR<13> $OpTx$$OpTx$FX_DC$476_INV$1624
PARTITION FB4_1 SHUT_UP_Z2<2> D_0_IOBUFE IDE_BASEADR<7> IDE_BASEADR<6>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<5> A_LAN_3_OBUF
IDE_BASEADR<4> CP_BASEADR<7> CP_BASEADR<6> A_LAN_2_OBUF
CP_BASEADR<5> A_LAN_5_OBUF CP_BASEADR<4> CP_BASEADR<2>
CP_BASEADR<1> CP_BASEADR<0>
PARTITION FB5_1 EXP26_ CP_CS_OBUF EXP27_ EXP28_
ROM_OE_OBUF $OpTx$INV$436 EXP29_ EXP30_
EXP31_ D_2_IOBUFE EXP32_ D_9_IOBUFE
EXP33_ D_10_IOBUFE D_11_IOBUFE EXP34_
D_12_IOBUFE AUTOCONFIG_Z2_ACCESS
PARTITION FB6_1 LAN_RST_SM_FSM_FFd3 ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF LAN_RST_SM_FSM_FFd2
A_LAN_13_OBUF A_LAN_10_OBUF LAN_IRQ_D0 A_LAN_11_OBUF
Z3_ADR<10> A_LAN_8_OBUF LAN_IRQ_OUT IDE_W_S
IDE_ACCESS A_LAN_9_OBUF AUTO_CONFIG_Z2_DONE<2> AUTO_CONFIG_Z2_DONE<1>
AUTO_CONFIG_Z2_DONE<0> $OpTx$INV$437
PARTITION FB7_1 LAN_BASEADR<9> EXP35_ D_13_IOBUFE LAN_BASEADR<7>
D_14_IOBUFE EXP36_ EXP37_ LAN_BASEADR<5>
LAN_BASEADR<4> LAN_BASEADR<1> EXP38_ D_15_IOBUFE
EXP39_ LAN_BASEADR<6> LAN_BASEADR<15> LAN_BASEADR<14>
LAN_BASEADR<13> AUTO_CONFIG_Z2_DONE_CYCLE<2>
PARTITION FB8_1 DQ_DATA<0> DQ_12_IOBUFE DQ_14_IOBUFE EXP40_
LAN_WRH_OBUF EXP41_ DQ_DATA<12> LAN_CS_OBUF
DQ_DATA<14> LAN_RD_OBUF EXP42_ DQ_DATA<4>
EXP43_ DQ_DATA<6> EXP44_ DQ_DATA<8>
LAN_SM_FSM_FFd8 EXP45_
PARTITION FB9_1 EXP46_ LAN_ACCESS LAN_SM_FSM_FFd13 LAN_SM_FSM_FFd2
Z3_ADR<12> Z3_ADR<11> LAN_WRL_S LAN_WRH_S
LAN_SM_FSM_FFd7 LAN_SM_FSM_FFd6 Z3_DATA<0> LAN_SM_FSM_FFd3
IDE_ENABLE Z3_DATA<1> DQ_SWAP LAN_SM_FSM_FFd4
Z3_DATA<2> LAN_SM_FSM_FFd1
PARTITION FB10_1 DQ<4>_BUFR.MC DQ_1_IOBUFE DQ_0_IOBUFE EXP47_
DQ_3_IOBUFE DQ_2_IOBUFE EXP48_ DQ_5_IOBUFE
EXP49_ _19_ DQ_7_IOBUFE DQ_6_IOBUFE
EXP50_ _18_ EXP51_ EXP52_
DQ_10_IOBUFE EXP53_
PARTITION FB11_1 $OpTx$FX_DC$1323 Z3_DATA<30> Z3_DATA<3> Z3_DATA<29>
Z3_DATA<4> Z3_DATA<28> Z3_DATA<27> Z3_DATA<22>
Z3_DATA<21> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
Z3_DATA<20> ROM_B_0_OBUF Z3_DATA<19> LAN_READY
CP_WE_OBUF Z3_A_LOW
PARTITION FB12_1 DQ_DATA<11> ROM_B_0_OBUF$BUF4 Z3_DATA<9>/Z3_DATA<9>_SETF__$INT LAN_SM_FSM_FFd10
DQ_15_IOBUFE LAN_INT_ENABLE EXP54_ DQ_13_IOBUFE
EXP55_ DQ_11_IOBUFE EXP56_ DQ_9_IOBUFE
EXP57_ DQ_DATA<7> EXP58_ DQ_DATA<3>
EXP59_ DQ_DATA<15>
PARTITION FB13_1 SHUT_UP_Z2<0> CP_RD_OBUF AUTO_CONFIG_Z2_DONE_CYCLE<1> AUTO_CONFIG_Z2_DONE_CYCLE<0>
EXP60_ EXP61_ D_Z2_OUT<3> Z3_DATA<7>
EXP62_ D_Z2_OUT<2> EXP63_ EXP64_
D_Z2_OUT<0> LAN_WRL_OBUF EXP65_ EXP66_
D_Z2_OUT<1> EXP67_
PARTITION FB14_1 LAN_A_INIT<3> LAN_WR_RST ROM_B_0_OBUF$BUF2 LAN_RST_SM_FSM_FFd7
LAN_RST_SM_FSM_FFd6 LAN_RST_SM_FSM_FFd5 LAN_RST_SM_FSM_FFd4 LAN_RST_SM_FSM_FFd1
LAN_D_INIT<8> LAN_D_INIT<1> CFOUT_OBUF LAN_CS_RST
LAN_A_INIT<6> SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR_1
Z3_ADR_0 Z3_ADR<9>
PARTITION FB15_1 DQ_DATA<1> LAN_SM_FSM_FFd5 DQ_DATA<13> ROM_OE_S
LAN_SM_FSM_FFd11 IDE_R_S CP_WE_S CP_RD_S
LAN_RD_S DQ_DATA<9> LAN_SM_FSM_FFd9 ROM_B_0_OBUF$BUF10
DQ_DATA<5> Z3_DATA<15> Z3_DATA<14> LAN_SM_FSM_FFd12
Z3_DATA<13> EXP68_
PARTITION FB16_1 DQ_DATA<10> Z3_DATA<12> Z3_DATA<11> EXP69_
DQ_DATA<2> Z3_DATA<10> Z3_DATA<17> Z3_DATA<9>
Z3_DATA<18> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<23>
Z3_DATA<24> Z3_DATA<25> Z3_DATA<26> Z3_DATA<31>
Z3_DATA<16> EXP70_
PARTITION FB1_1 EXP24_ EXP25_ AUTO_CONFIG_Z2_DONE_CYCLE<2> SHUT_UP_Z2<0>
D_5_IOBUFE D_4_IOBUFE EXP26_ IDE_CS_0_OBUF
LAN_BASEADR<8> IDE_CS_1_OBUF LAN_BASEADR<3> IDE_A_0_OBUF$BUF0
LAN_BASEADR<2> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 D_Z2_OUT<0>
IDE_R_OBUF D_Z2_OUT<2>
PARTITION FB2_1 EXP27_ A_LAN_4_OBUF A_LAN_7_OBUF LAN_RD_S
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 LAN_SM_FSM_FFd4 ROM_B_0_OBUF$BUF5
DQ_5_IOBUFE/DQ_5_IOBUFE_TRST D_6_IOBUFE EXP28_ D_3_IOBUFE
LAN_SM_FSM_FFd3 D_7_IOBUFE D_1_IOBUFE EXP29_
D_8_IOBUFE LAN_SM_FSM_FFd2
PARTITION FB3_1 $OpTx$BIN_STEP$140 IDE_W_OBUF EXP30_
PARTITION FB3_10 LAN_A_INIT<3> SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF LAN_D_INIT<8> LAN_D_INIT<1>
ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 LAN_A_INIT<6> CP_WE_QUIRK
EXP31_
PARTITION FB4_1 IDE_BASEADR<6> D_0_IOBUFE EXP32_ IDE_BASEADR<4>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<3> A_LAN_3_OBUF
IDE_BASEADR<2> IDE_BASEADR<1> IDE_BASEADR<0> A_LAN_2_OBUF
CP_BASEADR<0> A_LAN_5_OBUF EXP33_ D_Z2_OUT<1>
EXP34_ IDE_BASEADR<5>
PARTITION FB5_1 D_8_IOBUFE/D_8_IOBUFE_TRST CP_CS_OBUF SHUT_UP_Z2<2> LAN_BASEADR<10>
ROM_OE_OBUF CP_BASEADR<7> CP_BASEADR<3> CP_BASEADR<2>
EXP35_ D_2_IOBUFE CP_BASEADR<1> D_9_IOBUFE
EXP36_ D_10_IOBUFE D_11_IOBUFE EXP37_
D_12_IOBUFE IDE_BASEADR<7>
PARTITION FB6_1 EXP38_ ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF LAN_RST_SM_FSM_FFd3
A_LAN_13_OBUF A_LAN_10_OBUF LAN_RST_SM_FSM_FFd1 A_LAN_11_OBUF
LAN_IRQ_D0 A_LAN_8_OBUF Z3_ADR_1 Z3_ADR_0
Z3_ADR<9> A_LAN_9_OBUF LAN_WR_RST LAN_IRQ_OUT
EXP39_ LAN_ACCESS
PARTITION FB7_1 Z3_ADR<2> ROM_OE_S D_13_IOBUFE IDE_W_S
D_14_IOBUFE EXP40_ IDE_ENABLE CP_WE_S
CP_RD_S AUTO_CONFIG_Z2_DONE_CYCLE<0> AUTO_CONFIG_Z2_DONE<2> D_15_IOBUFE
IDE_R_S AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0> AUTOCONFIG_Z2_ACCESS
EXP41_ D_Z2_OUT<3>
PARTITION FB8_1 LAN_BASEADR<13> DQ_12_IOBUFE DQ_14_IOBUFE EXP42_
LAN_WRH_OBUF SHUT_UP_Z2<1> AUTO_CONFIG_Z2_DONE_CYCLE<1> LAN_CS_OBUF
LAN_BASEADR<9> LAN_RD_OBUF LAN_BASEADR<5> LAN_BASEADR<4>
LAN_BASEADR<1> LAN_BASEADR<6> EXP43_ LAN_BASEADR<7>
LAN_BASEADR<15> LAN_BASEADR<14>
PARTITION FB9_1 EXP44_ EXP45_ DQ_DATA<7> EXP46_
EXP47_ DQ_DATA<6> EXP48_ DQ_DATA<1>
EXP49_ DQ_DATA<15> Z3_DATA<0> EXP50_
EXP51_ Z3_DATA<1> DQ_DATA<14> EXP52_
Z3_DATA<2> LAN_INT_ENABLE
PARTITION FB10_1 DQ<4>_BUFR.MC DQ_1_IOBUFE DQ_0_IOBUFE EXP53_
DQ_3_IOBUFE DQ_2_IOBUFE EXP54_ DQ_5_IOBUFE
EXP55_ _19_ DQ_7_IOBUFE DQ_6_IOBUFE
EXP56_ _18_ EXP57_ EXP58_
DQ_10_IOBUFE EXP59_
PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<28>
Z3_DATA<4> Z3_DATA<27> Z3_DATA<22> Z3_DATA<21>
Z3_DATA<20> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
Z3_DATA<19> ROM_B_0_OBUF EXP60_ DQ_DATA<8>
CP_WE_OBUF DQ_DATA<0>
PARTITION FB12_1 LAN_BASEADR<11> ROM_B_0_OBUF$BUF4 LAN_BASEADR<0> EXP61_
DQ_15_IOBUFE CP_BASEADR<5> EXP62_ DQ_13_IOBUFE
EXP63_ DQ_11_IOBUFE EXP64_ DQ_9_IOBUFE
LAN_BASEADR<12> CP_BASEADR<4> DQ<8>_BUFR.MC EXP65_
EXP66_ CP_BASEADR<6>
PARTITION FB13_1 Z3_ADR<12> CP_RD_OBUF LAN_CS_RST DQ_DATA<9>
EXP67_ Z3_A_LOW EXP68_ Z3_DATA<7>
Z3_ADR<7> LAN_SM_FSM_FFd1 DQ_SWAP LAN_RST_SM_FSM_FFd2
LAN_WRH_S LAN_WRL_OBUF DQ_DATA<5> LAN_WRL_S
Z3_ADR<11> LAN_READY
PARTITION FB14_1 CP_ACCESS EXP69_ ROM_B_0_OBUF$BUF2
PARTITION FB14_6 Z3_ADR<8> Z3_ADR<6> Z3_ADR<5> Z3_ADR<4>
Z3_ADR<3> CFOUT_OBUF EXP70_ IDE_ACCESS
SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR<13> Z3_ADR<10>
EXP71_
PARTITION FB15_1 DQ_DATA<11> DQ_DATA<4> EXP72_ EXP73_
EXP74_ EXP75_ DQ_DATA<3> DQ_DATA<12>
EXP76_ DQ_DATA<13> EXP77_ ROM_B_0_OBUF$BUF10
Z3_DATA<31> Z3_DATA<15> Z3_DATA<14> Z3_DATA<23>
Z3_DATA<13> EXP78_
PARTITION FB16_1 EXP79_ Z3_DATA<12> Z3_DATA<11>
PARTITION FB16_5 Z3_DATA<26> Z3_DATA<10> Z3_DATA<25> Z3_DATA<9>
Z3_DATA<24> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<18>
Z3_DATA<17> Z3_DATA<16> EXP80_ DQ_DATA<10>
DQ_DATA<2> EXP81_
Logic/LAN_IDE/LAN_IDE_CP.jed
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Logic/LAN_IDE/LAN_IDE_CP.mfd
+4411 -3855
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Logic/LAN_IDE/LAN_IDE_CP.nga
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngc
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngd
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngr
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.pad
+1 -1
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-24-2019 3:25PM
2-27-2019 11:02PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
Logic/LAN_IDE/LAN_IDE_CP.pnx
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.rpt
+2561 -3153
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Logic/LAN_IDE/LAN_IDE_CP.syr
+84 -96
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@@ -43,9 +43,8 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Johnson
FSM Encoding Algorithm : Sequential
Safe Implementation : No
CASE Implementation Style : Full
Mux Extraction : Yes
Resource Sharing : YES
@@ -72,14 +71,15 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : JOHN
Setting FSM Encoding Algorithm to : SEQ
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
Architecture behavioral of Entity lan_ide_cp is up to date.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
@@ -110,25 +110,21 @@ INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP>
Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <LAN_SM_RST> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LAN_IRQ_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LAN_IRQ_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CP_WE_QUIRK> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
| States | 15 |
| Transitions | 29 |
| Inputs | 9 |
| Outputs | 16 |
| States | 13 |
| Transitions | 22 |
| Inputs | 7 |
| Outputs | 14 |
| Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) |
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | johnson |
| Encoding | sequential |
| Implementation | automatic |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
@@ -142,7 +138,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | johnson |
| Encoding | sequential |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -170,37 +166,39 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 180.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CP_ACCESS>.
Found 16-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 276.
Found 16-bit register for signal <CP_BASEADR>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 289.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 4-bit up counter for signal <CP_WAIT>.
Found 1-bit register for signal <CP_WE_QUIRK>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 264.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 256.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 303.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 296.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 263.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 265.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
Found 1-bit register for signal <LAN_IRQ_D0>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 489.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 494.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 383.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 387.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
@@ -211,8 +209,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 32-bit register for signal <Z3_DATA>.
Summary:
inferred 2 Finite State Machine(s).
inferred 1 Counter(s).
inferred 89 D-type flip-flop(s).
inferred 74 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
inferred 58 Tristate(s).
@@ -223,20 +220,18 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Counters : 1
4-bit up counter : 1
# Registers : 96
1-bit register : 89
# Registers : 84
1-bit register : 76
14-bit register : 2
16-bit register : 2
3-bit register : 1
4-bit register : 1
8-bit register : 1
8-bit register : 2
# Comparators : 6
16-bit comparator equal : 2
16-bit comparator equal : 1
2-bit comparator less : 2
4-bit comparator less : 1
8-bit comparator equal : 1
8-bit comparator equal : 2
# Tristates : 28
1-bit tristate buffer : 26
16-bit tristate buffer : 2
@@ -249,39 +244,37 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:4]> with johnson encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with sequential encoding.
------------------------
State | Encoding
------------------------
nop | 0000
wait0 | 0001
clr | 0011
clr_commit | 0111
wait1 | 1111
set | 1110
set_commit | 1100
done | 1000
nop | 000
wait0 | 001
clr | 010
clr_commit | 011
wait1 | 100
set | 101
set_commit | 110
done | 111
------------------------
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:8]> with johnson encoding.
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with sequential encoding.
-------------------------------
State | Encoding
-------------------------------
nop | 00000000
nop | 0000
start_read_upper | unreached
wait_read_upper | 00000011
end_read_upper | 11111111
start_read_lower | 11111100
wait_read_lower | 00000111
end_read_lower | 11111000
start_write_upper | 00001111
wait_write_upper | 11110000
end_write_upper | 11100000
start_write_lower | 00011111
wait_write_lower | 11000000
wait_cycle_end | 11111110
config_rw | 00000001
cp_read | 00111111
cp_write_wait | 01111111
wait_read_upper | 0010
end_read_upper | 0110
start_read_lower | 1000
wait_read_lower | 0011
end_read_lower | 1001
start_write_upper | 0100
wait_write_upper | 1010
end_write_upper | 1011
start_write_lower | 0101
wait_write_lower | 1100
wait_cycle_end | 0111
config_rw | 0001
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
@@ -311,13 +304,11 @@ Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Counters : 1
4-bit up counter : 1
# Registers : 89
Flip-Flops : 89
# Registers : 74
Flip-Flops : 74
# Comparators : 3
16-bit comparator equal : 2
8-bit comparator equal : 1
16-bit comparator equal : 1
8-bit comparator equal : 2
=========================================================================
@@ -346,36 +337,32 @@ WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 3 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11> <LAN_RST_SM_FSM_FFd4>
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11>
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=s : D_Z2_OUT_2
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=r : LAN_SM_FSM_FFd8
implementation constraint: INIT=r : LAN_SM_FSM_FFd7
implementation constraint: INIT=r : LAN_SM_FSM_FFd6
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=r : LAN_SM_FSM_FFd5
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=s : D_Z2_OUT_2
implementation constraint: INIT=s : D_Z2_OUT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=s : D_Z2_OUT_1
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
@@ -410,23 +397,24 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 2318
# AND2 : 681
# AND3 : 94
# BELS : 1441
# AND2 : 456
# AND3 : 68
# AND4 : 9
# AND5 : 2
# AND8 : 5
# AND5 : 17
# AND8 : 4
# GND : 1
# INV : 894
# OR2 : 412
# OR3 : 149
# OR4 : 26
# XOR2 : 45
# FlipFlops/Latches : 153
# FDC : 29
# INV : 548
# OR2 : 254
# OR3 : 49
# OR4 : 2
# XOR2 : 33
# FlipFlops/Latches : 140
# FD : 3
# FDC : 20
# FDCE : 7
# FDP : 73
# FDPE : 44
# FDP : 41
# FDPE : 69
# IO Buffers : 114
# IBUF : 23
# IOBUFE : 48
@@ -436,13 +424,13 @@ Cell Usage :
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.20 secs
Total CPU time to Xst completion: 8.79 secs
-->
Total memory usage is 4534800 kilobytes
Total memory usage is 4534808 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 51 ( 0 filtered)
Number of warnings : 47 ( 0 filtered)
Number of infos : 10 ( 0 filtered)
Logic/LAN_IDE/LAN_IDE_CP.tspec
+755 -1024
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Logic/LAN_IDE/LAN_IDE_CP.vhd
+202 -195
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@@ -108,9 +108,7 @@ architecture Behavioral of LAN_IDE_CP is
start_write_lower,
wait_write_lower,
wait_cycle_end,
config_rw,
cp_read,
cp_write_wait
config_rw
);
signal LAN_RST_SM: lan_reset :=nop;
@@ -124,7 +122,7 @@ architecture Behavioral of LAN_IDE_CP is
signal ROM_OE_S: STD_LOGIC;
signal CP_ACCESS: STD_LOGIC;
signal CP_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_ACCESS: STD_LOGIC;
signal DQ_SWAP: STD_LOGIC;
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
@@ -150,7 +148,6 @@ architecture Behavioral of LAN_IDE_CP is
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal CP_WAIT:STD_LOGIC_VECTOR(3 downto 0);
signal AMIGA_CLK:STD_LOGIC;
signal DS:STD_LOGIC;
@@ -249,36 +246,27 @@ begin
if(--AS ='0' or
reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
CP_ACCESS <= '0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '0';
end if;
--CP base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
end if;
end process ADDRESS_Z3_DECODE;
@@ -288,7 +276,7 @@ begin
reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
elsif(falling_edge(AS))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
@@ -297,7 +285,12 @@ begin
AUTOCONFIG_Z2_ACCESS <= '0';
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
@@ -309,130 +302,45 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
begin
if reset = '0' then
-- reset active ...
AUTO_CONFIG_Z2_DONE_CYCLE <="000";
D_Z2_OUT<="1111";
SHUT_UP_Z2 <="111";
IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FFFF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
D_Z2_OUT<="1111";
if(AS='1')then
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE;
elsif(AUTOCONFIG_Z2_ACCESS= '1' and DS='0') then
case A(6 downto 1) is
when "000000" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
else
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
when "000001" => D_Z2_OUT <= "0001" ; --one Card, 64KB =001
when "000010" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1000" ; --ProductID high nibble : 7->1000
else
D_Z2_OUT <= "1111" ; --ProductID high nibble : 0->1111
end if;
when "000011" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "0100" ; --ProductID low nibble: B->0100
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0011" ; --ProductID low nibble: C->0011
else
D_Z2_OUT <= "1001" ; --ProductID low nibble: 6->1001
end if;
when "000100" => --er_flags (Z3)
D_Z2_OUT <= "1110" ; -- io device no size extension 64kb subsize
when "000101" => --er_flags (Z3)
D_Z2_OUT <= "1101" ; -- io device no size extension 64kb subsize
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
when "001001" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0101" ; --Ventor ID 1
else
D_Z2_OUT <= "0111" ; --Ventor ID 1
end if;
when "001010" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1110" ; --Ventor ID 2
else
D_Z2_OUT <= "1101" ; --Ventor ID 2
end if;
when "001011" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
else
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $082C: BSC
end if;
when "001100" => D_Z2_OUT <= "0100" ; --Serial byte 0 (msb) high nibble
when "001101" => D_Z2_OUT <= "1110" ; --Serial byte 0 (msb) low nibble
when "001110" => D_Z2_OUT <= "1001" ; --Serial byte 1 high nibble
when "001111" => D_Z2_OUT <= "0100" ; --Serial byte 1 low nibble
when "010000" => D_Z2_OUT <= "1111" ; --Serial byte 2 high nibble
when "010001" => D_Z2_OUT <= "1111" ; --Serial byte 2 low nibble
when "010010" => D_Z2_OUT <= "0100" ; --Serial byte 3 (lsb) high nibble
when "010011" => D_Z2_OUT <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
CP_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(2) <= '0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
end if;
end if;
when "100110" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
end if;
end if;
when others => D_Z2_OUT <= "1111" ;
end case;
--set/deassert the LAN-interrupt bit
if( LAN_INT ='1' --or --no interupt
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
)then
LAN_IRQ_OUT <='1';
elsif(
(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
) then
LAN_IRQ_OUT <='0';
end if;
end if;
end process autoconfig_proc; --- that's all
end process lan_int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
end if;
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,FCS,reset,Z3_DS,LAN_ACCESS,BERR,CP_ACCESS )
lan_rw_gen: process (CLK_EXT,FCS,reset,Z3_DS,LAN_ACCESS,BERR )
begin
if(reset = '0') then
LAN_SM <=nop;
@@ -443,10 +351,6 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
CP_WAIT <="0000";
CP_RD_S <= '1';
CP_WE_S <= '1';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -454,16 +358,6 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
CP_RD_S <= '1';
CP_WE_S <= '1';
-- delay for clockport
if(CP_ACCESS = '1') then
CP_WAIT <= CP_WAIT+1;
else
CP_WAIT <="0000";
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -486,8 +380,7 @@ begin
end if;
end if;
if(LAN_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(Z3_DS < "1111" and LAN_ACCESS = '1')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
@@ -499,24 +392,16 @@ begin
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
elsif(CP_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(RW='1') then
CP_RD_S <= '0';
LAN_SM <= cp_read;
else
CP_WE_S <= '0';
LAN_SM <= cp_write_wait;
end if;
else
LAN_SM <= nop;
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
@@ -589,7 +474,7 @@ begin
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
if(FCS ='0')then
if(FCS='0')then
LAN_SM<=wait_cycle_end; -- stay here until cylce end
else
LAN_SM <= nop;
@@ -601,33 +486,131 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=wait_cycle_end;
when cp_read=>
CP_RD_S <= '0';
Z3_DATA(31 downto 0) <= DQ & DQ; -- bus mirroring
if(CP_WAIT(3) = '1') then --wait enough for CP-read
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
else
LAN_SM<=cp_read; -- stay here until cp is ready
end if;
when cp_write_wait=>
CP_WE_S <= '0';
if(CP_WAIT(3) = '1') then --wait enough for CP-write
LAN_READY <='1';
LAN_SM<= wait_cycle_end; --deassert CP_W
else
LAN_SM<=cp_write_wait;
end if;
end case;
LAN_SM <= wait_cycle_end;
end case;
end if;
end process lan_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
begin
if reset = '0' then
-- reset active ...
AUTO_CONFIG_Z2_DONE_CYCLE <="000";
D_Z2_OUT<="1111";
SHUT_UP_Z2 <="111";
IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
D_Z2_OUT<="1111";
if(AS='1')then
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE;
elsif(AUTOCONFIG_Z2_ACCESS= '1' and DS='0') then
case A(6 downto 1) is
when "000000" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
else
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
when "000001" => D_Z2_OUT <= "0001" ; --one Card, 64KB =001
when "000010" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1000" ; --ProductID high nibble : 7->1000
else
D_Z2_OUT <= "1111" ; --ProductID high nibble : 0->1111
end if;
when "000011" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "0100" ; --ProductID low nibble: B->0100
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0011" ; --ProductID low nibble: C->0011
else
D_Z2_OUT <= "1001" ; --ProductID low nibble: 6->1001
end if;
when "000100" => --er_flags (Z3)
D_Z2_OUT <= "1110" ; -- io device no size extension 64kb subsize
when "000101" => --er_flags (Z3)
D_Z2_OUT <= "1101" ; -- io device no size extension 64kb subsize
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
when "001001" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0101" ; --Ventor ID 1
else
D_Z2_OUT <= "0111" ; --Ventor ID 1
end if;
when "001010" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1110" ; --Ventor ID 2
else
D_Z2_OUT <= "1101" ; --Ventor ID 2
end if;
when "001011" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
else
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $082C: BSC
end if;
when "001100" => D_Z2_OUT <= "0100" ; --Serial byte 0 (msb) high nibble
when "001101" => D_Z2_OUT <= "1110" ; --Serial byte 0 (msb) low nibble
when "001110" => D_Z2_OUT <= "1001" ; --Serial byte 1 high nibble
when "001111" => D_Z2_OUT <= "0100" ; --Serial byte 1 low nibble
when "010000" => D_Z2_OUT <= "1111" ; --Serial byte 2 high nibble
when "010001" => D_Z2_OUT <= "1111" ; --Serial byte 2 low nibble
when "010010" => D_Z2_OUT <= "0100" ; --Serial byte 3 (lsb) high nibble
when "010011" => D_Z2_OUT <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(2) <= '0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
end if;
end if;
when "100110" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
end if;
end if;
when others => D_Z2_OUT <= "1111" ;
end case;
end if;
end if;
end process autoconfig_proc; --- that's all
--for the future
CP_WE <= CP_WE_S when FCS='0' else '1';
CP_RD <= CP_RD_S when FCS='0' else '1';
CP_CS <= not CP_ACCESS;
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
@@ -647,8 +630,9 @@ begin
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
@@ -658,10 +642,15 @@ begin
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when reset='0' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and (LAN_ACCESS ='1' or CP_ACCESS='1') else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D when RW='0' and AS='0' and CP_ACCESS ='1' else
(others => 'Z');
INT2_OUT <= '0' when LAN_INT = '0' and LAN_INT_ENABLE = '1' else
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
@@ -671,7 +660,7 @@ begin
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
OVR <= 'Z'; --'0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
@@ -713,7 +702,25 @@ begin
ROM_B <= "00";
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS when AS='0' else '1';
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.vm6
+12628 -12041
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.xml
+2 -2
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.xst
+1 -2
View File
@@ -17,9 +17,8 @@ run
-bus_delimiter <>
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Johnson
-fsm_extract YES -fsm_encoding Sequential
-safe_implementation No
-vlgcase Full
-mux_extract Yes
-resource_sharing YES
-iobuf YES
Logic/LAN_IDE/LAN_IDE_CP_build.xml
+5 -5
View File
@@ -1,10 +1,10 @@
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM 'file:///c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
<document>
<design name='LAN_IDE_CP'/>
<rptdir name='LAN_IDE_CP'/>
<xilinx path='c:/Xilinx/14.7/ISE_DS/ISE;'/>
<xilinx path='C:/Xilinx/14.7/ISE_DS/ISE;'/>
<projDir path='C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE'/>
<xslDir path='chipviewer/data/xsl'/>
<fileDir path='/chipviewer/data/html'/>
@@ -69,7 +69,7 @@
<output file='topnav.htm'/>
</xslFile>
<xslFile file='leftnav.xsl'>
<param name='result' value='0'/>
<param name='result' value='1'/>
<output file='leftnav.htm'/>
</xslFile>
<xslFile file='print.xsl'>
@@ -259,7 +259,7 @@
<output file='fbs_FB16.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
<xmlFile file='C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC95288XL-10-TQ144'/>
<param name='verOn' value='0'/>
@@ -271,7 +271,7 @@
<output file='pinlegendV.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='c:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
<xmlFile file='C:/Xilinx/14.7/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC95288XL-10-TQ144'/>
<param name='verOn' value='0'/>
Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
+23 -22
View File
@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sun Feb 24 15:21:43 2019">
<application stringID="NgdBuild" timeStamp="Wed Feb 27 23:01:57 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\AMD\ATI.ACE\Core-Static;C:\Windows\System32\OpenSSH\;%PATH;C:\Users\Matze\Amiga\development\VBCC\bin;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\AMD\ATI.ACE\Core-Static;C:\Windows\System32\OpenSSH\;%PATH;C:\Users\Matze\Amiga\development\VBCC\bin;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps;C:\Users\Matze\adb-fastboot\platform-tools"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
@@ -70,37 +70,38 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="681"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="94"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="456"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="68"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="73"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="41"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="894"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="548"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="412"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="45"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="254"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="49"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="681"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="94"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="456"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="68"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="103"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="894"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="548"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="412"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="254"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="49"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="45"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="33"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
Logic/LAN_IDE/LAN_IDE_CP_pad.csv
+1 -1
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-24-2019 3:25PM
2-27-2019 11:02PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 2-24-2019 3:25PM 2-27-2019 11:02PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
+20 -25
View File
@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sun Feb 24 15:21:26 2019">
<application stringID="Xst" timeStamp="Wed Feb 27 23:01:41 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\AMD\ATI.ACE\Core-Static;C:\Windows\System32\OpenSSH\;%PATH;C:\Users\Matze\Amiga\development\VBCC\bin;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\AMD\ATI.ACE\Core-Static;C:\Windows\System32\OpenSSH\;%PATH;C:\Users\Matze\Amiga\development\VBCC\bin;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps;C:\Users\Matze\adb-fastboot\platform-tools"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
@@ -71,7 +71,7 @@
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Johnson"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Sequential"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
@@ -79,16 +79,13 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="1">
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="96">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="89"/>
<item dataType="int" stringID="XST_REGISTERS" value="84">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="76"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="6"></item>
<item dataType="int" stringID="XST_TRISTATES" value="28">
@@ -100,11 +97,8 @@
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_COUNTERS" value="1">
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="89">
<item dataType="int" stringID="XST_FLIPFLOPS" value="89"/>
<item dataType="int" stringID="XST_REGISTERS" value="74">
<item dataType="int" stringID="XST_FLIPFLOPS" value="74"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
</section>
@@ -125,20 +119,21 @@
<item stringID="XST_IOS" value="117"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="2318">
<item dataType="int" stringID="XST_AND2" value="681"/>
<item dataType="int" stringID="XST_AND3" value="94"/>
<item dataType="int" stringID="XST_BELS" value="1441">
<item dataType="int" stringID="XST_AND2" value="456"/>
<item dataType="int" stringID="XST_AND3" value="68"/>
<item dataType="int" stringID="XST_AND4" value="9"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="894"/>
<item dataType="int" stringID="XST_OR2" value="412"/>
<item dataType="int" stringID="XST_XOR2" value="45"/>
<item dataType="int" stringID="XST_INV" value="548"/>
<item dataType="int" stringID="XST_OR2" value="254"/>
<item dataType="int" stringID="XST_XOR2" value="33"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="153">
<item dataType="int" stringID="XST_FDC" value="29"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="140">
<item dataType="int" stringID="XST_FD" value="3"/>
<item dataType="int" stringID="XST_FDC" value="20"/>
<item dataType="int" stringID="XST_FDCE" value="7"/>
<item dataType="int" stringID="XST_FDP" value="73"/>
<item dataType="int" stringID="XST_FDPE" value="44"/>
<item dataType="int" stringID="XST_FDP" value="41"/>
<item dataType="int" stringID="XST_FDPE" value="69"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="114">
<item dataType="int" stringID="XST_IBUF" value="23"/>
@@ -148,7 +143,7 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="51"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="47"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
</section>
</application>
Logic/LAN_IDE/_ngo/netlist.lst
+1 -1
View File
@@ -1,2 +1,2 @@
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551018095
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551304910
OK
Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
+2 -5
View File
@@ -20,13 +20,10 @@
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">MTCR</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">5</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">CP_CS</arg> to allow all signals assigned to this function block to be placed.
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ&lt;8&gt;</arg> to allow all signals assigned to this function block to be placed.
</msg>
<msg type="error" file="Cpld" num="886" delta="old" >Function block <arg fmt="%s" index="1">FB1</arg> was too congested to route successfully. This occurs due to excessive (&gt;= 50) product term input fanins to this function block. Consider moving output signals in this function block to less congested function blocks, buffering output signals that must remain in this function block, or selecting a larger package.
</msg>
<msg type="error" file="Cpld" num="868" delta="old" >Cannot fit the design into any of the specified devices with the selected implementation options.
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ&lt;4&gt;</arg> to allow all signals assigned to this function block to be placed.
</msg>
</messages>
Logic/LAN_IDE/_xmsgs/pn_parser.xmsgs
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@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd&quot; into library work</arg>
</msg>
</messages>
Logic/LAN_IDE/_xmsgs/xst.xmsgs
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@@ -29,22 +29,10 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">BERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_SM_RST</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_IRQ_OUT</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_IRQ_D0</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">CP_WE_QUIRK</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_SM_RST</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="1799" delta="old" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM &lt;<arg fmt="%s" index="2">LAN_SM</arg>&gt;.
@@ -182,7 +170,7 @@
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">LAN_A_INIT_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">LAN_IDE_CP</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">LAN_D_INIT_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;LAN_D_INIT_10&gt; &lt;LAN_D_INIT_11&gt; &lt;LAN_RST_SM_FSM_FFd4&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">LAN_D_INIT_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;LAN_D_INIT_10&gt; &lt;LAN_D_INIT_11&gt; </arg>
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">LAN_D_INIT_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;LAN_D_INIT_4&gt; &lt;LAN_D_INIT_9&gt; </arg>
Logic/LAN_IDE/area.xds
+2 -2
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@@ -8,9 +8,9 @@
<Properties>
<property name="Synthesize - XST:Optimization Goal" value="Speed"/>
<property name="Synthesize - XST:Optimization Effort" value="High"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Johnson"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Sequential"/>
<property name="Synthesize - XST:Safe Implementation" value="No"/>
<property name="Synthesize - XST:Case Implementation Style" value="Full"/>
<property name="Synthesize - XST:Case Implementation Style" value="None"/>
</Properties>
</DesignStrategy>
Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
+1 -1
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@@ -1,7 +1,7 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-02-24T15:13:03</DateModified>
<DateModified>2019-02-27T22:37:25</DateModified>
<ModuleName>LAN_IDE_CP</ModuleName>
<SummaryTimeStamp>2019-02-23T22:34:10</SummaryTimeStamp>
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
Logic/LAN_IDE/log.txt
+2511 -6386
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Logic/LAN_IDE/tmperr.err
-24
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@@ -1,24 +0,0 @@
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1007 - Removing unused input(s) 'BERR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal CP_CS to allow all signals assigned to this function block to be
placed.
ERROR:Cpld:886 - Function block FB1 was too congested to route successfully.
This occurs due to excessive (>= 50) product term input fanins to this
function block. Consider moving output signals in this function block to less
congested function blocks, buffering output signals that must remain in this
function block, or selecting a larger package.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
Logic/LAN_IDE/webtalk_pn.xml
+2 -3
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sun Feb 24 15:21:25 2019">
<application name="pn" timeStamp="Wed Feb 27 23:01:40 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -18,8 +18,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthCaseImplStyle" value="Full" type="process"/>
<property name="PROP_SynthFsmEncode" value="Johnson" type="process"/>
<property name="PROP_SynthFsmEncode" value="Sequential" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd
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