Dominick.Vansevenant/Zorro-LAN-IDE
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fully clocked z3-statemachine for lan without reset-hack

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MHeinrichs
2019-02-27 23:06:45 +01:00
parent 8230e4fca2
commit 95630fdcf7
34 changed files with 24894 additions and 28495 deletions
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Logic/LAN_IDE/webtalk_pn.xml
+2 -3
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sun Feb 24 15:21:25 2019">
<application name="pn" timeStamp="Wed Feb 27 23:01:40 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -18,8 +18,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthCaseImplStyle" value="Full" type="process"/>
<property name="PROP_SynthFsmEncode" value="Johnson" type="process"/>
<property name="PROP_SynthFsmEncode" value="Sequential" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>