fully clocked z3-statemachine for lan without reset-hack
This commit is contained in:
MHeinrichs
@@ -43,9 +43,8 @@ Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : LAN_IDE_CP
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Johnson
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FSM Encoding Algorithm : Sequential
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Safe Implementation : No
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CASE Implementation Style : Full
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Mux Extraction : Yes
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Resource Sharing : YES
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@@ -72,14 +71,15 @@ wysiwyg : NO
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=========================================================================
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Setting FSM Encoding Algorithm to : JOHN
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Setting FSM Encoding Algorithm to : SEQ
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
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Architecture behavioral of Entity lan_ide_cp is up to date.
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Entity <lan_ide_cp> compiled.
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Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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@@ -110,25 +110,21 @@ INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP>
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <BERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <LAN_SM_RST> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_IRQ_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_IRQ_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <CP_WE_QUIRK> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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-----------------------------------------------------------------------
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| States | 15 |
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| Transitions | 29 |
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| Inputs | 9 |
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| Outputs | 16 |
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| States | 13 |
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| Transitions | 22 |
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| Inputs | 7 |
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| Outputs | 14 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (negative) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | johnson |
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| Encoding | sequential |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
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@@ -142,7 +138,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | johnson |
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| Encoding | sequential |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 16-bit tristate buffer for signal <D>.
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@@ -170,37 +166,39 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 180.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
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Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
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Found 1-bit register for signal <CP_ACCESS>.
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Found 16-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 276.
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Found 16-bit register for signal <CP_BASEADR>.
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Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 289.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 4-bit up counter for signal <CP_WAIT>.
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Found 1-bit register for signal <CP_WE_QUIRK>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <D_Z2_OUT>.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 264.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 256.
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Found 1-bit register for signal <IDE_ACCESS>.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 303.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 296.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 263.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 265.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_IRQ_D0>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 489.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 494.
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Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 383.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 387.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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@@ -211,8 +209,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 32-bit register for signal <Z3_DATA>.
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 89 D-type flip-flop(s).
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inferred 74 D-type flip-flop(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 58 Tristate(s).
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@@ -223,20 +220,18 @@ Unit <LAN_IDE_CP> synthesized.
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HDL Synthesis Report
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Macro Statistics
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# Counters : 1
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4-bit up counter : 1
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# Registers : 96
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1-bit register : 89
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# Registers : 84
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1-bit register : 76
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14-bit register : 2
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16-bit register : 2
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3-bit register : 1
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4-bit register : 1
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8-bit register : 1
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8-bit register : 2
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# Comparators : 6
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16-bit comparator equal : 2
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16-bit comparator equal : 1
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2-bit comparator less : 2
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4-bit comparator less : 1
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8-bit comparator equal : 1
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8-bit comparator equal : 2
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# Tristates : 28
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1-bit tristate buffer : 26
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16-bit tristate buffer : 2
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@@ -249,39 +244,37 @@ Macro Statistics
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* Advanced HDL Synthesis *
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=========================================================================
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:4]> with johnson encoding.
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with sequential encoding.
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------------------------
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State | Encoding
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------------------------
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nop | 0000
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wait0 | 0001
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clr | 0011
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clr_commit | 0111
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wait1 | 1111
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set | 1110
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set_commit | 1100
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done | 1000
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nop | 000
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wait0 | 001
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clr | 010
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clr_commit | 011
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wait1 | 100
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set | 101
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set_commit | 110
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done | 111
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------------------------
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Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:8]> with johnson encoding.
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Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with sequential encoding.
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-------------------------------
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State | Encoding
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-------------------------------
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nop | 00000000
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nop | 0000
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start_read_upper | unreached
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wait_read_upper | 00000011
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end_read_upper | 11111111
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start_read_lower | 11111100
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wait_read_lower | 00000111
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end_read_lower | 11111000
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start_write_upper | 00001111
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wait_write_upper | 11110000
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end_write_upper | 11100000
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start_write_lower | 00011111
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wait_write_lower | 11000000
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wait_cycle_end | 11111110
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config_rw | 00000001
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cp_read | 00111111
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cp_write_wait | 01111111
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wait_read_upper | 0010
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end_read_upper | 0110
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start_read_lower | 1000
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wait_read_lower | 0011
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end_read_lower | 1001
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start_write_upper | 0100
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wait_write_upper | 1010
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end_write_upper | 1011
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start_write_lower | 0101
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wait_write_lower | 1100
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wait_cycle_end | 0111
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config_rw | 0001
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-------------------------------
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
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@@ -311,13 +304,11 @@ Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# Counters : 1
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4-bit up counter : 1
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# Registers : 89
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Flip-Flops : 89
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# Registers : 74
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Flip-Flops : 74
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# Comparators : 3
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16-bit comparator equal : 2
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8-bit comparator equal : 1
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16-bit comparator equal : 1
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8-bit comparator equal : 2
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=========================================================================
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@@ -346,36 +337,32 @@ WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 3 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11> <LAN_RST_SM_FSM_FFd4>
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11>
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=s : D_Z2_OUT_2
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implementation constraint: INIT=s : D_Z2_OUT_0
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implementation constraint: INIT=r : LAN_INT_ENABLE
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implementation constraint: INIT=r : LAN_SM_FSM_FFd8
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implementation constraint: INIT=r : LAN_SM_FSM_FFd7
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implementation constraint: INIT=r : LAN_SM_FSM_FFd6
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implementation constraint: INIT=s : LAN_A_INIT_3
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implementation constraint: INIT=r : LAN_SM_FSM_FFd5
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=r : LAN_SM_FSM_FFd4
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implementation constraint: INIT=s : LAN_A_INIT_6
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implementation constraint: INIT=r : LAN_SM_FSM_FFd3
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implementation constraint: INIT=r : LAN_SM_FSM_FFd2
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implementation constraint: INIT=s : LAN_A_INIT_3
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implementation constraint: INIT=r : LAN_SM_FSM_FFd1
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implementation constraint: INIT=s : LAN_A_INIT_6
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implementation constraint: INIT=s : D_Z2_OUT_3
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=s : D_Z2_OUT_2
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implementation constraint: INIT=s : D_Z2_OUT_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=s : D_Z2_OUT_1
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implementation constraint: INIT=s : D_Z2_OUT_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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@@ -410,23 +397,24 @@ Design Statistics
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# IOs : 117
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Cell Usage :
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# BELS : 2318
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# AND2 : 681
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# AND3 : 94
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# BELS : 1441
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# AND2 : 456
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# AND3 : 68
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# AND4 : 9
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# AND5 : 2
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# AND8 : 5
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# AND5 : 17
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# AND8 : 4
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# GND : 1
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# INV : 894
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# OR2 : 412
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# OR3 : 149
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# OR4 : 26
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# XOR2 : 45
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# FlipFlops/Latches : 153
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# FDC : 29
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# INV : 548
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# OR2 : 254
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# OR3 : 49
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# OR4 : 2
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# XOR2 : 33
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# FlipFlops/Latches : 140
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# FD : 3
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# FDC : 20
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# FDCE : 7
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# FDP : 73
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# FDPE : 44
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# FDP : 41
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# FDPE : 69
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# IO Buffers : 114
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# IBUF : 23
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# IOBUFE : 48
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@@ -436,13 +424,13 @@ Cell Usage :
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Total REAL time to Xst completion: 9.00 secs
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Total CPU time to Xst completion: 9.20 secs
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Total CPU time to Xst completion: 8.79 secs
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-->
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Total memory usage is 4534800 kilobytes
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Total memory usage is 4534808 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 51 ( 0 filtered)
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Number of warnings : 47 ( 0 filtered)
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Number of infos : 10 ( 0 filtered)
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Reference in New Issue
Block a user