Update in Firmware (pure Z2-AC but LAN becomes Z3) and new pcb
This commit is contained in:
MHeinrichs
@@ -0,0 +1,496 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:08:29 12/13/2016
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-- Design Name:
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-- Module Name: LAN_IDE_CP - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- directory cleanup hint:
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-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LAN_IDE_CP is
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Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
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D : inout STD_LOGIC_VECTOR (15 downto 0);
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DQ : inout STD_LOGIC_VECTOR (15 downto 0);
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A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
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OWN : out STD_LOGIC;
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SLAVE : out STD_LOGIC;
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CFOUT : out STD_LOGIC;
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CFIN : in STD_LOGIC;
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C1 : in STD_LOGIC;
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C3 : in STD_LOGIC;
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MTCR : in STD_LOGIC;
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OVR : out STD_LOGIC;
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BERR : in STD_LOGIC;
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MTACK : out STD_LOGIC;
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DS0 : in STD_LOGIC;
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DTACK : out STD_LOGIC;
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UDS : in STD_LOGIC;
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LDS : in STD_LOGIC;
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AS : in STD_LOGIC;
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RW : in STD_LOGIC;
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Z3 : in STD_LOGIC;
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DS1 : in STD_LOGIC;
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FCS : in STD_LOGIC;
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RESET : in STD_LOGIC;
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INT_OUT : out STD_LOGIC;
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AUTOBOOT_OFF : in STD_LOGIC;
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ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
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ROM_OE : out STD_LOGIC;
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IDE_WAIT : in STD_LOGIC;
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CLK_EXT : in STD_LOGIC;
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IDE_W : out STD_LOGIC;
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IDE_R : out STD_LOGIC;
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IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
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IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
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LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
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LAN_RD : out STD_LOGIC;
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LAN_CS : out STD_LOGIC;
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LAN_WRH : out STD_LOGIC;
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LAN_WRL : out STD_LOGIC;
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LAN_INT : in STD_LOGIC;
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CP_RD : out STD_LOGIC;
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CP_WE : out STD_LOGIC;
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CP_CS : out STD_LOGIC;
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CP_IRQ : in STD_LOGIC);
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end LAN_IDE_CP;
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architecture Behavioral of LAN_IDE_CP is
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TYPE lan_reset IS (
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nop,
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wait0,
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clr,
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clr_commit,
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wait1,
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set,
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set_commit,
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done
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);
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SIGNAL LAN_RST_SM: lan_reset :=nop;
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SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
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SIGNAL ide: STD_LOGIC;
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SIGNAL autoconfig: STD_LOGIC;
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SIGNAL lan_adr: STD_LOGIC;
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SIGNAL lan_adr_sw: STD_LOGIC;
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SIGNAL cp: STD_LOGIC;
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signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
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signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(1 downto 0);
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signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
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signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
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signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
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signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
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signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
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signal IDE_ENABLE:STD_LOGIC;
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signal ROM_OE_S:STD_LOGIC;
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signal IDE_R_S:STD_LOGIC;
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signal IDE_W_S:STD_LOGIC;
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signal DTACK_S:STD_LOGIC;
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signal AMIGA_CLK: std_logic;
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signal LAN_INT_ENABLE: std_logic;
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signal DECODE_RESET: std_logic;
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signal LAN_INT_D0: std_logic;
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signal DS: std_logic;
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signal DS_D: std_logic;
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signal LAN_RD_S: std_logic;
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signal LAN_WRH_S: std_logic;
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signal LAN_WRL_S: std_logic;
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signal LAN_IRQ_D0: std_logic;
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signal LAN_IRQ_OUT: std_logic;
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signal CP_RD_S: std_logic;
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signal CP_WE_S: std_logic;
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signal CP_WE_QUIRK: std_logic;
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signal LAN_CS_RST: std_logic;
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signal LAN_WR_RST: std_logic;
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constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
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constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
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constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000";
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constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000";
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Function to_std_logic(X: in Boolean) return Std_Logic is
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variable ret : std_logic;
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begin
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if x then ret := '1'; else ret := '0'; end if;
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return ret;
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end to_std_logic;
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begin
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AMIGA_CLK <= not (C1 xor C3);
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DECODE_RESET <= BERR and reset;
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DS <= UDS and LDS;
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clock_init: process(CLK_EXT)
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begin
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if(rising_edge(CLK_EXT))then
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if(reset = '0')then
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--init the clock!
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case LAN_RST_SM is
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when nop=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait0;
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when wait0=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=clr;
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when clr=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=clr_commit;
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when clr_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait1;
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when wait1=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=set;
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when set=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=set_commit;
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when set_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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when done=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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end case;
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else
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=nop;
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end if;
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end if;
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end process clock_init;
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ADDRESS_DECODE: process(DECODE_RESET,AS)
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begin
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if(DECODE_RESET ='0')then
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autoconfig <= '0';
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ide <= '0';
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lan_adr <= '0';
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lan_adr_sw <= '0';
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cp <= '0';
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lancp <= '0';
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elsif(falling_edge(AS))then
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--default values
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autoconfig <= '0';
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ide <= '0';
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lan_adr <= '0';
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lan_adr_sw <= '0';
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cp <= '0';
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lancp <= '0';
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if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
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autoconfig <= '1';
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elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
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if(A(14 downto 13)<"11")then
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lan_adr_sw <= '1';
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end if;
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lan_adr <= '1';
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lancp <= '1';
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elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
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cp <= '1';
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lancp <= '1';
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elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
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ide <= '1';
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lancp <= '1';
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end if;
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end if;
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end process ADDRESS_DECODE;
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--LAN interrupt enable
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lan_int_proc: process (AMIGA_CLK,reset)
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begin
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if(reset ='0') then
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LAN_INT_ENABLE <='0';
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LAN_IRQ_D0 <='1';
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LAN_IRQ_OUT <='1';
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elsif falling_edge(AMIGA_CLK) then
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LAN_IRQ_D0 <= LAN_INT;
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if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
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LAN_IRQ_OUT <='0';
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elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then
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LAN_IRQ_OUT <='1';
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elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
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LAN_IRQ_OUT <= D(14); --controll lan irq
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end if;
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if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
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LAN_INT_ENABLE <= D(15);
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end if;
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end if;
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end process lan_int_proc;
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--lan signal generation: all Signals are HIGH active!
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lan_rw_gen: process (AMIGA_CLK)
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begin
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if falling_edge(AMIGA_CLK) then
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--default values
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LAN_RD_S <= '0';
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LAN_WRH_S <= '0';
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LAN_WRL_S <= '0';
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if(lan_adr='1' and DS='0' and A(15)='0')then
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LAN_RD_S <= RW;
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-- swapped LDS/UDS here: ENC624 is little endian
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LAN_WRH_S <= not LDS and not RW;
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LAN_WRL_S <= not UDS and not RW;
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end if;
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end if;
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end process lan_rw_gen;
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--cp signal generation
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cp_rw_gen: process (AMIGA_CLK)
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begin
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if falling_edge(AMIGA_CLK) then
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--default values
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CP_RD_S <= '1';
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CP_WE_S <= '1';
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if(cp = '1' and DS='0')then --datastrobe instead of AS!
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CP_RD_S <= not RW;
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CP_WE_S <= RW;
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end if;
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CP_WE_QUIRK <= CP_WE_S;
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end if;
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end process cp_rw_gen;
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--ide signal generation
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ide_rw_gen: process (reset,AMIGA_CLK)
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begin
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if (reset = '0') then
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IDE_ENABLE <= '1';
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IDE_R_S <= '1';
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IDE_W_S <= '1';
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ROM_OE_S <= '1';
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elsif falling_edge(AMIGA_CLK) then
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--default values
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IDE_R_S <= '1';
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IDE_W_S <= '1';
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ROM_OE_S <= '1';
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if(ide='1' and AS='0')then
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if(RW='0')then
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--the write goes to the hdd!
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IDE_ENABLE <= '0'; -- enable IDE on first read
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IDE_W_S <= '0';
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else
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IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
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ROM_OE_S <= not IDE_ENABLE;
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end if;
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end if;
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end if;
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end process ide_rw_gen;
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--autoconfig
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autoconfig_proc: process (reset, AMIGA_CLK)
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begin
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if reset = '0' then
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-- reset active ...
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AUTO_CONFIG_DONE_CYCLE <="00";
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Dout1<="1111";
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--Dout2<="1111";
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SHUT_UP <="111";
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IDE_BASEADR<=x"FF";
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LAN_BASEADR<=x"FF";
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CP_BASEADR<=x"FF";
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AUTO_CONFIG_DONE <="00";
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elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
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DS_D <= DS;
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if(AS='1')then
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AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
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elsif(autoconfig= '1' and DS='0') then
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case A(6 downto 1) is
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when "000000" =>
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if(AUTO_CONFIG_DONE < 2)then
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Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
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else
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Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
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end if;
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when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
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when "000010" =>
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if(AUTO_CONFIG_DONE < 2)then
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Dout1 <= "1000" ; --ProductID high nibble : 7->1000
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else
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Dout1 <= "1111" ; --ProductID high nibble : 0->1111
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end if;
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when "000011" =>
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if(AUTO_CONFIG_DONE = 0)then
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Dout1 <= "0100" ; --ProductID low nibble: B->0100
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elsif(AUTO_CONFIG_DONE = 1)then
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Dout1 <= "0011" ; --ProductID low nibble: C->0011
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else
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Dout1 <= "1001" ; --ProductID low nibble: 6->1001
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end if;
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when "001000" => Dout1 <= "1111" ; --Ventor ID 0
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when "001001" =>
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if(AUTO_CONFIG_DONE < 2)then
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Dout1 <= "0101" ; --Ventor ID 1
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else
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Dout1 <= "0111" ; --Ventor ID 1
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end if;
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when "001010" =>
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if(AUTO_CONFIG_DONE < 2)then
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Dout1 <= "1110" ; --Ventor ID 2
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else
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Dout1 <= "1101" ; --Ventor ID 2
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end if;
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when "001011" =>
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if(AUTO_CONFIG_DONE < 2)then
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Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
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else
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Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC
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end if;
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when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble
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when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble
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when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble
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when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble
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when "010000" => Dout1 <= "1111" ; --Serial byte 2 high nibble
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when "010001" => Dout1 <= "1111" ; --Serial byte 2 low nibble
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when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble
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when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
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--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
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--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
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--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
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when "010111" =>
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if(AUTO_CONFIG_DONE = 2)then
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Dout1 <= "1110" ; --Rom vector low byte low nibble
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else
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Dout1 <= "1111" ; --Rom vector low byte low nibble
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end if;
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when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero
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when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero
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when "100100" =>
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Dout1 <= "1111" ;
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if(RW='0' and DS_D='1')then
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if(AUTO_CONFIG_DONE = 0)then
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LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
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SHUT_UP(0) <='0'; --enable board
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AUTO_CONFIG_DONE_CYCLE <= "01"; --done here
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elsif(AUTO_CONFIG_DONE = 1)then
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CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
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SHUT_UP(1) <= '0'; --enable board
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AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part!
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elsif(AUTO_CONFIG_DONE = 2)then
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IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
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SHUT_UP(2) <= '0'; --enable board
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AUTO_CONFIG_DONE_CYCLE <= "11"; --done here
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end if;
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end if;
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when "100110" =>
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Dout1 <= "1111" ;
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if(RW='0' and DS_D='1')then
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AUTO_CONFIG_DONE_CYCLE <= AUTO_CONFIG_DONE_CYCLE+1; --done here
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end if;
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when others => Dout1 <= "1111" ;
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end case;
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end if;
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end if;
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end process autoconfig_proc; --- that's all
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LAN_CS <= lan_adr when reset='1' else LAN_CS_RST;
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LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
|
||||
LAN_CFG <= "0010"; -- "ZZZZ";
|
||||
|
||||
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||
CP_CS <= not cp;
|
||||
|
||||
--the lanport is shifted by one adress line but I forgot to adopt the clockport address!
|
||||
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip
|
||||
A(14 downto 7);
|
||||
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
|
||||
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(2 downto 1);
|
||||
|
||||
|
||||
|
||||
--signal assignment
|
||||
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
|
||||
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else
|
||||
DQ when RW='1' and ide = '1' and AS='0' else
|
||||
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
|
||||
(others => 'Z');
|
||||
|
||||
--defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
|
||||
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
|
||||
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
|
||||
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
|
||||
D when RW='0' and AS='0' and lancp ='1'
|
||||
else (others => 'Z');
|
||||
|
||||
IDE_W <= IDE_W_S when AS='0' else '1';
|
||||
IDE_R <= IDE_R_S when AS='0' else '1';
|
||||
IDE_CS(0)<= not(A(12));
|
||||
IDE_CS(1)<= not(A(13));
|
||||
IDE_A(2 downto 0) <= A(11 downto 9);
|
||||
ROM_B <= "00";
|
||||
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
|
||||
|
||||
-- INT_OUT <= 'Z';
|
||||
INT_OUT <= '0' when
|
||||
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
|
||||
or CP_IRQ = '0'
|
||||
else 'Z';
|
||||
|
||||
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
|
||||
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
|
||||
|
||||
-- OVR <= 'Z';
|
||||
OVR <= '0' when ide='1' and AS='0' else 'Z';
|
||||
|
||||
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or
|
||||
-- AUTOCONFIG_IN_PROGRES ='1'
|
||||
-- else 'Z';
|
||||
|
||||
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
|
||||
-- DTACK <= 'Z';
|
||||
A <= (others => 'Z');
|
||||
MTACK <= 'Z';
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,460 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:59:54 01/15/2017
|
||||
-- Design Name:
|
||||
-- Module Name: C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP_TB.vhd
|
||||
-- Project Name: LAN_IDE
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: LAN_IDE_CP
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY LAN_IDE_CP_TB IS
|
||||
END LAN_IDE_CP_TB;
|
||||
|
||||
ARCHITECTURE behavior OF LAN_IDE_CP_TB IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT LAN_IDE_CP
|
||||
PORT(
|
||||
A : INOUT std_logic_vector(23 downto 1);
|
||||
D : INOUT std_logic_vector(15 downto 0);
|
||||
DQ : INOUT std_logic_vector(15 downto 0);
|
||||
A_LAN : OUT std_logic_vector(13 downto 0);
|
||||
OWN : OUT std_logic;
|
||||
SLAVE : OUT std_logic;
|
||||
CFOUT : OUT std_logic;
|
||||
CFIN : IN std_logic;
|
||||
C1 : IN std_logic;
|
||||
C3 : IN std_logic;
|
||||
MTCR : IN std_logic;
|
||||
OVR : OUT std_logic;
|
||||
BERR : IN std_logic;
|
||||
MTACK : OUT std_logic;
|
||||
DS0 : IN std_logic;
|
||||
DTACK : OUT std_logic;
|
||||
UDS : IN std_logic;
|
||||
LDS : IN std_logic;
|
||||
AS : IN std_logic;
|
||||
RW : IN std_logic;
|
||||
Z3 : IN std_logic;
|
||||
DS1 : IN std_logic;
|
||||
FCS : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
INT_OUT : OUT std_logic;
|
||||
AUTOBOOT_OFF : IN std_logic;
|
||||
ROM_B : OUT std_logic_vector(1 downto 0);
|
||||
ROM_OE : OUT std_logic;
|
||||
IDE_WAIT : IN std_logic;
|
||||
CLK_EXT : IN std_logic;
|
||||
IDE_W : OUT std_logic;
|
||||
IDE_R : OUT std_logic;
|
||||
IDE_A : OUT std_logic_vector(2 downto 0);
|
||||
IDE_CS : OUT std_logic_vector(1 downto 0);
|
||||
LAN_CFG : OUT std_logic_vector(4 downto 1);
|
||||
LAN_RD : OUT std_logic;
|
||||
LAN_CS : OUT std_logic;
|
||||
LAN_WRH : OUT std_logic;
|
||||
LAN_WRL : OUT std_logic;
|
||||
LAN_INT : IN std_logic;
|
||||
CP_RD : OUT std_logic;
|
||||
CP_WE : OUT std_logic;
|
||||
CP_CS : OUT std_logic;
|
||||
CP_IRQ : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CFIN : std_logic := '0';
|
||||
signal C1 : std_logic := '0';
|
||||
signal C3 : std_logic := '0';
|
||||
signal MTCR : std_logic := '0';
|
||||
signal BERR : std_logic := '0';
|
||||
signal DS0 : std_logic := '0';
|
||||
signal UDS : std_logic := '0';
|
||||
signal LDS : std_logic := '0';
|
||||
signal AS : std_logic := '0';
|
||||
signal RW : std_logic := '0';
|
||||
signal Z3 : std_logic := '0';
|
||||
signal DS1 : std_logic := '0';
|
||||
signal FCS : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal AUTOBOOT_OFF : std_logic := '0';
|
||||
signal IDE_WAIT : std_logic := '0';
|
||||
signal CLK_EXT : std_logic := '0';
|
||||
signal LAN_INT : std_logic := '0';
|
||||
signal CP_IRQ : std_logic := '0';
|
||||
|
||||
--BiDirs
|
||||
signal A : std_logic_vector(23 downto 1);
|
||||
signal D : std_logic_vector(15 downto 0);
|
||||
signal DQ : std_logic_vector(15 downto 0);
|
||||
|
||||
--Outputs
|
||||
signal A_LAN : std_logic_vector(13 downto 0);
|
||||
signal OWN : std_logic;
|
||||
signal SLAVE : std_logic;
|
||||
signal CFOUT : std_logic;
|
||||
signal OVR : std_logic;
|
||||
signal MTACK : std_logic;
|
||||
signal DTACK : std_logic;
|
||||
signal INT_OUT : std_logic;
|
||||
signal ROM_B : std_logic_vector(1 downto 0);
|
||||
signal ROM_OE : std_logic;
|
||||
signal IDE_W : std_logic;
|
||||
signal IDE_R : std_logic;
|
||||
signal IDE_A : std_logic_vector(2 downto 0);
|
||||
signal IDE_CS : std_logic_vector(1 downto 0);
|
||||
signal LAN_CFG : std_logic_vector(4 downto 1);
|
||||
signal LAN_RD : std_logic;
|
||||
signal LAN_CS : std_logic;
|
||||
signal LAN_WRH : std_logic;
|
||||
signal LAN_WRL : std_logic;
|
||||
signal CP_RD : std_logic;
|
||||
signal CP_WE : std_logic;
|
||||
signal CP_CS : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
signal AMIGA_CLK :std_logic;
|
||||
|
||||
constant CLK_EXT_period : time := 40 ns;
|
||||
constant CLK_AMIGA_period : time := 140 ns;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: LAN_IDE_CP PORT MAP (
|
||||
A => A,
|
||||
D => D,
|
||||
DQ => DQ,
|
||||
A_LAN => A_LAN,
|
||||
OWN => OWN,
|
||||
SLAVE => SLAVE,
|
||||
CFOUT => CFOUT,
|
||||
CFIN => CFIN,
|
||||
C1 => C1,
|
||||
C3 => C3,
|
||||
MTCR => MTCR,
|
||||
OVR => OVR,
|
||||
BERR => BERR,
|
||||
MTACK => MTACK,
|
||||
DS0 => DS0,
|
||||
DTACK => DTACK,
|
||||
UDS => UDS,
|
||||
LDS => LDS,
|
||||
AS => AS,
|
||||
RW => RW,
|
||||
Z3 => Z3,
|
||||
DS1 => DS1,
|
||||
FCS => FCS,
|
||||
RESET => RESET,
|
||||
INT_OUT => INT_OUT,
|
||||
AUTOBOOT_OFF => AUTOBOOT_OFF,
|
||||
ROM_B => ROM_B,
|
||||
ROM_OE => ROM_OE,
|
||||
IDE_WAIT => IDE_WAIT,
|
||||
CLK_EXT => CLK_EXT,
|
||||
IDE_W => IDE_W,
|
||||
IDE_R => IDE_R,
|
||||
IDE_A => IDE_A,
|
||||
IDE_CS => IDE_CS,
|
||||
LAN_CFG => LAN_CFG,
|
||||
LAN_RD => LAN_RD,
|
||||
LAN_CS => LAN_CS,
|
||||
LAN_WRH => LAN_WRH,
|
||||
LAN_WRL => LAN_WRL,
|
||||
LAN_INT => LAN_INT,
|
||||
CP_RD => CP_RD,
|
||||
CP_WE => CP_WE,
|
||||
CP_CS => CP_CS,
|
||||
CP_IRQ => CP_IRQ
|
||||
);
|
||||
|
||||
AMIGA_CLK <= not (C1 xor C3);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_EXT_process :process
|
||||
begin
|
||||
CLK_EXT <= '0';
|
||||
wait for CLK_EXT_period/2;
|
||||
CLK_EXT <= '1';
|
||||
wait for CLK_EXT_period/2;
|
||||
end process;
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_13_process :process
|
||||
begin
|
||||
C1 <= '1';
|
||||
C3 <= '0';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '0';
|
||||
C3 <= '0';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '0';
|
||||
C3 <= '1';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '1';
|
||||
C3 <= '1';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <='0';
|
||||
AS <='1';
|
||||
BERR <='1';
|
||||
D <= (others=>'Z');
|
||||
DQ <= (others=>'Z');
|
||||
A <= (others=>'Z');
|
||||
RW <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
CFIN <='0';
|
||||
|
||||
MTCR <='1';
|
||||
DS0 <='1';
|
||||
Z3 <='0';
|
||||
DS1 <='1';
|
||||
FCS <='1';
|
||||
AUTOBOOT_OFF <='1';
|
||||
IDE_WAIT <='1';
|
||||
LAN_INT <='1';
|
||||
CP_IRQ <='1';
|
||||
|
||||
wait for 100 ns;
|
||||
reset <='1';
|
||||
|
||||
wait for CLK_AMIGA_period*10;
|
||||
|
||||
--make a quick autoconfig
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"EAEA"; --address config 1
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"EBEB"; --address config 2
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"ECEC"; --address config 3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on LAN
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EA";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EA";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on CS
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EB";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EB";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on IDE
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EC";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EC";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK);
|
||||
wait until falling_edge(AMIGA_CLK);
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,151 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAN_IDEz2v2.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="LAN_IDE_CP.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="LAN_IDE_CP.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_GYD" xil_pn:name="LAN_IDE_CP.gyd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_JEDEC" xil_pn:name="LAN_IDE_CP.jed"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="LAN_IDE_CP.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MFD" xil_pn:name="LAN_IDE_CP.mfd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGA" xil_pn:name="LAN_IDE_CP.nga"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="LAN_IDE_CP.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="LAN_IDE_CP.pnx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tspec"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP_build.xml"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="LAN_IDE_CP_html"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="LAN_IDE_CP_pad.csv"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1545128934" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1545128934">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545128934" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5081391373936803697" xil_pn:start_ts="1545128934">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595558" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1235887333676579674" xil_pn:start_ts="1545595546">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.lso"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngc"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngr"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.prj"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.stx"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.syr"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.xst"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545079613" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1545079613">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595565" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1545595558">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595609" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1545595565">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.gyd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.mfd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.nga"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.pad"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.pnx"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.vm6"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.xml"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_build.xml"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_html"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595612" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1545595609">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545129218" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1545129218">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForced"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595676" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_configureTargetDevice_CPLD" xil_pn:prop_ck="-154879694275837835" xil_pn:start_ts="1545595673">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:name="TRAN_timRpt">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
@@ -0,0 +1,244 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="LAN_IDE_CP-Z2v2.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="LAN_IDE_CP_TB.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc95288xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Compact" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="LAN_IDE_CP_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="LAN_IDE_CP_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="LAN_IDE_CP_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="LAN_IDE_CP_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="pinlist.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|LAN_IDE_CP_TB|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-12-18T11:26:25" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A2E624B6ED1449CD92F77DE849BF7B51" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
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|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
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|
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|
||||
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|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
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|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
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|
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|
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<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
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|
||||
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|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
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|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
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|
||||
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|
||||
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|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
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|
||||
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|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
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|
||||
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|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
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|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.grf" label="Guide Results Report" />
|
||||
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|
||||
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|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
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|
||||
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|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="netgen/par/LAN_IDE_CP_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
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|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
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|
||||
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|
||||
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|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
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|
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|
||||
</report-views>
|
||||
@@ -0,0 +1,75 @@
|
||||
<?xml version='1.0' encoding='utf-8'?>
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<!--It holds project specific layout data for the projectmgr plugin.-->
|
||||
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
|
||||
<Project version="2" owner="projectmgr" name="LAN_IDEz2v2" >
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/pinlist.ucf)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000015a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000015a0000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/pinlist.ucf)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008b00000001000000000000009d0000000100000000000000660000000100000000000002150000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>LAN_IDE_CP-Z2v2.vhd</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="Library" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>work</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
</Project>
|
||||
@@ -0,0 +1,123 @@
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "A<10>" LOC = "P59" ;
|
||||
NET "A<11>" LOC = "P60" ;
|
||||
NET "A<12>" LOC = "P61" ;
|
||||
NET "A<13>" LOC = "P64" ;
|
||||
NET "A<14>" LOC = "P66" ;
|
||||
NET "A<15>" LOC = "P74" ;
|
||||
NET "A<16>" LOC = "P97" ;
|
||||
NET "A<17>" LOC = "P95" ;
|
||||
NET "A<18>" LOC = "P94" ;
|
||||
NET "A<19>" LOC = "P92" ;
|
||||
NET "A<1>" LOC = "P57" ;
|
||||
NET "A<20>" LOC = "P91" ;
|
||||
NET "A<21>" LOC = "P88" ;
|
||||
NET "A<22>" LOC = "P87" ;
|
||||
NET "A<23>" LOC = "P86" ;
|
||||
NET "A<2>" LOC = "P54" ;
|
||||
NET "A<3>" LOC = "P52" ;
|
||||
NET "A<4>" LOC = "P50" ;
|
||||
NET "A<5>" LOC = "P49" ;
|
||||
NET "A<6>" LOC = "P51" ;
|
||||
NET "A<7>" LOC = "P53" ;
|
||||
NET "A<8>" LOC = "P56" ;
|
||||
NET "A<9>" LOC = "P58" ;
|
||||
NET "A_LAN<0>" LOC = "P4" ;
|
||||
NET "A_LAN<10>" LOC = "P138" ;
|
||||
NET "A_LAN<11>" LOC = "P139" ;
|
||||
NET "A_LAN<12>" LOC = "P136" ;
|
||||
NET "A_LAN<13>" LOC = "P137" ;
|
||||
NET "A_LAN<1>" LOC = "P3" ;
|
||||
NET "A_LAN<2>" LOC = "P6" ;
|
||||
NET "A_LAN<3>" LOC = "P5" ;
|
||||
NET "A_LAN<4>" LOC = "P9" ;
|
||||
NET "A_LAN<5>" LOC = "P7" ;
|
||||
NET "A_LAN<6>" LOC = "P11" ;
|
||||
NET "A_LAN<7>" LOC = "P10" ;
|
||||
NET "A_LAN<8>" LOC = "P140" ;
|
||||
NET "A_LAN<9>" LOC = "P142" ;
|
||||
NET "AS" LOC = "P80" ;
|
||||
NET "AUTOBOOT_OFF" LOC = "P75" ;
|
||||
NET "BERR" LOC = "P98" ;
|
||||
NET "C1" LOC = "P103" ;
|
||||
NET "C3" LOC = "P102" ;
|
||||
NET "CFIN" LOC = "P104" ;
|
||||
NET "CFOUT" LOC = "P105" ;
|
||||
NET "CLK_EXT" LOC = "P30" ;
|
||||
NET "CP_CS" LOC = "P34" ;
|
||||
NET "CP_IRQ" LOC = "P31" ;
|
||||
NET "CP_RD" LOC = "P71" ;
|
||||
NET "CP_WE" LOC = "P70" ;
|
||||
NET "D<0>" LOC = "P2" ;
|
||||
NET "D<10>" LOC = "P41" ;
|
||||
NET "D<11>" LOC = "P43" ;
|
||||
NET "D<12>" LOC = "P44" ;
|
||||
NET "D<13>" LOC = "P45" ;
|
||||
NET "D<14>" LOC = "P46" ;
|
||||
NET "D<15>" LOC = "P48" ;
|
||||
NET "D<1>" LOC = "P17" ;
|
||||
NET "D<2>" LOC = "P39" ;
|
||||
NET "D<3>" LOC = "P15" ;
|
||||
NET "D<4>" LOC = "P21" ;
|
||||
NET "D<5>" LOC = "P20" ;
|
||||
NET "D<6>" LOC = "P14" ;
|
||||
NET "D<7>" LOC = "P16" ;
|
||||
NET "D<8>" LOC = "P19" ;
|
||||
NET "D<9>" LOC = "P40" ;
|
||||
NET "DQ<0>" LOC = "P118" ;
|
||||
NET "DQ<10>" LOC = "P129" ;
|
||||
NET "DQ<11>" LOC = "P115" ;
|
||||
NET "DQ<12>" LOC = "P130" ;
|
||||
NET "DQ<13>" LOC = "P113" ;
|
||||
NET "DQ<14>" LOC = "P131" ;
|
||||
NET "DQ<15>" LOC = "P112" ;
|
||||
NET "DQ<1>" LOC = "P117" ;
|
||||
NET "DQ<2>" LOC = "P120" ;
|
||||
//NET "DQ<2>" LOC = "P68" ; //fix for broken Xilinx
|
||||
NET "DQ<3>" LOC = "P119" ;
|
||||
NET "DQ<4>" LOC = "P124" ;
|
||||
NET "DQ<5>" LOC = "P121" ;
|
||||
//NET "DQ<5>" LOC = "P38" ;//fix for broken Xilinx
|
||||
NET "DQ<6>" LOC = "P126" ;
|
||||
NET "DQ<7>" LOC = "P125" ;
|
||||
NET "DQ<8>" LOC = "P128" ;
|
||||
NET "DQ<9>" LOC = "P116" ;
|
||||
NET "DS0" LOC = "P93" ;
|
||||
NET "DS1" LOC = "P78" ;
|
||||
NET "DTACK" LOC = "P85" ;
|
||||
NET "FCS" LOC = "P77" ;
|
||||
NET "IDE_A<0>" LOC = "P24" ;
|
||||
NET "IDE_A<1>" LOC = "P26" ;
|
||||
NET "IDE_A<2>" LOC = "P25" ;
|
||||
NET "IDE_CS<0>" LOC = "P22" ;
|
||||
NET "IDE_CS<1>" LOC = "P23" ;
|
||||
NET "IDE_R" LOC = "P27" ;
|
||||
NET "IDE_W" LOC = "P28" ;
|
||||
NET "IDE_WAIT" LOC = "P33" ;
|
||||
NET "INT_OUT" LOC = "P32" ;
|
||||
NET "LAN_CFG<1>" LOC = "P12" ;
|
||||
NET "LAN_CFG<2>" LOC = "P135" ;
|
||||
NET "LAN_CFG<3>" LOC = "P13" ;
|
||||
NET "LAN_CFG<4>" LOC = "P110" ;
|
||||
NET "LAN_CS" LOC = "P133" ;
|
||||
NET "LAN_WRL" LOC = "P76" ;
|
||||
NET "LAN_INT" LOC = "P111" ;
|
||||
NET "LAN_RD" LOC = "P134" ;
|
||||
NET "LAN_WRH" LOC = "P132" ;
|
||||
NET "LDS" LOC = "P82" ;
|
||||
NET "MTACK" LOC = "P96" ;
|
||||
NET "MTCR" LOC = "P101" ;
|
||||
NET "OVR" LOC = "P100" ;
|
||||
NET "OWN" LOC = "P107" ;
|
||||
NET "RESET" LOC = "P143" ;
|
||||
NET "ROM_B<0>" LOC = "P68" ;//comment if fix for broken Xilinx!
|
||||
NET "ROM_B<1>" LOC = "P69" ;
|
||||
NET "ROM_OE" LOC = "P35" ;
|
||||
NET "RW" LOC = "P83" ;
|
||||
NET "SLAVE" LOC = "P106" ;
|
||||
NET "UDS" LOC = "P81" ;
|
||||
NET "Z3" LOC = "P79" ;
|
||||
#Created by Constraints Editor (xc95288xl-tq144-10) - 2017/01/26
|
||||
NET "CLK_EXT" TNM_NET = CLK_EXT;
|
||||
TIMESPEC TS_CLK_EXT = PERIOD "CLK_EXT" 25 MHz HIGH 50%;
|
||||
Reference in New Issue
Block a user