Dominick.Vansevenant/Zorro-LAN-IDE
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toggle-edge-detection for fcs

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This commit is contained in:
MHeinrichs
2019-02-28 22:59:03 +01:00
parent 95630fdcf7
commit 943507175a
31 changed files with 20630 additions and 22182 deletions
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Logic/LAN_IDE/LAN_IDE_CP.syr
+64 -58
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@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Sequential
FSM Encoding Algorithm : Compact
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -56,7 +56,7 @@ Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -71,7 +71,7 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : SEQ
Setting FSM Encoding Algorithm to : OPT
=========================================================================
@@ -112,19 +112,20 @@ Synthesizing Unit <LAN_IDE_CP>.
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_CYCLE_IN_PROGRESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
| States | 13 |
| Transitions | 22 |
| Inputs | 7 |
| Transitions | 26 |
| Inputs | 9 |
| Outputs | 14 |
| Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) |
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | sequential |
| Encoding | compact |
| Implementation | automatic |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
@@ -138,7 +139,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | sequential |
| Encoding | compact |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -166,12 +167,12 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 183.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CP_ACCESS>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 289.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 295.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
@@ -179,16 +180,19 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 256.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
Found 1-bit register for signal <FCS_N_D0>.
Found 1-bit register for signal <FCS_P_D0>.
Found 1-bit register for signal <FCS_SM_P_D0>.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 296.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 302.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 265.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 271.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
@@ -197,8 +201,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 383.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 387.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 419.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 423.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
@@ -209,7 +213,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 32-bit register for signal <Z3_DATA>.
Summary:
inferred 2 Finite State Machine(s).
inferred 74 D-type flip-flop(s).
inferred 77 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
inferred 58 Tristate(s).
@@ -220,8 +224,8 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Registers : 84
1-bit register : 76
# Registers : 86
1-bit register : 78
14-bit register : 2
16-bit register : 2
3-bit register : 1
@@ -244,37 +248,37 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with sequential encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with compact encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 001
clr | 010
clr_commit | 011
wait1 | 100
set | 101
set_commit | 110
done | 111
wait0 | 100
clr | 101
clr_commit | 111
wait1 | 001
set | 011
set_commit | 010
done | 110
------------------------
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with sequential encoding.
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with compact encoding.
-------------------------------
State | Encoding
-------------------------------
nop | 0000
start_read_upper | unreached
wait_read_upper | 0010
end_read_upper | 0110
start_read_lower | 1000
wait_read_lower | 0011
end_read_lower | 1001
start_write_upper | 0100
wait_write_upper | 1010
end_write_upper | 1011
start_write_lower | 0101
wait_write_lower | 1100
wait_cycle_end | 0111
config_rw | 0001
wait_read_upper | 1111
end_read_upper | 1100
start_read_lower | 0110
wait_read_lower | 0111
end_read_lower | 0001
start_write_upper | 1011
wait_write_upper | 1110
end_write_upper | 0100
start_write_lower | 0011
wait_write_lower | 1101
wait_cycle_end | 0010
config_rw | 0101
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
@@ -304,8 +308,8 @@ Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 74
Flip-Flops : 74
# Registers : 76
Flip-Flops : 76
# Comparators : 3
16-bit comparator equal : 1
8-bit comparator equal : 2
@@ -342,6 +346,7 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent t
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_0
@@ -355,9 +360,8 @@ Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=s : D_Z2_OUT_2
implementation constraint: INIT=s : D_Z2_OUT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
@@ -397,21 +401,23 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 1441
# AND2 : 456
# AND3 : 68
# AND4 : 9
# AND5 : 17
# BELS : 1292
# AND2 : 404
# AND3 : 63
# AND4 : 17
# AND5 : 1
# AND6 : 2
# AND7 : 1
# AND8 : 4
# GND : 1
# INV : 548
# OR2 : 254
# OR3 : 49
# OR4 : 2
# XOR2 : 33
# FlipFlops/Latches : 140
# INV : 480
# OR2 : 250
# OR3 : 34
# OR4 : 1
# XOR2 : 34
# FlipFlops/Latches : 142
# FD : 3
# FDC : 20
# FDC : 22
# FDCE : 7
# FDP : 41
# FDPE : 69
@@ -423,14 +429,14 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.79 secs
Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.75 secs
-->
Total memory usage is 4534808 kilobytes
Total memory usage is 4534768 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 47 ( 0 filtered)
Number of warnings : 48 ( 0 filtered)
Number of infos : 10 ( 0 filtered)