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Firmware for new version. IDE and CP working

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This commit is contained in:
MHeinrichs
2019-05-26 22:17:28 +02:00
parent ef4c647915
commit 906d8a902f
11 changed files with 3032 additions and 3004 deletions
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Logic/LAN_IDE/LAN_IDE.xise
+6 -6
View File
@@ -41,7 +41,7 @@
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Sequential" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -97,7 +97,7 @@
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -111,8 +111,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -155,7 +155,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE/LAN_IDE_CP.jed
+1 -1
View File
@@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Thu Mar 07 23:51:37 2019
Date Extracted: Wed May 22 23:51:10 2019
QF186624*
QP144*
Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd
+5 -10
View File
@@ -58,8 +58,7 @@ entity LAN_IDE_CP is
DS1 : in STD_LOGIC;
FCS : in STD_LOGIC;
RESET : in STD_LOGIC;
INT2_OUT : out STD_LOGIC;
INT6_OUT : out STD_LOGIC;
INT_OUT : out STD_LOGIC;
AUTOBOOT_OFF : in STD_LOGIC;
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
ROM_OE : out STD_LOGIC;
@@ -69,7 +68,7 @@ entity LAN_IDE_CP is
IDE_R : out STD_LOGIC;
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
-- LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
LAN_RD : out STD_LOGIC;
LAN_CS : out STD_LOGIC;
LAN_WRH : out STD_LOGIC;
@@ -424,7 +423,7 @@ begin
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
-- LAN_CFG <= "0010"; -- "ZZZZ";
LAN_CFG <= "0010"; -- "ZZZZ";
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
@@ -471,14 +470,10 @@ begin
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
-- INT_OUT <= 'Z';
INT2_OUT <= '0' when
INT_OUT <= '0' when
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
or CP_IRQ = '0'
else 'Z';
INT6_OUT <= '0' when
CP_IRQ = '0'
else 'Z';
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
Logic/LAN_IDE_V2/LAN_IDE_CP-z2v2.jed
+1395 -1395
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.jed
+1513 -1513
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.vhd
+5 -11
View File
@@ -504,7 +504,7 @@ begin
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
D_Z2_OUT<="1111";
if(AS='1')then
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE;
AUTO_CONFIG_Z2_DONE <= AUTO_CONFIG_Z2_DONE or AUTO_CONFIG_Z2_DONE_CYCLE or (not AUTOBOOT_OFF & "00") ;
elsif(AUTOCONFIG_Z2_ACCESS= '1' and DS='0') then
case A(6 downto 1) is
when "000000" =>
@@ -615,15 +615,9 @@ begin
-- LAN_CFG <= "ZZZZ";
A_LAN(13 downto 6)<= LAN_A_INIT(13 downto 6) when reset ='0' else
Z3_ADR(14 downto 7);
A_LAN(5 downto 2) <= LAN_A_INIT(5 downto 2) when reset ='0' else
-- A(5 downto 2) when CP_ACCESS='1' else --mux the clock-port adresses! (CP was shifted by 1 on V1 boards, condition disabled here for V2)
Z3_ADR(6 downto 3);
A_LAN(1 downto 0)<= LAN_A_INIT(1 downto 0) when reset ='0' else
Z3_ADR(2) & Z3_A_LOW;
A_LAN(13 downto 0)<= LAN_A_INIT(13 downto 0) when reset ='0' else
Z3_ADR(14 downto 2) & Z3_A_LOW when LAN_ACCESS = '1' else
A(12 downto 1)&"00";
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
@@ -693,7 +687,7 @@ begin
IDE_W <= IDE_W_S when AS='0' else '1';
IDE_R <= IDE_R_S when AS='0' else '1';
ROM_OE<= ROM_OE_S when AS='0' and AUTOBOOT_OFF ='0' else '1';
ROM_OE<= ROM_OE_S when AS='0' else '1';
IDE_CS(0)<= not(A(12));
IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9);
Logic/LAN_IDE_V2/LAN_IDEz2v2.xise
+9 -9
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="LAN_IDE_CP-Z2v2.vhd" xil_pn:type="FILE_VHDL">
@@ -41,7 +41,7 @@
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Compact" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -82,9 +82,9 @@
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP-z2v2|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP-z2v2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -111,7 +111,7 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -129,7 +129,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP-z2v2" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
@@ -146,7 +146,7 @@
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP-z2v2" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
Logic/LAN_IDE_V2/LAN_IDEz3v2.xise
+11 -11
View File
@@ -12,19 +12,19 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="LAN_IDE_CP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="LAN_IDE_CP_TB.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
@@ -41,7 +41,7 @@
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -111,8 +111,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -129,7 +129,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP-z3v2" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP-z3v2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
@@ -155,7 +155,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
PCB/ZORRO-LAN-IDE-CP-V2F.brd
+4 -4
View File
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.5.0">
<eagle version="6.6.0">
<drawing>
<settings>
<setting alwaysvectorfont="yes"/>
@@ -3150,7 +3150,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
<attribute name="NAME" x="42.1792125" y="68.05243125" size="0.8128" layer="25" rot="R180"/>
<attribute name="VALUE" x="44.205965625" y="67.071175" size="0.6096" layer="27" rot="R180"/>
</element>
<element name="C20" library="rcl" package="C1210K" value="10u" x="109.934375" y="64.5795" smashed="yes">
<element name="C20" library="rcl" package="C1206K" value="10u" x="109.934375" y="64.5795" smashed="yes">
<attribute name="NAME" x="109.76371875" y="62.17229375" size="0.8128" layer="25"/>
<attribute name="VALUE" x="109.6723" y="66.20165" size="0.8128" layer="27"/>
</element>
@@ -3234,7 +3234,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
<attribute name="NAME" x="73.817059375" y="69.677809375" size="1.016" layer="25" rot="R90"/>
<attribute name="VALUE" x="72.57335" y="70.147315625" size="1.016" layer="27" rot="R90"/>
</element>
<element name="R12" library="rcl" package="R0603" value="3.3k" x="91.028115625" y="61.5221125" smashed="yes" rot="R270">
<element name="R12" library="rcl" package="R0603" value="4.7k" x="91.028115625" y="61.5221125" smashed="yes" rot="R270">
<attribute name="NAME" x="91.694865625" y="63.2366125" size="1.27" layer="25" rot="R270"/>
<attribute name="VALUE" x="89.043740625" y="63.4112375" size="1.27" layer="27" rot="R270"/>
</element>
@@ -3368,7 +3368,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
<attribute name="NAME" x="112.601375" y="30.32125" size="1.27" layer="25" ratio="10"/>
<attribute name="VALUE" x="117.236875" y="27.3685" size="1.27" layer="27" ratio="10"/>
</element>
<element name="C31" library="rcl" package="C1210K" value="47u" x="124.761625" y="17.0815"/>
<element name="C31" library="rcl" package="C1206K" value="47u" x="124.761625" y="17.0815"/>
<element name="C32" library="rcl" package="C0603K" value="100n" x="44.54525" y="54.689375" rot="MR180"/>
<element name="Q2" library="crystal" package="HC49UP" value="25MHz" x="82.45475" y="34.432875" smashed="yes" rot="R180">
<attribute name="OC_NEWARK" value="unknown" x="82.45475" y="34.432875" size="1.778" layer="27" rot="R180" display="off"/>
PCB/ZORRO-LAN-IDE-CP-V2F.sch
+44 -44
View File
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.5.0">
<eagle version="6.6.0">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
@@ -8,34 +8,34 @@
</settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/>
<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/>
<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/>
<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/>
<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/>
<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/>
<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/>
<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/>
<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/>
<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/>
<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/>
<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/>
<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/>
<layer number="2" name="Route2" color="1" fill="3" visible="yes" active="no"/>
<layer number="3" name="Route3" color="4" fill="3" visible="yes" active="no"/>
<layer number="4" name="Route4" color="1" fill="4" visible="yes" active="no"/>
<layer number="5" name="Route5" color="4" fill="4" visible="yes" active="no"/>
<layer number="6" name="Route6" color="1" fill="8" visible="yes" active="no"/>
<layer number="7" name="Route7" color="4" fill="8" visible="yes" active="no"/>
<layer number="8" name="Route8" color="1" fill="2" visible="yes" active="no"/>
<layer number="9" name="Route9" color="4" fill="2" visible="yes" active="no"/>
<layer number="10" name="Route10" color="1" fill="7" visible="yes" active="no"/>
<layer number="11" name="Route11" color="4" fill="7" visible="yes" active="no"/>
<layer number="12" name="Route12" color="1" fill="5" visible="yes" active="no"/>
<layer number="13" name="Route13" color="4" fill="5" visible="yes" active="no"/>
<layer number="14" name="Route14" color="1" fill="6" visible="yes" active="no"/>
<layer number="15" name="Route15" color="4" fill="6" visible="yes" active="no"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/>
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/>
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/>
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/>
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/>
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/>
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/>
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/>
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/>
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="no"/>
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="no"/>
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="no"/>
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="no"/>
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
@@ -44,8 +44,8 @@
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
<layer number="37" name="tTest" color="7" fill="1" visible="yes" active="no"/>
<layer number="38" name="bTest" color="7" fill="1" visible="yes" active="no"/>
<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
@@ -53,16 +53,16 @@
<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="no"/>
<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="no" active="no"/>
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="no" active="no"/>
<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
<layer number="46" name="Milling" color="3" fill="1" visible="yes" active="no"/>
<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="no"/>
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="no"/>
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="no"/>
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="no"/>
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="no"/>
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="no"/>
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="no"/>
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="no"/>
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="no"/>
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
@@ -13823,7 +13823,7 @@ Low profile connectors, straight&lt;p&gt;
<part name="GND30" library="supply1" deviceset="GND" device=""/>
<part name="GND31" library="supply1" deviceset="GND" device=""/>
<part name="P+3" library="supply1" deviceset="+5V" device=""/>
<part name="C20" library="rcl" deviceset="C-EU" device="C1210K" value="10u"/>
<part name="C20" library="rcl" deviceset="C-EU" device="C1206K" value="10u"/>
<part name="GND32" library="supply1" deviceset="GND" device=""/>
<part name="C21" library="rcl" deviceset="C-EU" device="C1210K" value="10u"/>
<part name="GND33" library="supply1" deviceset="GND" device=""/>
@@ -13849,7 +13849,7 @@ Low profile connectors, straight&lt;p&gt;
<part name="R10" library="rcl" deviceset="R-EU_" device="R0805" value="1K"/>
<part name="FRAME3" library="frames" deviceset="A4L-LOC" device=""/>
<part name="R11" library="rcl" deviceset="R-EU_" device="R0805" value="1K"/>
<part name="R12" library="rcl" deviceset="R-EU_" device="R0603" value="3.3k"/>
<part name="R12" library="rcl" deviceset="R-EU_" device="R0603" value="4.7k"/>
<part name="IC1" library="OLIMEX-ENJ" deviceset="ENC624J600" device=""/>
<part name="C1" library="rcl" deviceset="C-EU" device="C0805K" value="100nF"/>
<part name="C3" library="rcl" deviceset="C-EU" device="C0805K" value="100nF"/>
@@ -13890,7 +13890,7 @@ Low profile connectors, straight&lt;p&gt;
<part name="GND35" library="supply1" deviceset="GND" device=""/>
<part name="LEDB" library="jumper" deviceset="JP1E" device=""/>
<part name="LEDA" library="jumper" deviceset="JP1E" device=""/>
<part name="C31" library="rcl" deviceset="C-EU" device="C1210K" value="47u"/>
<part name="C31" library="rcl" deviceset="C-EU" device="C1206K" value="47u"/>
<part name="C32" library="rcl" deviceset="C-EU" device="C0603K" value="100n"/>
<part name="Q2" library="crystal" deviceset="CRYSTAL" device="HC49UP" value="25MHz"/>
<part name="SV1" library="con-ml" deviceset="ML14" device=""/>
PCB/ZORRO-LAN-IDE-CP-V2F.txt
+39
View File
@@ -0,0 +1,39 @@
Stückliste exportiert aus C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/PCB/ZORRO-LAN-IDE-CP-V2F.sch am 19.05.2019 21:33:40
Qty Value Device Package Parts Description MF MPN OC_FARNELL OC_NEWARK
1 4R-NCAY16 CAY16 RN1 Array Chip Resistor unknown unknown
6 JP1E JP1 AUTOBOOT_ON, IDE_ACT, IDE_OFF, JP1, LEDA, LEDB JUMPER
1 ML10L ML10L SV2 HARTING unknown unknown
1 ML14 ML14 SV1 HARTING unknown unknown
1 ML40 ML40 IDE HARTING unknown unknown
2 SJ SJ SJ1, SJ2 SMD solder JUMPER
1 10 R-EU_R0603 R0603 R19 RESISTOR, European symbol
12 100n C-EUC0603K C0603K C9, C10, C11, C12, C14, C15, C16, C17, C22, C29, C30, C32 CAPACITOR, European symbol
8 100nF C-EUC0805K C0805K C1, C3, C4, C6, C7, C8, C13, C18 CAPACITOR, European symbol
2 10n C-EUC0805K C0805K C28, C33 CAPACITOR, European symbol
2 10u C-EUC0805K C0805K C2, C23 CAPACITOR, European symbol
1 10u C-EUC1206K C1206K C19 CAPACITOR, European symbol
2 10u C-EUC1210K C1210K C20, C21 CAPACITOR, European symbol
1 12k R-EU_R0603 R0603 R13 RESISTOR, European symbol
2 180 R-EU_R0603 R0603 R6, R14 RESISTOR, European symbol
2 1K R-EU_R0805 R0805 R10, R11 RESISTOR, European symbol
1 25MHz CRYSTALHC18U-V HC18U-V Q1 CRYSTAL unknown unknown
1 25MHz CRYSTALHC49UP HC49UP Q2 CRYSTAL unknown unknown
2 27p C-EUC0805K C0805K C24, C25 CAPACITOR, European symbol
1 3.3k R-EU_R0603 R0603 R12 RESISTOR, European symbol
1 330 R-EU_R0603 R0603 R7 RESISTOR, European symbol
1 390 R-EU_R0603 R0603 R4 RESISTOR, European symbol
6 4.7k R-EU_R0603 R0603 R1, R2, R3, R5, R8, R9 RESISTOR, European symbol
1 47u C-EUC1210K C1210K C31 CAPACITOR, European symbol
1 47uF C-EUC1206K C1206K C5 CAPACITOR, European symbol
4 49.9 R-EU_R0603 R0603 R15, R16, R17, R18 RESISTOR, European symbol
1 500mA R-EU_R2512 R2512 F1 RESISTOR, European symbol
2 6.8n C-EUC0805K C0805K C26, C27 CAPACITOR, European symbol
3 74HCT245PW 74HCT245PW TSSOP20 IC3, IC4, IC5 Octal BUS TRANSCEIVER, 3-state
1 A1200-CLOCKPORT A1200-CLOCKPORT CP-2X11-2.00 CN2
1 AM29F010S AM29F010S PLCC-SR32 IC8 1-Megabit FLASH MEMORY
1 ENC624J600 ENC624J600 SQFP-S-10X10-64 IC1
1 LD117ADT33TR LD117ADT33TR DPACK IC7 Low drop fixed and adjustable positive voltage regulators 1 A
1 SI-50170 SI-50170 SI-50170 X1 Ethernet Connector MagJack (R) unknown unknown
1 XC95288XL-TQ144 XC95288XL-TQ144 TQFP144 IC2
1 ZORROII_EDGE_ROUND_CONTACTS ZORROII_EDGE_ROUND_CONTACTS LKONT_50_R CN1