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CP timing fixed and Bytemirror for CP

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MHeinrichs
2017-01-27 23:47:04 +01:00
parent c5e1b0debd
commit 8e2723cc99
59 changed files with 18437 additions and 15856 deletions
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Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
-6
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@@ -11,9 +11,6 @@
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal &apos;<arg fmt="%s" index="1">CLK_EXT</arg>&apos; based upon the LOC constraint &apos;<arg fmt="%s" index="2">P30</arg>&apos;. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
</msg>
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal &apos;<arg fmt="%s" index="1">DQ&lt;5&gt;</arg>&apos; based upon the LOC constraint &apos;<arg fmt="%s" index="2">P38</arg>&apos;. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DS0</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
@@ -29,8 +26,5 @@
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">Z3</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1239" delta="old" >The global <arg fmt="%s" index="1">clock</arg> designation (BUFG) on signal &apos;<arg fmt="%s" index="2">N41</arg>&apos; is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal.
</msg>
</messages>