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@@ -11,9 +11,6 @@
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">DQ<5></arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P38</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DS0</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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@@ -29,7 +26,7 @@
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">Z3</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1239" delta="new" >The global <arg fmt="%s" index="1">clock</arg> designation (BUFG) on signal '<arg fmt="%s" index="2">N66</arg>' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal.
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<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ<8></arg> to allow all signals assigned to this function block to be placed.
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</msg>
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</messages>
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