Dominick.Vansevenant/Zorro-LAN-IDE
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Fixed reset issue: The initialisation loop must be performed exactly once!

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buffered address
This commit is contained in:
MHeinrichs
2022-03-08 12:25:56 +01:00
parent dc65757a8a
commit 88cdb9fb52
14 changed files with 17896 additions and 16293 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP.syr
+57 -46
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: LAN_IDE_CP.prj
@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Gray
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -71,15 +71,12 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : Gray
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
Architecture behavioral of Entity lan_ide_cp is up to date.
=========================================================================
* Design Hierarchy Analysis *
@@ -91,7 +88,7 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 158: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 161: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AMIGA_CLK>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -122,13 +119,13 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
| States | 8 |
| Transitions | 8 |
| Inputs | 0 |
| Outputs | 9 |
| Outputs | 10 |
| Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) |
| Reset | LAN_RST_SM$and0000 (positive) |
| Reset type | synchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | gray |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -139,15 +136,16 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 1-bit tristate buffer for signal <DTACK>.
Found 1-bit tristate buffer for signal <INT2_OUT>.
Found 1-bit tristate buffer for signal <INT6_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 151.
Found 14-bit register for signal <A_LAN_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 153.
Found 1-bit register for signal <AS_D>.
Found 2-bit register for signal <AUTO_CONFIG_DONE>.
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 464.
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 472.
Found 1-bit register for signal <autoconfig>.
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 227.
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 235.
Found 1-bit register for signal <cp>.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 237.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 245.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
@@ -155,17 +153,17 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 16-bit register for signal <D_IN>.
Found 16-bit register for signal <D_OUT>.
Found 4-bit register for signal <Dout1>.
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 391.
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 399.
Found 1-bit register for signal <ide>.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 241.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 249.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <lan_adr>.
Found 1-bit register for signal <lan_adr_sw>.
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 230.
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 231.
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 238.
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 239.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
@@ -176,6 +174,7 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
Found 1-bit register for signal <ROM_OE_S>.
Found 1-bit register for signal <SET_FREQUENCY>.
Found 3-bit register for signal <SHUT_UP>.
Summary:
inferred 1 Finite State Machine(s).
@@ -193,8 +192,9 @@ HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
2-bit subtractor : 1
# Registers : 32
1-bit register : 24
# Registers : 34
1-bit register : 25
14-bit register : 1
16-bit register : 2
2-bit register : 2
4-bit register : 1
@@ -216,19 +216,22 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:8]> with one-hot encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 001
clr | 011
clr_commit | 010
wait1 | 110
set | 111
set_commit | 101
done | 100
nop | 00000001
wait0 | 00000010
clr | 00000100
clr_commit | 00001000
wait1 | 00010000
set | 00100000
set_commit | 01000000
done | 10000000
------------------------
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block SET_FREQUENCY.
You should achieve better results by setting this init to 0.
=========================================================================
Advanced HDL Synthesis Report
@@ -247,8 +250,16 @@ Macro Statistics
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch SET_FREQUENCY hinder the constant cleaning in the block LAN_IDE_CP.
You should achieve better results by setting this init to 0.
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SET_FREQUENCY
implementation constraint: INIT=s : LAN_RST_SM_FSM_FFd8
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd7
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd6
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd5
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
@@ -283,23 +294,23 @@ Design Statistics
# IOs : 113
Cell Usage :
# BELS : 745
# AND2 : 193
# AND3 : 54
# BELS : 879
# AND2 : 267
# AND3 : 41
# AND4 : 7
# AND8 : 3
# GND : 1
# INV : 284
# OR2 : 155
# OR3 : 20
# OR4 : 2
# INV : 333
# OR2 : 166
# OR3 : 32
# OR4 : 3
# XOR2 : 26
# FlipFlops/Latches : 91
# FD : 6
# FDC : 8
# FlipFlops/Latches : 111
# FD : 25
# FDC : 5
# FDCE : 33
# FDP : 7
# FDPE : 37
# FDP : 10
# FDPE : 38
# IO Buffers : 106
# IBUF : 35
# IOBUFE : 32
@@ -308,14 +319,14 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.72 secs
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.77 secs
-->
Total memory usage is 4514348 kilobytes
Total memory usage is 4514408 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 13 ( 0 filtered)
Number of warnings : 15 ( 0 filtered)
Number of infos : 1 ( 0 filtered)