Dominick.Vansevenant/Zorro-LAN-IDE
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Improved clock startup and IDE-ROM-timing

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This commit is contained in:
MHeinrichs
2020-10-09 00:17:40 +02:00
parent 02c04ac3c5
commit 8231b54f78
15 changed files with 3217 additions and 4897 deletions
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.gitignore
+48
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@@ -121,3 +121,51 @@ Logic/LAN_IDE_V2/LAN_IDE_CP_html/tim/
Logic/LAN_IDE/LAN_IDE\.zip Logic/LAN_IDE/LAN_IDE\.zip
/PCB/ZORRO-LAN-IDE-CP-V2F.s## /PCB/ZORRO-LAN-IDE-CP-V2F.s##
/Logic/LAN_IDE_V2/iseconfig/LAN_IDE_CP.xreport
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz2v2.projectmgr
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz3v2.projectmgr
/Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
/Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
/Logic/LAN_IDE_V2/LAN_IDE_CP.jed
/Logic/LAN_IDE_V2/LAN_IDE_CP.mfd
/Logic/LAN_IDE_V2/LAN_IDE_CP.nga
/Logic/LAN_IDE_V2/LAN_IDE_CP.ngd
/Logic/LAN_IDE_V2/LAN_IDE_CP.pad
/Logic/LAN_IDE_V2/LAN_IDE_CP.rpt
/Logic/LAN_IDE_V2/LAN_IDE_CP.syr
/Logic/LAN_IDE_V2/LAN_IDE_CP.tspec
/Logic/LAN_IDE/area.xds
/Logic/LAN_IDE_V2/iseconfig/LAN_IDE_CP.xreport
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz2v2.projectmgr
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz3v2.projectmgr
/Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
/Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
/Logic/LAN_IDE_V2/LAN_IDE_CP.jed
/Logic/LAN_IDE/area.xds
/Logic/LAN_IDE_V2/iseconfig/LAN_IDE_CP.xreport
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz2v2.projectmgr
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz3v2.projectmgr
/Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
/Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
/Logic/LAN_IDE_V2/LAN_IDE_CP.jed
/Bilder/Patch Rapidroad.png
/Driver/rapidroadcpusb.device
/Driver/rapidroadcpusb-.device
/Driver/rapidroadcpusb-orig.device
/Driver/rapidroadxs100usb.device
/Driver/rapidroadxs100usb-orig.device
/Logic/LAN_IDE/area.xds
/Logic/LAN_IDE_V2/iseconfig/LAN_IDE_CP.xreport
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz2v2.projectmgr
/Logic/LAN_IDE_V2/iseconfig/LAN_IDEz3v2.projectmgr
/Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
/Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
/Logic/LAN_IDE_V2/LAN_IDE_CP.mfd
/Logic/LAN_IDE_V2/LAN_IDE_CP.nga
/Logic/LAN_IDE_V2/LAN_IDE_CP.ngd
/Logic/LAN_IDE_V2/LAN_IDE_CP.pad
/Logic/LAN_IDE_V2/LAN_IDE_CP.rpt
/Logic/LAN_IDE_V2/LAN_IDE_CP.syr
/Logic/LAN_IDE_V2/LAN_IDE_CP.tspec
/Logic/LAN_IDE_V2/LAN_IDE_CP.vm6
/Logic/LAN_IDE_V2/ZORO_LAN_IDE_Z2.ipf
Logic/LAN_IDE/area.xds
-16
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@@ -1,16 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<DesignStrategy goal="Balanced" strategy="area" version="12.1">
<Description>The Default strategy provides a balanced optimization of performance results vs. runtime. The default property values correspond to the default values of each of the underlying implementation tools. This strategy keeps all properties in an unlocked state so that you can modify the values as you wish.</Description>
<DeviceList devices="xc9500xl"/>
<Properties>
<property name="Synthesize - XST:Optimization Goal" value="Speed"/>
<property name="Synthesize - XST:Optimization Effort" value="High"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Gray"/>
<property name="Synthesize - XST:Safe Implementation" value="No"/>
<property name="Synthesize - XST:Case Implementation Style" value="None"/>
</Properties>
</DesignStrategy>
Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd
+79 -51
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@@ -110,6 +110,8 @@ architecture Behavioral of LAN_IDE_CP is
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0); signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal IDE_ENABLE:STD_LOGIC; signal IDE_ENABLE:STD_LOGIC;
signal ROM_OE_S:STD_LOGIC; signal ROM_OE_S:STD_LOGIC;
signal ROM_OE_D0:STD_LOGIC;
signal IDE_TERM:STD_LOGIC;
signal IDE_R_S:STD_LOGIC; signal IDE_R_S:STD_LOGIC;
signal IDE_W_S:STD_LOGIC; signal IDE_W_S:STD_LOGIC;
signal DTACK_S:STD_LOGIC; signal DTACK_S:STD_LOGIC;
@@ -118,7 +120,7 @@ architecture Behavioral of LAN_IDE_CP is
signal DECODE_RESET: std_logic; signal DECODE_RESET: std_logic;
signal LAN_INT_D0: std_logic; signal LAN_INT_D0: std_logic;
signal DS: std_logic; signal DS: std_logic;
signal DS_D: std_logic; signal DS_D: std_logic;
signal LAN_RD_S: std_logic; signal LAN_RD_S: std_logic;
signal LAN_WRH_S: std_logic; signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic; signal LAN_WRL_S: std_logic;
@@ -152,8 +154,12 @@ begin
clock_init: process(CLK_EXT) clock_init: process(CLK_EXT)
begin begin
if(rising_edge(CLK_EXT))then if(rising_edge(CLK_EXT))then
if(reset = '0')then if(reset = '0' )then
--init the clock! LAN_RST_SM <= nop;
LAN_CS_RST<='0';
LAN_WR_RST<='0';
else
--init the clock afer reset finished!
case LAN_RST_SM is case LAN_RST_SM is
when nop=> when nop=>
LAN_CS_RST<='0'; LAN_CS_RST<='0';
@@ -183,29 +189,25 @@ begin
LAN_CS_RST<='1'; LAN_CS_RST<='1';
LAN_WR_RST<='0'; LAN_WR_RST<='0';
LAN_RST_SM<=done; LAN_RST_SM<=done;
when done=> when done=> --stay here
LAN_CS_RST<='0'; LAN_CS_RST<='0';
LAN_WR_RST<='0'; LAN_WR_RST<='0';
LAN_RST_SM<=done; LAN_RST_SM<=done;
end case; end case;
else
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=nop;
end if; end if;
end if; end if;
end process clock_init; end process clock_init;
ADDRESS_DECODE: process(DECODE_RESET,AS) ADDRESS_DECODE: process(reset,AMIGA_CLK)
begin begin
if(DECODE_RESET ='0')then if(reset ='0')then
autoconfig <= '0'; autoconfig <= '0';
ide <= '0'; ide <= '0';
lan_adr <= '0'; lan_adr <= '0';
lan_adr_sw <= '0'; lan_adr_sw <= '0';
cp <= '0'; cp <= '0';
lancp <= '0'; lancp <= '0';
elsif(falling_edge(AS))then elsif(rising_edge(AMIGA_CLK))then
--default values --default values
autoconfig <= '0'; autoconfig <= '0';
ide <= '0'; ide <= '0';
@@ -255,11 +257,15 @@ begin
end process lan_int_proc; end process lan_int_proc;
--lan signal generation: all Signals are HIGH active! --lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (AMIGA_CLK) lan_rw_gen: process (AMIGA_CLK,AS)
begin begin
if falling_edge(AMIGA_CLK) then if(AS ='1') then
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
elsif falling_edge(AMIGA_CLK) then
--default values --default values
LAN_RD_S <= '0'; LAN_RD_S <= '0';
LAN_WRH_S <= '0'; LAN_WRH_S <= '0';
LAN_WRL_S <= '0'; LAN_WRL_S <= '0';
@@ -273,9 +279,13 @@ begin
end process lan_rw_gen; end process lan_rw_gen;
--cp signal generation --cp signal generation
cp_rw_gen: process (AMIGA_CLK) cp_rw_gen: process (AMIGA_CLK,AS)
begin begin
if falling_edge(AMIGA_CLK) then if (AS = '1') then
CP_WE_QUIRK <= '1';
CP_WE_S <= '1';
CP_RD_S <= '1';
elsif falling_edge(AMIGA_CLK) then
--default values --default values
CP_RD_S <= '1'; CP_RD_S <= '1';
CP_WE_S <= '1'; CP_WE_S <= '1';
@@ -288,27 +298,55 @@ begin
end process cp_rw_gen; end process cp_rw_gen;
--ide signal generation --ide signal generation
ide_rw_gen: process (reset,AMIGA_CLK) ide_enable_gen: process (reset,AMIGA_CLK)
begin begin
if (reset = '0') then if (reset = '0') then
IDE_ENABLE <= '1'; IDE_ENABLE <= '1';
elsif falling_edge(AMIGA_CLK) then
if(ide='1' and AS='0' and RW='0')then
IDE_ENABLE <= '0'; -- enable IDE on first write
end if;
end if;
end process ide_enable_gen;
ide_rw_gen: process (AS,AMIGA_CLK)
begin
if (AS = '1') then
IDE_R_S <= '1'; IDE_R_S <= '1';
IDE_W_S <= '1'; IDE_W_S <= '1';
ROM_OE_S <= '1'; ROM_OE_S <= '1';
ROM_OE_D0 <= '1';
IDE_TERM <= '1';
elsif falling_edge(AMIGA_CLK) then elsif falling_edge(AMIGA_CLK) then
--default values
IDE_R_S <= '1'; if(ide='1')then
IDE_W_S <= '1';
ROM_OE_S <= '1';
if(ide='1' and AS='0')then
if(RW='0')then if(RW='0')then
--the write goes to the hdd! --the write goes to the hdd!
IDE_ENABLE <= '0'; -- enable IDE on first read
IDE_W_S <= '0'; IDE_W_S <= '0';
IDE_R_S <= '1';
ROM_OE_S <= '1';
ROM_OE_D0 <= '1';
IDE_TERM <= not IDE_WAIT or IDE_W_S;
elsif(IDE_ENABLE ='1')then
IDE_W_S <= '1';
IDE_R_S <= '1';
ROM_OE_S <= '0'; --read from ROM instead from IDE
ROM_OE_D0 <= ROM_OE_S;
IDE_TERM <= '0';
else else
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM IDE_W_S <= '1';
ROM_OE_S <= not IDE_ENABLE; IDE_R_S <= '0'; --read from IDE instead from ROM
ROM_OE_S <= '1';
ROM_OE_D0 <= '1';
IDE_TERM <= not IDE_WAIT or IDE_R_S;
end if; end if;
else
--default values
IDE_R_S <= '1';
IDE_W_S <= '1';
ROM_OE_S <= '1';
ROM_OE_D0 <= '1';
IDE_TERM <= '1';
end if; end if;
end if; end if;
end process ide_rw_gen; end process ide_rw_gen;
@@ -337,7 +375,7 @@ begin
if(AUTO_CONFIG_DONE < 2)then if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
else else
Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM Dout1 <= "1101" ; --ZII, no System-Memory, ROM
end if; end if;
when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001 when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
when "000010" => when "000010" =>
@@ -402,7 +440,7 @@ begin
elsif(AUTO_CONFIG_DONE = 1)then elsif(AUTO_CONFIG_DONE = 1)then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(1) <= '0'; --enable board SHUT_UP(1) <= '0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part! AUTO_CONFIG_DONE_CYCLE <= ('1' & not(AUTOBOOT_OFF)); --done here, if Autoboot = 1 skip ide part!
elsif(AUTO_CONFIG_DONE = 2)then elsif(AUTO_CONFIG_DONE = 2)then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(2) <= '0'; --enable board SHUT_UP(2) <= '0'; --enable board
@@ -431,16 +469,10 @@ begin
CP_CS <= not cp; CP_CS <= not cp;
--the lanport is shifted by one adress line but I forgot to adopt the clockport address! --the lanport is shifted by one adress line but I forgot to adopt the clockport address!
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else A_LAN(13 downto 0)<= LAN_A_CLRREG(13 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else LAN_A_SETREG(13 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip A(14 downto 1) when lan_adr ='1' else
A(14 downto 7); A(12 downto 1) &"00";
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(2 downto 1);
@@ -448,16 +480,16 @@ begin
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and (cp = '1' or ROM_OE_S ='0') and AS='0' else
DQ when RW='1' and ide = '1' and AS='0' else DQ when RW='1' and ide = '1' and ROM_OE_S ='1' and AS='0' else
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
(others => 'Z'); (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards) --defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else --D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else --D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
D when RW='0' and AS='0' and lancp ='1' D when RW='0' and AS='0' and lancp ='1'
else (others => 'Z'); else (others => 'Z');
@@ -468,7 +500,7 @@ begin
IDE_CS(1)<= not(A(13)); IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9); IDE_A(2 downto 0) <= A(11 downto 9);
ROM_B <= "00"; ROM_B <= "00";
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1'; ROM_OE <= ROM_OE_S when AS='0' else '1';
-- INT_OUT <= 'Z'; -- INT_OUT <= 'Z';
INT2_OUT <= '0' when INT2_OUT <= '0' when
@@ -484,15 +516,11 @@ begin
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1'; SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1'; CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
-- OVR <= 'Z'; --OVR <= 'Z';
OVR <= '0' when ide='1' and AS='0' else 'Z'; OVR <= '0' when ide='1' and AS='0' else 'Z';
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or DTACK <= IDE_TERM when ide='1' and AS='0' else 'Z';
-- AUTOCONFIG_IN_PROGRES ='1' --DTACK <= 'Z';
-- else 'Z';
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
-- DTACK <= 'Z';
A <= (others => 'Z'); A <= (others => 'Z');
MTACK <= 'Z'; MTACK <= 'Z';
Logic/LAN_IDE_V2/LAN_IDE_CP-z2v2.jed
+1466 -1466
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP-z3v2.jed
+1527 -1527
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.jed
-1750
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.vhd
+11 -10
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@@ -184,14 +184,14 @@ begin
clock_init: process(reset,CLK_EXT) clock_init: process(reset,CLK_EXT)
begin begin
if(reset='1')then if(reset='0')then
--default values --default values
LAN_CS_RST<='0'; LAN_CS_RST<='0';
LAN_WR_RST<='0'; LAN_WR_RST<='0';
LAN_RST_SM<=nop; LAN_RST_SM<=nop;
LAN_A_INIT<="11"&x"FFF"; LAN_A_INIT<="11"&x"FFF";
LAN_D_INIT<= x"0000"; LAN_D_INIT<= x"0000";
elsif(rising_edge(CLK_EXT))then --reset is low! elsif(rising_edge(CLK_EXT))then --reset is high!
case LAN_RST_SM is case LAN_RST_SM is
when nop=> when nop=>
LAN_CS_RST<='0'; LAN_CS_RST<='0';
@@ -281,13 +281,13 @@ begin
end if; end if;
end process ADDRESS_Z3_DECODE; end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(AS,reset) ADDRESS_Z2_DECODE: process(AMIGA_CLK,reset)
begin begin
if(reset='0' )then if(reset='0' )then
AUTOCONFIG_Z2_ACCESS <= '0'; AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0'; IDE_ACCESS <= '0';
CP_ACCESS <= '0'; CP_ACCESS <= '0';
elsif(falling_edge(AS))then elsif(rising_edge(AMIGA_CLK))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0' and LAN_ACCESS = '0')then if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0' and LAN_ACCESS = '0')then
AUTOCONFIG_Z2_ACCESS <= '1'; AUTOCONFIG_Z2_ACCESS <= '1';
else else
@@ -618,7 +618,7 @@ begin
-- LAN_CFG <= "ZZZZ"; -- LAN_CFG <= "ZZZZ";
A_LAN(13 downto 0)<= LAN_A_INIT(13 downto 0) when reset ='0' else A_LAN(13 downto 0)<= LAN_A_INIT(13 downto 0) when LAN_RST_SM/=done else
Z3_ADR(14 downto 2) & Z3_A_LOW when LAN_ACCESS = '1' else Z3_ADR(14 downto 2) & Z3_A_LOW when LAN_ACCESS = '1' else
A(12 downto 1)&"00"; A(12 downto 1)&"00";
@@ -635,7 +635,7 @@ begin
A(7 downto 1) <= (others => 'Z'); A(7 downto 1) <= (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses --defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when reset='0' else DQ <= LAN_D_INIT when LAN_RST_SM/=done else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D when RW='0' and AS='0' and CP_ACCESS ='1' else D when RW='0' and AS='0' and CP_ACCESS ='1' else
D when RW='0' and AS='0' and IDE_ACCESS ='1' else D when RW='0' and AS='0' and IDE_ACCESS ='1' else
@@ -669,20 +669,21 @@ begin
IDE_ENABLE <= '1'; IDE_ENABLE <= '1';
IDE_R_S <= '1'; IDE_R_S <= '1';
IDE_W_S <= '1'; IDE_W_S <= '1';
ROM_OE_S <= '1'; ROM_OE_S <= '1';
elsif rising_edge(CLK_EXT) then elsif rising_edge(CLK_EXT) then
--default values --default values
IDE_R_S <= '1'; IDE_R_S <= '1';
IDE_W_S <= '1'; IDE_W_S <= '1';
ROM_OE_S <= '1'; ROM_OE_S <= '1';
if(IDE_ACCESS='1' and AS='0' and DS='0')then if(IDE_ACCESS='1' and AS='0' and DS='0')then
if(RW='0')then if(RW='0')then
--the write goes to the hdd! --the write goes to the hdd!
IDE_ENABLE <= '0'; -- enable IDE on first read IDE_ENABLE <= '0'; -- enable IDE on first read
IDE_W_S <= '0'; IDE_W_S <= '0';
elsif(IDE_ENABLE ='1')then
ROM_OE_S <='0';
else else
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM IDE_R_S <= '0'; --read from IDE instead from ROM
ROM_OE_S <= not IDE_ENABLE;
end if; end if;
end if; end if;
end if; end if;
Logic/LAN_IDE_V2/LAN_IDE_CP_V2.zip
BIN
View File
Binary file not shown.
Logic/LAN_IDE_V2/LAN_IDEz2v2.gise
+19 -18
View File
@@ -38,6 +38,7 @@
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tim"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tspec"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tspec"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/>
@@ -67,12 +68,10 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1545595558" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1235887333676579674" xil_pn:start_ts="1545595546"> <transform xil_pn:end_ts="1602193494" xil_pn:in_ck="-8368315473908605201" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5742752562858310575" xil_pn:start_ts="1602193490">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<outfile xil_pn:name="LAN_IDE_CP.lso"/> <outfile xil_pn:name="LAN_IDE_CP.lso"/>
<outfile xil_pn:name="LAN_IDE_CP.ngc"/> <outfile xil_pn:name="LAN_IDE_CP.ngc"/>
<outfile xil_pn:name="LAN_IDE_CP.ngr"/> <outfile xil_pn:name="LAN_IDE_CP.ngr"/>
@@ -86,32 +85,30 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1545079613" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1545079613"> <transform xil_pn:end_ts="1602102352" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1602102352">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1545595565" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1545595558"> <transform xil_pn:end_ts="1602193498" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1602193494">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/> <outfile xil_pn:name="LAN_IDE_CP.bld"/>
<outfile xil_pn:name="LAN_IDE_CP.ngd"/> <outfile xil_pn:name="LAN_IDE_CP.ngd"/>
<outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/> <outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1545595609" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1545595565"> <transform xil_pn:end_ts="1602193522" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-9118991997326562509" xil_pn:start_ts="1602193498">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="LAN_IDE_CP.gyd"/> <outfile xil_pn:name="LAN_IDE_CP.gyd"/>
<outfile xil_pn:name="LAN_IDE_CP.mfd"/> <outfile xil_pn:name="LAN_IDE_CP.mfd"/>
<outfile xil_pn:name="LAN_IDE_CP.nga"/> <outfile xil_pn:name="LAN_IDE_CP.nga"/>
<outfile xil_pn:name="LAN_IDE_CP.pad"/> <outfile xil_pn:name="LAN_IDE_CP.pad"/>
<outfile xil_pn:name="LAN_IDE_CP.pnx"/> <outfile xil_pn:name="LAN_IDE_CP.pnx"/>
<outfile xil_pn:name="LAN_IDE_CP.rpt"/> <outfile xil_pn:name="LAN_IDE_CP.rpt"/>
<outfile xil_pn:name="LAN_IDE_CP.tim"/>
<outfile xil_pn:name="LAN_IDE_CP.tspec"/> <outfile xil_pn:name="LAN_IDE_CP.tspec"/>
<outfile xil_pn:name="LAN_IDE_CP.vm6"/> <outfile xil_pn:name="LAN_IDE_CP.vm6"/>
<outfile xil_pn:name="LAN_IDE_CP.xml"/> <outfile xil_pn:name="LAN_IDE_CP.xml"/>
@@ -119,30 +116,34 @@
<outfile xil_pn:name="LAN_IDE_CP_html"/> <outfile xil_pn:name="LAN_IDE_CP_html"/>
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/> <outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
</transform> </transform>
<transform xil_pn:end_ts="1545595612" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1545595609"> <transform xil_pn:end_ts="1602195303" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1602195301">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForOutputs"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1545129218" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1545129218"> <transform xil_pn:end_ts="1602023829" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1602023829">
<status xil_pn:value="AbortedRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/> <status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1545595676" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_configureTargetDevice_CPLD" xil_pn:prop_ck="-154879694275837835" xil_pn:start_ts="1545595673"> <transform xil_pn:end_ts="1545595676" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_configureTargetDevice_CPLD" xil_pn:prop_ck="-154879694275837835" xil_pn:start_ts="1545595673">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:name="TRAN_timRpt"> <transform xil_pn:name="TRAN_timRpt">
<status xil_pn:value="AbortedRun"/> <status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/> <status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
</transform> </transform>
Logic/LAN_IDE_V2/LAN_IDEz2v2.xise
+6 -6
View File
@@ -44,7 +44,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/> <property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/> <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="50" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Compact" xil_pn:valueState="non-default" xil_pn:x_locked="true"/> <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -81,7 +81,7 @@
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/> <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
@@ -111,8 +111,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/> <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/> <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -155,7 +155,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE_V2/LAN_IDEz3v2.gise
+10 -6
View File
@@ -68,7 +68,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1574202935" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5742752562858310575" xil_pn:start_ts="1574202924"> <transform xil_pn:end_ts="1602195170" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5742752562858310575" xil_pn:start_ts="1602195165">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -89,7 +89,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1574202943" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1574202935"> <transform xil_pn:end_ts="1602195174" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1602195170">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/> <outfile xil_pn:name="LAN_IDE_CP.bld"/>
@@ -98,7 +98,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1574202972" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1574202943"> <transform xil_pn:end_ts="1602195212" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1602195174">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -116,16 +116,20 @@
<outfile xil_pn:name="LAN_IDE_CP_html"/> <outfile xil_pn:name="LAN_IDE_CP_html"/>
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/> <outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
</transform> </transform>
<transform xil_pn:end_ts="1574202975" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1574202972"> <transform xil_pn:end_ts="1602195214" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1602195212">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1574196319" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1574196319"> <transform xil_pn:end_ts="1574196319" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1574196319">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1558897401" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1558897398"> <transform xil_pn:end_ts="1558897401" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1558897398">
<status xil_pn:value="AbortedRun"/> <status xil_pn:value="AbortedRun"/>
Logic/LAN_IDE_V2/LAN_IDEz3v2_ise12migration.zip
BIN
View File
Binary file not shown.
Logic/LAN_IDE_V2/pinlist.ucf
+1 -3
View File
@@ -74,11 +74,9 @@ NET "DQ<14>" LOC = "P131" ;
NET "DQ<15>" LOC = "P112" ; NET "DQ<15>" LOC = "P112" ;
NET "DQ<1>" LOC = "P117" ; NET "DQ<1>" LOC = "P117" ;
NET "DQ<2>" LOC = "P120" ; NET "DQ<2>" LOC = "P120" ;
//NET "DQ<2>" LOC = "P68" ; //fix for broken Xilinx
NET "DQ<3>" LOC = "P119" ; NET "DQ<3>" LOC = "P119" ;
NET "DQ<4>" LOC = "P124" ; NET "DQ<4>" LOC = "P124" ;
NET "DQ<5>" LOC = "P121" ; NET "DQ<5>" LOC = "P121" ;
//NET "DQ<5>" LOC = "P38" ;//fix for broken Xilinx
NET "DQ<6>" LOC = "P126" ; NET "DQ<6>" LOC = "P126" ;
NET "DQ<7>" LOC = "P125" ; NET "DQ<7>" LOC = "P125" ;
NET "DQ<8>" LOC = "P128" ; NET "DQ<8>" LOC = "P128" ;
@@ -112,7 +110,7 @@ NET "MTCR" LOC = "P101" ;
NET "OVR" LOC = "P100" ; NET "OVR" LOC = "P100" ;
NET "OWN" LOC = "P107" ; NET "OWN" LOC = "P107" ;
NET "RESET" LOC = "P143" ; NET "RESET" LOC = "P143" ;
NET "ROM_B<0>" LOC = "P68" ;//comment if fix for broken Xilinx! NET "ROM_B<0>" LOC = "P68" ;
NET "ROM_B<1>" LOC = "P69" ; NET "ROM_B<1>" LOC = "P69" ;
NET "ROM_OE" LOC = "P35" ; NET "ROM_OE" LOC = "P35" ;
NET "RW" LOC = "P83" ; NET "RW" LOC = "P83" ;
PCB/ZORRO-LAN-IDE-CP-V2F.brd
+1 -1
View File
@@ -8092,7 +8092,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
<wire x1="73.457221875" y1="66.142675" x2="73.457221875" y2="65.561984375" width="0.254" layer="1"/> <wire x1="73.457221875" y1="66.142675" x2="73.457221875" y2="65.561984375" width="0.254" layer="1"/>
<wire x1="73.457221875" y1="65.561984375" x2="73.992221875" y2="65.026984375" width="0.254" layer="1"/> <wire x1="73.457221875" y1="65.561984375" x2="73.992221875" y2="65.026984375" width="0.254" layer="1"/>
</signal> </signal>
<signal name="AUTO_BOOT_OFF"> <signal name="IDE_OFF">
<contactref element="IDE_OFF" pad="2"/> <contactref element="IDE_OFF" pad="2"/>
<contactref element="R5" pad="2"/> <contactref element="R5" pad="2"/>
<contactref element="IC2" pad="75"/> <contactref element="IC2" pad="75"/>
PCB/ZORRO-LAN-IDE-CP-V2F.sch
+49 -43
View File
@@ -8,34 +8,34 @@
</settings> </settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> <grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers> <layers>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/> <layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
<layer number="2" name="Route2" color="1" fill="3" visible="yes" active="no"/> <layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
<layer number="3" name="Route3" color="4" fill="3" visible="yes" active="no"/> <layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/>
<layer number="4" name="Route4" color="1" fill="4" visible="yes" active="no"/> <layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/>
<layer number="5" name="Route5" color="4" fill="4" visible="yes" active="no"/> <layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/>
<layer number="6" name="Route6" color="1" fill="8" visible="yes" active="no"/> <layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/>
<layer number="7" name="Route7" color="4" fill="8" visible="yes" active="no"/> <layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/>
<layer number="8" name="Route8" color="1" fill="2" visible="yes" active="no"/> <layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/>
<layer number="9" name="Route9" color="4" fill="2" visible="yes" active="no"/> <layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/>
<layer number="10" name="Route10" color="1" fill="7" visible="yes" active="no"/> <layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/>
<layer number="11" name="Route11" color="4" fill="7" visible="yes" active="no"/> <layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/>
<layer number="12" name="Route12" color="1" fill="5" visible="yes" active="no"/> <layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/>
<layer number="13" name="Route13" color="4" fill="5" visible="yes" active="no"/> <layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/>
<layer number="14" name="Route14" color="1" fill="6" visible="yes" active="no"/> <layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/>
<layer number="15" name="Route15" color="4" fill="6" visible="yes" active="no"/> <layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/> <layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/> <layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/> <layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/> <layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/> <layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/> <layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/> <layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/> <layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/> <layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="no"/> <layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="no"/> <layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="no"/> <layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="no"/> <layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/> <layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/> <layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/> <layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
@@ -44,8 +44,8 @@
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/> <layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/> <layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/> <layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
<layer number="37" name="tTest" color="7" fill="1" visible="yes" active="no"/> <layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
<layer number="38" name="bTest" color="7" fill="1" visible="yes" active="no"/> <layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/> <layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/> <layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/> <layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
@@ -53,16 +53,16 @@
<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/> <layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/> <layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/> <layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
<layer number="46" name="Milling" color="3" fill="1" visible="yes" active="no"/> <layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="no"/> <layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="no"/> <layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="no"/> <layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="no"/> <layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="no"/> <layer number="51" name="tDocu" color="7" fill="1" visible="no" active="no"/>
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="no"/> <layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="no"/> <layer number="53" name="tGND_GNDA" color="7" fill="1" visible="no" active="no"/>
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="no"/> <layer number="54" name="bGND_GNDA" color="7" fill="1" visible="no" active="no"/>
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="no"/> <layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/> <layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/> <layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/> <layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
@@ -15008,11 +15008,15 @@ Low profile connectors, straight&lt;p&gt;
<label x="129.54" y="119.38" size="1.27" layer="95" rot="R180"/> <label x="129.54" y="119.38" size="1.27" layer="95" rot="R180"/>
</segment> </segment>
</net> </net>
<net name="AUTO_BOOT_OFF" class="0"> <net name="IDE_OFF" class="0">
<segment> <segment>
<pinref part="IDE_OFF" gate="A" pin="2"/> <pinref part="IDE_OFF" gate="A" pin="2"/>
<pinref part="R5" gate="G$1" pin="2"/> <pinref part="R5" gate="G$1" pin="2"/>
<wire x1="119.38" y1="121.92" x2="119.38" y2="119.38" width="0.1524" layer="91"/> <wire x1="119.38" y1="121.92" x2="119.38" y2="119.38" width="0.1524" layer="91"/>
<label x="124.46" y="111.76" size="1.778" layer="95" rot="R270"/>
<wire x1="119.38" y1="119.38" x2="124.46" y2="119.38" width="0.1524" layer="91"/>
<wire x1="124.46" y1="119.38" x2="124.46" y2="111.76" width="0.1524" layer="91"/>
<junction x="119.38" y="119.38"/>
</segment> </segment>
</net> </net>
<net name="N$42" class="0"> <net name="N$42" class="0">
@@ -15408,7 +15412,9 @@ Low profile connectors, straight&lt;p&gt;
<pinref part="R1" gate="G$1" pin="2"/> <pinref part="R1" gate="G$1" pin="2"/>
<pinref part="AUTOBOOT_ON" gate="A" pin="2"/> <pinref part="AUTOBOOT_ON" gate="A" pin="2"/>
<wire x1="119.38" y1="81.28" x2="119.38" y2="83.82" width="0.1524" layer="91"/> <wire x1="119.38" y1="81.28" x2="119.38" y2="83.82" width="0.1524" layer="91"/>
<label x="119.38" y="81.28" size="1.778" layer="95"/> <label x="127" y="81.28" size="1.778" layer="95"/>
<wire x1="119.38" y1="81.28" x2="127" y2="81.28" width="0.1524" layer="91"/>
<junction x="119.38" y="81.28"/>
</segment> </segment>
</net> </net>
<net name="DOE" class="0"> <net name="DOE" class="0">
@@ -16298,7 +16304,7 @@ Low profile connectors, straight&lt;p&gt;
<label x="147.32" y="45.72" size="1.27" layer="95"/> <label x="147.32" y="45.72" size="1.27" layer="95"/>
</segment> </segment>
</net> </net>
<net name="AUTO_BOOT_OFF" class="0"> <net name="IDE_OFF" class="0">
<segment> <segment>
<pinref part="IC2" gate="G$1" pin="P$75-FB13MC11"/> <pinref part="IC2" gate="G$1" pin="P$75-FB13MC11"/>
<wire x1="144.78" y1="48.26" x2="147.32" y2="48.26" width="0.1524" layer="91"/> <wire x1="144.78" y1="48.26" x2="147.32" y2="48.26" width="0.1524" layer="91"/>