try for CP in Z3

This commit is contained in:
MHeinrichs
2019-02-26 21:59:05 +01:00
parent 6d4a455d68
commit 8230e4fca2
30 changed files with 14764 additions and 8030 deletions
+4 -2
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Feb 21 23:42:19 2019">
<application name="pn" timeStamp="Sun Feb 24 15:21:25 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -18,7 +18,9 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthFsmEncode" value="One-Hot" type="process"/>
<property name="PROP_SynthCaseImplStyle" value="Full" type="process"/>
<property name="PROP_SynthFsmEncode" value="Johnson" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>