Dominick.Vansevenant/Zorro-LAN-IDE
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

try for CP in Z3

Browse Source
This commit is contained in:
MHeinrichs
2019-02-26 21:59:05 +01:00
parent 6d4a455d68
commit 8230e4fca2
30 changed files with 14764 additions and 8030 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE/LAN_IDE_CP.vhd
+225 -225
View File
@@ -107,8 +107,10 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
config_rw
wait_cycle_end,
config_rw,
cp_read,
cp_write_wait
);
signal LAN_RST_SM: lan_reset :=nop;
@@ -122,7 +124,7 @@ architecture Behavioral of LAN_IDE_CP is
signal ROM_OE_S: STD_LOGIC;
signal CP_ACCESS: STD_LOGIC;
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
signal LAN_ACCESS: STD_LOGIC;
signal DQ_SWAP: STD_LOGIC;
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
@@ -148,6 +150,7 @@ architecture Behavioral of LAN_IDE_CP is
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal CP_WAIT:STD_LOGIC_VECTOR(3 downto 0);
signal AMIGA_CLK:STD_LOGIC;
signal DS:STD_LOGIC;
@@ -246,9 +249,9 @@ begin
if(--AS ='0' or
reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
Z3_ADR <= (others => '1');
CP_ACCESS <= '0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
@@ -266,8 +269,16 @@ begin
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
end if;
--CP base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
end if;
end process ADDRESS_Z3_DECODE;
@@ -277,7 +288,7 @@ begin
reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
elsif(falling_edge(AS))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
@@ -286,12 +297,7 @@ begin
AUTOCONFIG_Z2_ACCESS <= '0';
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
@@ -303,187 +309,7 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
if( LAN_INT ='1' --or --no interupt
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
)then
LAN_IRQ_OUT <='1';
elsif(
(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
) then
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
end if;
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,FCS,reset,Z3_DS,LAN_ACCESS,BERR )
begin
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
end case;
end if;
end process lan_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
begin
@@ -493,7 +319,7 @@ begin
D_Z2_OUT<="1111";
SHUT_UP_Z2 <="111";
IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
CP_BASEADR<=x"FFFF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
@@ -506,7 +332,7 @@ begin
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
else
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
@@ -565,8 +391,10 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
if(AUTO_CONFIG_Z2_DONE(0) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
CP_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
when "100100" =>
@@ -602,8 +430,204 @@ begin
end if;
end if;
end process autoconfig_proc; --- that's all
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,FCS,reset,Z3_DS,LAN_ACCESS,BERR,CP_ACCESS )
begin
if(reset = '0') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
CP_WAIT <="0000";
CP_RD_S <= '1';
CP_WE_S <= '1';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
CP_RD_S <= '1';
CP_WE_S <= '1';
-- delay for clockport
if(CP_ACCESS = '1') then
CP_WAIT <= CP_WAIT+1;
else
CP_WAIT <="0000";
end if;
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(LAN_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
elsif(CP_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(RW='1') then
CP_RD_S <= '0';
LAN_SM <= cp_read;
else
CP_WE_S <= '0';
LAN_SM <= cp_write_wait;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
if(FCS ='0')then
LAN_SM<=wait_cycle_end; -- stay here until cylce end
else
LAN_SM <= nop;
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=wait_cycle_end;
when cp_read=>
CP_RD_S <= '0';
Z3_DATA(31 downto 0) <= DQ & DQ; -- bus mirroring
if(CP_WAIT(3) = '1') then --wait enough for CP-read
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
else
LAN_SM<=cp_read; -- stay here until cp is ready
end if;
when cp_write_wait=>
CP_WE_S <= '0';
if(CP_WAIT(3) = '1') then --wait enough for CP-write
LAN_READY <='1';
LAN_SM<= wait_cycle_end; --deassert CP_W
else
LAN_SM<=cp_write_wait;
end if;
end case;
end if;
end process lan_rw_gen;
--for the future
CP_WE <= CP_WE_S when FCS='0' else '1';
CP_RD <= CP_RD_S when FCS='0' else '1';
CP_CS <= not CP_ACCESS;
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
@@ -623,9 +647,8 @@ begin
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
@@ -635,15 +658,10 @@ begin
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when reset='0' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D when RW='0' and AS='0' and CP_ACCESS ='1' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and (LAN_ACCESS ='1' or CP_ACCESS='1') else
(others => 'Z');
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
INT2_OUT <= '0' when LAN_INT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
@@ -695,25 +713,7 @@ begin
ROM_B <= "00";
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
end Behavioral;