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CP and LAN working! Clockport needed to be stopped if FCS='1'

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This commit is contained in:
MHeinrichs
2019-03-07 23:53:52 +01:00
parent 943507175a
commit 7936ad431b
161 changed files with 45433 additions and 43327 deletions
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.gitignore
+6
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@@ -112,3 +112,9 @@ Driver/baxnet/source/vasm\.exe
Driver/baxnet/source/Makefile
Driver/baxnet/source/vc\.cfg
Logic/LAN_IDE_V2/LAN_IDE_CP_html/fit/
Logic/LAN_IDE_V2/LAN_IDE_CP_html/images/
Logic/LAN_IDE_V2/LAN_IDE_CP_html/tim/
Driver/baxnet/README.miitool
+94
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@@ -0,0 +1,94 @@
MIITool
-------
This utility allows to observe and change the physical parameters
of Ethernet NICs on AmigaOS. The parameters include autonegotiation
settings and forced speed/duplex combinations. While it is expected
that autonegotiation "just works" with modern equipment, there still
are people with some interest in retro-computing who might or might
not experience link-related problems or are just curious about some
inner workings of everyday hardware.
A modern switch ("link partner") should advertise it`s capabilities
properly such that the Ethernet hardware can select the optimal mode
out of the supported set. If that is not the case, you can narrow down
the list of advertised modes such that the link partners come to a
working agreement. The last resort is to set a fixed speed/duplex
combination. Please note that fixed parameters must be set at both
ends of the link. Otherwise the link will work slowly or not at all.
None of the settings this tool applies is permanent. Changed parameters
are only valid until a reboot of the NIC.
Examples for usage are given at the end of this text.
Prerequisites:
- AmigaOS 2.04 on 68k
- active Ethernet SANA-II driver, i.e. after starting the IP-Stack
Invocation:
- MIITool is supposed to be run from CLI/Shell.
Arguments template:
DEVICE/K,UNIT/K/N,V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG/S,RESET/S,VV/S
Detailed description of arguments:
keyword - description
------------------------
DEVICE/K - device name corresponding to active ethernet interface
DEV/K example: DEVICE=enc624j6net.device
UNIT/K/N - unit number of device to be opened (default: 0)
example: UNIT=0
FORCEMEDIA - speed/duplex combination to set unconditionally,
see below for a list of valid speed or duplex modes
ADVERTISE - speed/duplex combinations to announce by autonegotiation,
implicitly restart autonegotiation,
see below for a list of valid speed or duplex modes
RENEG - restart autonegotiation, please allow a couple of seconds
RESTART until the negotiation is finished
RESET - reset PHY to power-on state
VERBOSE - more detailed outputs
V
VERYVERBOSE- even more detailed outputs
VV
Valid Speed/Duplex combinations (not case sensitive):
10baseT-HD - 10 Mbit/s half duplex
10baseT-FD - 10 Mbit/s full duplex
100baseTx-HD - 100 Mbit/s half duplex over two wire pairs
100baseTx-FD - 100 Mbit/s full duplex over two wire pairs (common)
100baseT4 - 100 Mbit/s full duplex over 4 wire pairs (rare)
10baseT - 10 Mbit/s half or full duplex
10bT - 10 Mbit/s half or full duplex
100baseTx - 100 Mbit/s half or full duplex
100bTx - 100 Mbit/s half or full duplex
Examples:
current status (detailed):
miitool DEV=enc624j6net.device v
negotiate 10 Mbit/s only
miitool DEV=enc624j6net.device ADVERTISE=10bT
negotiate 100baseTx and 10baseT half duplex only:
miitool DEV=enc624j6net.device ADVERTISE=100bTx,10baseT-HD
force 100 Mbit/s full duplex
miitool DEV=enc624j6net.device FORCEMEDIA=100baseTx-FD
Driver/baxnet/bin/enc624j6net.device
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Driver/baxnet/bin/enc624j6net.device.zip
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Driver/baxnet/bin/enc624j6net.device_68000
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Driver/baxnet/bin/miitool
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Driver/baxnet/bin/vwiznet500ex.device
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Driver/baxnet/bin/vwiznet600sd.device
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Driver/baxnet/enc624j6net.device
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Driver/baxnet/source/Makefile.enc
+2 -2
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@@ -23,7 +23,7 @@
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
SUBDIR=enc624j6net
ASMOBJECTS = $(SUBDIR)/enc624j6l.o $(SUBDIR)/intervaltimer.o
ASMOBJECTS = $(SUBDIR)/enc624j6l.o $(SUBDIR)/intervaltimer.o kprintf.o
###############################################################################
# Devices to build (1 or 2, keep DEVICEID2 empty if only one build is desired)
@@ -31,7 +31,7 @@ ASMOBJECTS = $(SUBDIR)/enc624j6l.o $(SUBDIR)/intervaltimer.o
###############################################################################
DEVICEID=enc624j6net.device
DEFINES = # -DPROTO_V2EXPNET
DEFINES = -DHW_DMA_TX # -DPROTO_V2EXPNET
ASMDEFS = # -DPROTO_V2EXPNET
CPU = 68020
Driver/baxnet/source/debug.i
+188
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@@ -0,0 +1,188 @@
;APS00000000000000000000000000000000000000000000000000000000000000000000000000000000
; ifd DEBUG
; XDEF _AbsExecBase
; XDEF _LVORawDoFmt
; XDEF _LVORawPutChar
; XDEF _LVORawMayGetChar
; XDEF _AbsExecBase
; endif
ifnd _LVORawDoFmt
_LVORawDoFmt equ -$20a
endc
ifnd _LVORawPutChar
_LVORawPutChar equ -$204
_LVORawIOInit equ -$1f8
_LVORawMayGetChar equ -$1fe
endc
;
;
;
ifd DEBUG
XREF _KPrintF
WRITEDEBUG macro
movem.l d0/d1/a0/a1,-(sp)
ifnb \9
move.l \9,-(sp)
endif
ifnb \8
move.l \8,-(sp)
endif
ifnb \7
move.l \7,-(sp)
endif
ifnb \6
move.l \6,-(sp)
endif
ifnb \5
move.l \5,-(sp)
endif
ifnb \4
move.l \4,-(sp)
endif
ifnb \3
move.l \3,-(sp)
endif
ifnb \2
move.l \2,-(sp)
endif
lea.l (\1),a0
move.l sp,a1
jsr _KPrintF
ifnb \2
add.l #4,sp
endif
ifnb \3
add.l #4,sp
endif
ifnb \4
add.l #4,sp
endif
ifnb \5
add.l #4,sp
endif
ifnb \6
add.l #4,sp
endif
ifnb \7
add.l #4,sp
endif
ifnb \8
add.l #4,sp
endif
ifnb \9
add.l #4,sp
endif
movem.l (sp)+,d0/d1/a0/a1
endm
else
WRITEDEBUG macro
nop
endm
endc
;
;
;
WRITEOUT macro
movem.l d0/d1/d2/a0/a1/a6,-(sp)
ifnb \9
move.l \9,-(sp)
endif
ifnb \8
move.l \8,-(sp)
endif
ifnb \7
move.l \7,-(sp)
endif
ifnb \6
move.l \6,-(sp)
endif
ifnb \5
move.l \5,-(sp)
endif
ifnb \4
move.l \4,-(sp)
endif
ifnb \3
move.l \3,-(sp)
endif
ifnb \2
move.l \2,-(sp)
endif
ifd DEBUG
move.l \1,a0
move.l sp,a1
jsr _KPrintF
endif
move.l \1,d1
move.l sp,d2
movea.l DOSBase,a6
jsr _LVOVPrintf(a6)
ifnb \2
add.l #4,sp
endif
ifnb \3
add.l #4,sp
endif
ifnb \4
add.l #4,sp
endif
ifnb \5
add.l #4,sp
endif
ifnb \6
add.l #4,sp
endif
ifnb \7
add.l #4,sp
endif
ifnb \8
add.l #4,sp
endif
ifnb \9
add.l #4,sp
endif
movem.l (sp)+,d0/d1/d2/a0/a1/a6
endm
;COUNTERS only when DEBUG is on
ifd DEBUG
ifne DEBUG
DEBUG_COUNTERS EQU 1
endc
endc
ifd DEBUG_COUNTERS
COUNTER_INC macro
addq.l #1,\1
endm
else
COUNTER_INC macro
nop
endm
endc
; write usage of all emulated instructions if DEBUG is 1 to RAWIO (sushi/sashimi/serial)
ifd DEBUG
ifne DEBUG
HAVE_DEBUGINSTR EQU 1
DEBUGINSTR macro
ifnb \3
WRITEDEBUG \1,\2,\3
else
WRITEDEBUG \1,\2
endc
endm
endc
endc
ifnd HAVE_DEBUGINSTR
DEBUGINSTR macro
endm
endc
Driver/baxnet/source/device.c
+13
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@@ -18,6 +18,8 @@
in server.c as a separate process. Interrupts are forwarded
as signals to server.c as well (depending on target hardware).
S2_CONFIGINTERFACE worked more than once, it *must* only work once.
*/
#define DEVICE_MAIN
@@ -200,6 +202,12 @@ ASM SAVEDS LONG DevOpen( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
dbm->dbm_PacketFilter = (APTR)( GetTagData(S2_PacketFilter,0,
(struct TagItem *)ioreq->ios2_BufferManagement));
dbm->dbm_CopyFromBufferDMA = (BMCALL)((void (*)())(GetTagData(S2_DMACopyFromBuff32, 0,
(struct TagItem *)ioreq->ios2_BufferManagement)));
dbm->dbm_CopyToBufferDMA = (BMCALL)((void (*)())(GetTagData(S2_DMACopyToBuff32, 0,
(struct TagItem *)ioreq->ios2_BufferManagement)));
/* v1.95: disabled CopyToBuffer32 due to problems with MiamiDX */
/* v1.99: try identifying Miami */
/* MiamiDX requires byte count to be a multiple of 4 */
@@ -265,6 +273,8 @@ ASM SAVEDS LONG DevOpen( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
}
ioreq->ios2_Req.io_Message.mn_Node.ln_Type = NT_REPLYMSG;
D(("DevOpen return code %ld\n",ret));
return ret;
}
@@ -588,6 +598,8 @@ ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
{
struct IOStdReq *stdrq = (struct IOStdReq *)ioreq;
D(("NSCMD_DEVICEQUERY size %ld\n",(ULONG)stdrq->io_Length));
if( (!stdrq->io_Data) || (stdrq->io_Length < sizeof( NSDQueryAnswer ) ) )
{
ioreq->ios2_Req.io_Error = IOERR_BADLENGTH;
@@ -598,6 +610,7 @@ ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
stdrq->io_Actual = sizeof( NSDQueryAnswer );
ioreq->ios2_Req.io_Error = 0;
}
D(("NSCMD_DEVICEQUERY return %ld\n",(ULONG)ioreq->ios2_Req.io_Error));
}
break;
/* query contents may ask for live data: handle in server.c */
Driver/baxnet/source/device.h
+3 -1
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@@ -123,7 +123,7 @@ struct devbase {
};
typedef BOOL (* ASM BMCALL)( ASMR(a0) void * ASMREG(a0), ASMR(a1) void * ASMREG(a1), ASMR(d0) LONG ASMREG(d0) );
typedef LONG (* ASM BMCALL)( ASMR(a0) void * ASMREG(a0), ASMR(a1) void * ASMREG(a1), ASMR(d0) LONG ASMREG(d0) );
struct db_BufferManagement {
struct MinNode dbm_n;
@@ -131,6 +131,8 @@ struct db_BufferManagement {
BMCALL dbm_CopyToBuffer32;
BMCALL dbm_CopyFromBuffer;
BMCALL dbm_CopyToBuffer;
BMCALL dbm_CopyFromBufferDMA; /* this buffering method requires additional support from lowlevel HW implementation */
BMCALL dbm_CopyToBufferDMA; /* usage of this pointer requires additional checks */
APTR dbm_PacketFilter; /* this is actually a Hook */
ULONG dbm_ID;
};
Driver/baxnet/source/enc624j6net.device
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Driver/baxnet/source/enc624j6net.device_68000
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Driver/baxnet/source/enc624j6net/enc624j6l.asm
+188 -40
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@@ -1,3 +1,4 @@
;APS00000000000000000000000000000000000000000000000000000000000000000000000000000000
; ------------------------------------------------------------------------------
; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
; | Henryk Richter <henryk.richter@gmx.net> |
@@ -15,18 +16,23 @@
;
;
;TODO:
; - Pattern Matching, MC/MC filtering: Multicast,Broadcast,Unicast(self),MagicPacket,correct CRC,"not me" Unicast
; - Pattern Matching, MC filtering: Multicast,Broadcast,Unicast(self),MagicPacket,correct CRC,"not me" Unicast
; - _enc624j6l_RXReset -> won't recover from totally unresponsive chip (but exits gracefully)
; - RXSTART_INIT = $0c00 -> currently $2000 due to previous location bug
;
; enable debugging code block (comment/uncomment, see below)
;DEBUG EQU 1
incdir src:baxnet/trunk/source/
;Temp:Amiga/src/Zorro-LAN-IDE.git/Driver/enc624j6net/
include "enc624j6net/registers.i"
include "enc624j6net/macros.i"
include "debug.i"
include "hw.i"
; enable debugging code block
ifnd DEBUG
DEBUG EQU 0
endc
;
ADD_4RX EQU 1 ;add 4 to valid RX size (fake CRC), fixes shapeshifter RAW treatment
_OPT_LONGRESET EQU 0 ;in testing, don't enable
@@ -116,6 +122,9 @@ ENC_BOARDID EQU 123 ;ZII-IDE-LAN-CP
XDEF _enc624j6l_bc_mc_filter
XDEF _enc624j6l_ReadPHY
XDEF _enc624j6l_WritePHY
;
; System includes
;
@@ -250,9 +259,9 @@ opendos:
beq .noframe ;nothing received
;debug: disable recv
move.l _boardbase(pc),a0
moveq #ECON1_RXEN,d0
CLRREG ECON1,a0,d0
;move.l _boardbase(pc),a0
;moveq #ECON1_RXEN,d0
;CLRREG ECON1,a0,d0
move.l _boardbase(pc),a0
lea readframe,a1
@@ -791,7 +800,7 @@ _enc624j6l_EnableInterrupt:
move.w d0,($4000,a0)
lea -$4000(a0),a0
move #EIE_PKTIE|EIE_INTIE,d0
move #EIE_PKTIE|EIE_PCFULIE|EIE_INTIE,d0
SETREG EIE,a0,d0
moveq #1,d0
@@ -814,7 +823,7 @@ _enc624j6l_EnableInterrupt:
; Notes: assumes that init() was called before
;
_enc624j6l_EnableGlobalInterrupt:
move #EIE_INTIE,d0
move #EIE_PKTIE|EIE_PCFULIE|EIE_INTIE,d0 ; move #EIE_INTIE,d0
SETREG EIE,a0,d0
moveq #1,d0
.rts
@@ -896,35 +905,32 @@ _enc624j6l_DisableInterrupt:
; ULONG sigbit
;
_enc624j6l_IntServer_List:
move.l a6,-(sp)
move.l a1,d0 ;no pointer supplied ? -> return
beq.s .rts
beq.s .end
movem.l d1/A1/a6,-(sp)
move.l a1,a6
moveq #0,d1
.boardloop:
move.l (a1)+,d0 ;next entry from list
beq.s .done ;
move.l d0,a0 ;current board
move.l (A6)+,d0 ;read magic word
cmp.l #HW_MAGIC_WORD,D0 ; are we in the right structure?
bne.s .done
READREG EIR,a0,d0 ;get interrupt status reg
and #EIR_PKTIF,d0
or.l d0,d1
bra.s .boardloop
.boardloop:
move.l (A6)+,d0 ;next entry from list
beq.s .done ;
move.l d0,a1 ;current board
READREG EIR,A1,d0 ;get interrupt status reg
and #EIR_PKTIF|EIR_PCFULIF,D0
beq.s .boardloop ;no interrupt here
or.l d0,D1 ; save if at least one one board has interrupted
move #EIE_INTIE,D0 ;disable board interrupt until someone enables it again
CLRREG EIE,A1,d0
BRA.s .boardloop
.done:
tst.w d1
beq.s .rts
; clear EIE_INTIE in all active boards directly from here
.intdis_loop:
move.l (a6)+,d0
beq.s .boardsdone
move.l d0,a1
move #EIE_INTIE,D0 ;disable board interrupt until someone enables it again
CLRREG EIE,A1,d0
bra.s .intdis_loop
.boardsdone:
;faster: get from extended Driver board list instead from ZII/ZIII card
ifne 1
@@ -960,7 +966,8 @@ _enc624j6l_IntServer_List:
jsr _LVOSignal(a6)
.rts
move.l (sp)+,a6
movem.l (sp)+,D1/A1/A6
.end
moveq #0,d0 ;set Z flag
rts
@@ -1062,8 +1069,45 @@ _enc624j6l_CheckLinkChange:
; Notes: - Doesn't check for Board Pointer (!)
; - doesn't re-enable RX (!)
;
ifne DEBUG
RXReset_MSG: dc.b "RXReset Head %04lx Tail %04lx NextPacket %04lx ReadPTR %04lx Bytes %04lx",10,0
endc
_enc624j6l_RXReset:
ifne DEBUG
;print current HW registers to serial
movem.l d2-d7,-(sp)
moveq #0,d0
moveq #0,d1
moveq #0,d2
moveq #0,d3
READREG ERXHEAD,A0,d0
READREG ERXTAIL,A0,d1
READREG PNextPacket,a0,d2
READSRAM a0,d2,d3 ;move (a0,d7.w),d0
ifeq _OPT_BUFFER_SWAP
rol.w #8,d3 ;swap pointer to Big Endian
endc ;d3=next Packet (from receive status vector)
moveq #2,d5
add d2,d5 ;increment pointer by one word
WRAPINDEX d5 ;wrap D4 if beyond buffer
READSRAM a0,d5,d4 ;receive byte count
ifeq _OPT_BUFFER_SWAP
rol.w #8,d4 ;swap pointer to Big Endian
endc
WRITEDEBUG RXReset_MSG,d0,d1,d2,d3,d4
movem.l (sp)+,d2-d7
endc
moveq #ECON2_RXRST,d0 ;RX Reset, clears RXEN
SETREG ECON2,a0,d0 ;
;moveq #ECON1_RXEN,d0 ;done by RX reset
@@ -1171,6 +1215,15 @@ _enc624j6l_RecvFrame: ;
rol.w #8,d0 ;swap pointer to Big Endian
endc
; btst #0,d0
; beq.s .nozerobit
; nop
;.nozerobit
; btst #0,d7
; beq.s .nozerobit2
; nop
;.nozerobit2
;verify next packet pointer, re-initialize recv if this is invalid
cmp #RXSTOP_INIT,d0 ;bad pointer (<0 or >end of memory)
bhi.w .recv_err
@@ -1259,10 +1312,23 @@ _enc624j6l_RecvFrame: ;
lea (a0,d7.w),a2 ;read pointer
ifeq _OPT_BUFFER_SWAP
btst #1,d7 ;do we have a read address that`s not long aligned?
beq.s .no_impair
move.w (a2)+,(a1)+ ;long-align address
subq #2,d0
ble.w .end_read ;should not happen (>14 per valid frame)
moveq #15,d1 ;
move.l d0,d2 ;total bytes
and.l d0,d1 ;remainder: max 15 bytes
lsr.w #4,d2 ;total/16
addq #2,d0
bra.s .impair
.no_impair:
move.l d0,d2 ;total bytes
moveq #15,d1 ;
lsr.w #4,d2 ;total/16
and.l d0,d1 ;remainder: max 15 bytes
.impair:
addq #3,d1 ;remainder, rounded up to +3 bytes
subq #1,d2 ;dbf
blt.s .nopt16_read ;less than 16 bytes -> bail out
@@ -1424,7 +1490,7 @@ _enc624j6l_RecvFrame: ;
; notes:
;
_enc624j6l_TransmitFrame:
movem.l d2-d5/a2,-(sp)
movem.l d2-d5/a3,-(sp)
;---------------- parameter check -------------------------------------
@@ -1455,33 +1521,60 @@ _enc624j6l_TransmitFrame:
eor.w #PSwapTX,d2 ;swap buffer
WRITEREG PNextTX,a0,d2 ;remember pointer (d2 also for ETXST later)
lea (a0,d2.w),a2 ;write pointer for frame
lea (a0,d2.w),a3 ;write pointer for frame
ifeq _OPT_BUFFER_SWAP
ifd HW_DMA_TX
move.l a2,d3
beq.s .no_separate_header
ifne 1
move.l -2(a2),(a3)+ ;garbage (2), DstMAC,SrcMAC,Type/Len = 16 Bytes
move.l 2(a2),(a3)+
move.l 6(a2),(a3)+
move.l 10(a2),(a3)+
moveq #14,d3
addq #2,d2 ;start pointer behind garbage (2)
else
move.l (a2),(a3)+ ;copy DstMAC,SrcMAC,Type/Len = 14 Bytes
move.l 4(a2),(a3)+
move.l 8(a2),(a3)+
move.w 12(a2),(a3)+
moveq #14,d3
endc
.no_separate_header
endc
;faster TX when buffer swapping is not necessary
move.l d0,d4 ;remember length
moveq #63,d5 ;
and.l d5,d0 ;remainder of 64 byte copy loop
move.l d4,d5 ;length in bytes
ifd HW_DMA_TX
add.l d3,d4 ;length+header (either 0 or 14)
endc
asr.w #6,d5 ;64 byte blocks
subq.w #1,d5 ;dbf
blt.s .smallcopy
bra.s .largecopy_start
.largecopy:
move.l d1,(a2)+
move.l d1,(a3)+
.largecopy_start:
rept 15
move.l (a1)+,(a2)+ ;save to SRAM
move.l (a1)+,(a3)+ ;save to SRAM
endr
move.l (a1)+,d1
dbf d5,.largecopy
move.l d1,(a2)+
move.l d1,(a3)+
else ;_OPT_BUFFER_SWAP
ifd HW_DMA_TX
error "HW_DMA_TX not supported for _OPT_BUFFER_SWAP configuration, disable!"
endc
move.w d0,d4 ;still need length later
endc ;_OPT_BUFFER_SWAP
@@ -1507,11 +1600,11 @@ _enc624j6l_TransmitFrame:
rol.w d4,d3
swap d1
swap d3
move.l d1,(a2)+ ;save to SRAM
move.l d3,(a2)+ ;save to SRAM
move.l d1,(a3)+ ;save to SRAM
move.l d3,(a3)+ ;save to SRAM
else ;_OPT_BUFFER_SWAP
move.l (a1)+,(a2)+ ;save to SRAM
move.l (a1)+,(a2)+ ;save to SRAM
move.l (a1)+,(a3)+ ;save to SRAM
move.l (a1)+,(a3)+ ;save to SRAM
endc ;_OPT_BUFFER_SWAP
dbf d0,.txcopy
@@ -1546,7 +1639,7 @@ _enc624j6l_TransmitFrame:
SETREG ECON1,a0,d1 ;
.err:
movem.l (sp)+,d2-d5/a2
movem.l (sp)+,d2-d5/a3
rts
ifne _OPT_CHECKLINK_TX
@@ -1559,6 +1652,7 @@ _enc624j6l_TransmitFrame:
endc
;---------------------------------------------------------------------------------------
;
; read PHY register (16 Bit)
@@ -1613,6 +1707,60 @@ _enc624j6l_ReadPHY:
.err:
moveq #-1,d0
rts
;---------------------------------------------------------------------------------------
;
; write PHY register (16 Bit)
;
; input: A0 - APTR mmapped board base address
; D0 - LONG Phy register (5 valid bits)
; D1 - SHORT value written into PHY reg
;
; output: LONG D0 <0 - error (bad register index)
; - 16 Bit PHY reg contents
;
; trash: -
;
; notes:
;
;
_enc624j6l_WritePHY:
cmp.w #31,d0
bhi.w .err
bset #8,d0 ;$100 + PHY_REG
WRITEREG MIREGADR,a0,d0 ;set PHY register address
WRITEREG MIWR,a0,d1 ;set desired content
moveq #25,d0 ;25 us delay (at least)
bsr _enc624j6l_UMinDelay ;
moveq #100,d1
.waitloop:
READREG MISTAT,a0,d0
btst #0,d0
beq.s .notbusy
tst.b $BFE301 ;1 CIA access = 1.4 us
subq.w #1,d1 ;>165 us exceeded ? -> something is wrong, SPEC says 25.6 us
blt.s .notbusy ;error
bra.s .waitloop
.notbusy
; moveq #0,d0
; WRITEREG MICMD,a0,d0 ;cancel write command
moveq #0,d0
.ret:
rts
.err:
moveq #-1,d0
bra.s .ret
;------------------------------------------------------------------------------------------------
;------------------------------------------------------------------------------------------------
;
Driver/baxnet/source/enc624j6net/enc624j6l.h
+24 -3
View File
@@ -196,17 +196,23 @@ ASM SAVEDS int enc624j6l_RecvFrame( ASMR(a0) void *board ASMREG(a0),
input: board - mmapped board base address
buffer - output buffer (should have >=1514 bytes)
sendsize - size of buffer in bytes ( no CRC appended (!) )
header - 14 Bytes Ethernet header
(total frame transmit size = sendsize+14)
output: <0 - error
0 - nothing in receive buffer
>0 - size of received frame
notes:
"header" argument valid only when "HW_DMA_TX" is defined (Makefile)
*/
ASM SAVEDS int enc624j6l_TransmitFrame( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) unsigned char* buffer ASMREG(a1),
ASMR(d0) short sendsize ASMREG(d0) );
ASMR(d0) short sendsize ASMREG(d0)
#ifdef HW_DMA_TX
,ASMR(a2) unsigned char* header ASMREG(a2)
#endif
);
/*
@@ -330,7 +336,7 @@ ASM SAVEDS int enc624j6l_CheckLinkChange( ASMR(a0) void *board ASMREG(a0) );
Purpose: read PHY register
input: board - mmapped board base address
flags - broadcast,promiscous, multicast
phyreg - PHY register to read
output: <0 - error
>=0 - OK
@@ -340,5 +346,20 @@ ASM SAVEDS int enc624j6l_ReadPHY(
ASMR(d0) unsigned long phyreg ASMREG(d0) );
/*
Purpose: write PHY register
input: board - mmapped board base address
phyreg - PHY register to read
value - value written into PHY reg
output: <0 - error
>=0 - OK
*/
ASM SAVEDS int enc624j6l_WritePHY(
ASMR(a0) void *board ASMREG(a0),
ASMR(d0) unsigned long phyreg ASMREG(d0),
ASMR(d1) unsigned short data ASMREG(d1) );
#endif /* _INC_ENC624J6L_H */
Driver/baxnet/source/enc624j6net/hw.c
+58 -13
View File
@@ -51,10 +51,10 @@ void myhw_ControlIntervalTimer( DEVBASEP );
/* these calls might not run within the context of a process and
will be called from varying tasks and without prior init:
hw_Find_Boards()
hw_Find_Boards() - this one just identifies available HW and returns #boards
hw_AllocBoard()
hw_ReleaseBoard()
hw_GetMacAddress()
hw_GetMacAddress() - get default MAC address from board
these calls are in the context of the server task:
hw_Setup() - general init (board allocated already)
@@ -62,7 +62,7 @@ void myhw_ControlIntervalTimer( DEVBASEP );
hw_Attach() - make hardware ready for action (online)
hw_Detach() - put hardware into sleep mode (offline)
hw_recv_sigmask() - get signals for hardware (if any)
hw_recv_sigmask() - get signals for hardware (if any, i.e. signal on interrupt)
hw_recv_pending() - check for pending receive frames
hw_recv_frame() - receive one frame
@@ -71,10 +71,11 @@ void myhw_ControlIntervalTimer( DEVBASEP );
and apply them (called only when no RX/TX
in progress)
hw_config_init() - set defaults for HW
hw_config_update() - update config of HW
hw_ConfigInit() - set defaults for HW
hw_ConfigUpdate() - update config of HW
hw_get_mac_status() - running parameters
hw_change_multicast - re-initialize multicast filter for new address list
hw_get_mac_status() - running parameters (optional), S2_DEVICEQUERYEXT
*/
const BYTE exp_name[] = "expansion.library";
@@ -274,13 +275,31 @@ ASM SAVEDS void hw_ConfigUpdate( ASMR(a0) DEVBASEP ASMREG(a0),
hwd->multicast = 1;
}
/*
send a single frame to the hardware:
- either fully assembled frame (14 bytes DMAC,SMAC,TYPE followed by payload
- or payload in "frame" and 14 byte header in "header"
- provide Makefile-level definition of HW_DMA_TX in the latter case
- note: if you pass "header==NULL" with active HW_DMA_TX definition,
the hw_send_frame assumes the header to be present (SANA-II RAW frames) and
is handling "frame" as fully assembled frame
*/
ASM SAVEDS LONG hw_send_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1),
ASMR(d1) ULONG framesize ASMREG(d1) )
ASMR(d1) ULONG framesize ASMREG(d1)
#ifdef HW_DMA_TX
,ASMR(a2) UBYTE *header ASMREG(a2)
#endif
)
{
enc624j6l_TransmitFrame( db->db_Units[unit].duh_BASE, frame, framesize );
/* TX with separate header support ? (optional) */
enc624j6l_TransmitFrame( db->db_Units[unit].duh_BASE, frame, framesize
#ifdef HW_DMA_TX
,header
#endif
);
return 1;
}
@@ -329,7 +348,9 @@ ASM SAVEDS LONG hw_check_link_change( ASMR(a0) DEVBASEP ASMREG(
return 1; /* don't signal panic to the outside, everything is under control */
}
/* obtain running parameters of Ethernet MAC: link up/down, Speed, Duplex */
/* obtain running parameters of Ethernet MAC: link up/down, Speed, Duplex for
SANA-II DeviceQueryExtension (general parameters)
*/
ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
@@ -385,6 +406,30 @@ ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(
}
/* read PHY register */
ASM SAVEDS LONG hw_read_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
return enc624j6l_ReadPHY( boardbase, reg );
}
/* write PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1),
ASMR(d2) ULONG value ASMREG(d2) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
return enc624j6l_WritePHY( boardbase, reg, value );
}
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) struct List *mcastlist ASMREG(a1) )
@@ -404,8 +449,6 @@ ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(
enc624j6l_bc_mc_filter(boardbase, flags );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
return 1;
}
@@ -417,7 +460,9 @@ void myhw_ControlInterrupts( DEVBASEP )
ObtainSemaphore( &hwd->hwd_Sem ); /* redundant here: server is a single task -> but it looks good :-) */
flag = 0;
hwd->hwd_act_boards[0] = HW_MAGIC_WORD;
flag = 1;
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
@@ -431,7 +476,7 @@ void myhw_ControlInterrupts( DEVBASEP )
hwd->hwd_act_boards[flag+2] = (APTR)hwd->hwd_IntSig; /* append sigbit */
hwd->hwd_act_boards[flag+3] = (APTR)db->db_SysBase; /* append ExecBase *((APTR*)0x4); */
if( flag ) /* determine on/off switch */
if( flag>1 ) /* determine on/off switch */
{
/* at least 1 board is online */
if( hwd->hwd_Interrupt.is_Data )
Driver/baxnet/source/enc624j6net/hwprivate.h
+1 -1
View File
@@ -22,7 +22,7 @@
struct HWData {
struct Interrupt hwd_Interrupt; /* keep the interrupt at top of HWData !! */
struct SignalSemaphore hwd_Sem; /* list locking (global per unit) */
APTR hwd_act_boards[MAX_UNITS+1+3]; /* poll all active boards by ptr in interrupt, NULL terminated, followed by SigTask,Sigbit,ExecBase */
APTR hwd_act_boards[MAX_UNITS+1+3+1]; /* poll all active boards by ptr in interrupt, MAGIC_WORD INIT, NULL terminated, followed by SigTask,Sigbit,ExecBase */
ULONG hwd_SigMask; /* signal mask to wait for in server main instance */
Driver/baxnet/source/hw.h
+28 -2
View File
@@ -51,7 +51,7 @@ struct devbase;
#define HW_MACB_SPEEDS_END 18 /* this is the next free bit */
#define HW_MAC_SPEEDSMASK ((1<<HW_MACB_SPEEDS_END)-4)
#define HW_MAC_NEXTSPEED(_a_) ( (_a_)+2 )
#define HW_MAGIC_WORD 0xB00BDEED
@@ -94,10 +94,24 @@ ASM SAVEDS void hw_ConfigInit( ASMR(a0) DEVBASEP ASMREG(a0) )
ASM SAVEDS void hw_ConfigUpdate( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(a1) void * ASMREG(a1) );
/*
send a single frame to the hardware:
- either fully assembled frame (14 bytes DMAC,SMAC,TYPE followed by payload
- or payload in "frame" and 14 byte header in "header"
- provide Makefile-level definition of HW_DMA_TX in the latter case
- note: if you pass "header==NULL" with active HW_DMA_TX definition,
the hw_send_frame assumes the header to be present (SANA-II RAW frames) and
is handling "frame" as fully assembled frame
*/
ASM SAVEDS LONG hw_send_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1),
ASMR(d1) ULONG framesize ASMREG(d1) );
ASMR(d1) ULONG framesize ASMREG(d1)
#ifdef HW_DMA_TX
,ASMR(a2) UBYTE *header ASMREG(a2)
#endif
);
ASM SAVEDS LONG hw_recv_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
@@ -116,6 +130,18 @@ ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(
ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
/* read PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_read_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1) );
/* write PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1),
ASMR(d2) ULONG value ASMREG(d2) );
/* kept this global for now: Z-II/Z-III boards share the same interrupt */
ASM SAVEDS ULONG hw_recv_sigmask( ASMR(a0) DEVBASEP ASMREG(a0) );
Driver/baxnet/source/hw.i
+1 -1
View File
@@ -39,5 +39,5 @@ HW_MACB_SPEED5000 EQU 10
HW_MACB_SPEED10000 EQU 12 ; Am I optimistic ?
HW_MACB_SPEEDS_END EQU 14 ; this is the next free bit
HW_MAC_SPEEDSMASK EQU ((1<<HW_MACB_SPEEDS_END)-4)
HW_MAGIC_WORD EQU $B00BDEED
endc ;_INC_HW_I
Driver/baxnet/source/kprintf.asm
+44
View File
@@ -0,0 +1,44 @@
incdir include:
ifnd _LVOSupervisor
include exec/exec_lib.i
endc
include exec/execbase.i
ifnd _LVORawDoFmt
_LVORawDoFmt equ -$20a
endc
ifnd _LVORawPutChar
_LVORawPutChar equ -$204
_LVORawIOInit equ -$1f8
_LVORawMayGetChar equ -$1fe
endc
XDEF _KPrintF
;A0 = format
;A1 = arguments
_KPrintF:
ifd DEBUG
movem.l d0-d2/a0-a3/a6,-(sp)
move.l 4.w,a6
jsr _LVORawIOInit(a6) ;better safe than sorry
lea .kprintfproc(pc),a2
suba.l a3,a3 ;data pointer (0 here)
jsr _LVORawDoFmt(a6)
movem.l (sp)+,d0-d2/a0-a3/a6
rts
.kprintfproc:
movem.l d0/d1/a0/a1/a6,-(sp)
move.l 4.w,a6
jsr _LVORawPutChar(a6) ; move.b d0,(a3)+
movem.l (sp)+,d0/d1/a0/a1/a6
endc ;DEBUG
rts
Driver/baxnet/source/miitool.c
+661
View File
@@ -0,0 +1,661 @@
/*******************************************************************************************/
/** **/
/** miitool.c **/
/** SANA-II extension for access to Ethernet PHY registers over MII interface **/
/** **/
/** Copyright (c) 2019, Henryk Richter, Timm S. Müller **/
/** All rights reserved. **/
/** **/
/** Redistribution and use in source and binary forms, with or without **/
/** modification, are permitted provided that the following conditions are met: **/
/** 1. Redistributions of source code must retain the above copyright **/
/** notice, this list of conditions and the following disclaimer. **/
/** 2. Redistributions in binary form must reproduce the above copyright **/
/** notice, this list of conditions and the following disclaimer in the **/
/** documentation and/or other materials provided with the distribution. **/
/** 3. All advertising materials mentioning features or use of this software **/
/** must display the following acknowledgement: **/
/** This product includes software developed by Henryk Richter. **/
/** 4. Neither the name of the Henryk Richter nor the **/
/** names of its contributors may be used to endorse or promote products **/
/** derived from this software without specific prior written permission. **/
/** **/
/** THIS SOFTWARE IS PROVIDED BY Henryk Richter ''AS IS'' AND ANY **/
/** EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED **/
/** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE **/
/** DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY **/
/** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES **/
/** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; **/
/** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND **/
/** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **/
/** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS **/
/** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/
/** **/
/*******************************************************************************************/
/*
Notes:
- make sure you have an up-to-date devices/sana2devqueryext.h
- make sure you have devices/newstyle.h
- compilation
sc miitool.c link
*/
#include <proto/exec.h>
#include <proto/dos.h>
#include <proto/utility.h>
#include <devices/newstyle.h>
#include <devices/sana2.h>
#include <devices/sana2devqueryext.h>
#include "miitool.h"
#define OPT_TEMPLATE "DEVICE=DEV/K,UNIT/K/N,VERBOSE=V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG=RESTART/S,RESET/S,VERYVERBOSE=VV/S"
const char opt_template[] = OPT_TEMPLATE;
struct progopts {
BYTE *devname;
LONG *unit; /* unit to open */
ULONG verbose; /* verbose mode enabled */
BYTE *force; /* force media type */
BYTE *advertise; /* advertise specific types */
ULONG renegotiate; /* restart autonegotiation */
ULONG reset; /* reset MII */
ULONG vverbose; /* higher verbosity level */
};
struct prgdata {
struct MsgPort *sana2devport;
struct IOSana2Req *sana2devio;
struct Device *sana2dev;
UBYTE devvalid;
struct progopts opts;
};
void end_prog( struct prgdata *prg )
{
if( prg->sana2devio )
{
if( prg->devvalid )
CloseDevice( (struct IORequest *)prg->sana2devio );
DeleteIORequest( (struct IORequest *)prg->sana2devio );
}
if( prg->sana2devport )
DeleteMsgPort( prg->sana2devport );
}
/*
note: call this only once at program startup
*/
LONG start_prog( struct prgdata *prg )
{
SHORT i;
UBYTE *t = (UBYTE*)prg;
for( i=0 ; i < sizeof( struct prgdata ) ; i++ )
*t++ = 0;
prg->sana2devport = CreateMsgPort();
if( !prg->sana2devport )
goto err;
prg->sana2devio = (struct IOSana2Req *) CreateIORequest(
prg->sana2devport, sizeof(struct IOSana2Req));
if( !prg->sana2devio )
goto err;
return 1;
err:
end_prog( prg );
return 0;
}
void clr_device( struct prgdata *prg )
{
if( !prg->devvalid )
return;
prg->devvalid = 0;
CloseDevice( (struct IORequest *)prg->sana2devio );
}
LONG get_device(struct prgdata *prg, BYTE *name, LONG unit )
{
if( !name )
return 0;
if( prg->devvalid ) /* close previously opened device */
clr_device( prg );
prg->devvalid = OpenDevice(name,unit,(struct IORequest *)prg->sana2devio,0) == 0;
if( !prg->devvalid )
{
Printf( "Cannot open %s unit %ld\n",(ULONG)name,unit );
return 0;
}
return 1;
}
static BOOL findcmd(struct NSDeviceQueryResult *nsdqr, UWORD cmd)
{
UWORD *p;
for (p = nsdqr->SupportedCommands; (*p); ++p)
if (*p == cmd)
return TRUE;
return FALSE;
}
/*
verify NSD support, SANA-II type, Device Query extension on previously opened device
*/
LONG probe_device( struct prgdata *prg )
{
struct IOStdReq *stdreq;
struct NSDeviceQueryResult nsdqr;
if( !prg )
return 0;
if( !prg->devvalid )
return 0;
stdreq = (struct IOStdReq *)prg->sana2devio;
stdreq->io_Command = NSCMD_DEVICEQUERY;
stdreq->io_Flags = 0;
stdreq->io_Data = &nsdqr;
stdreq->io_Length = sizeof nsdqr;
if (DoIO((struct IORequest *) stdreq) != 0)
{
Printf("I/O error: no NewStyleDevice.\n");
return 0;
}
if (nsdqr.DeviceType != NSDEVTYPE_SANA2)
{
Printf("Device is not a SANA-II device (type %ld, needed %ld\n).", (LONG)nsdqr.DeviceType, (LONG) NSDEVTYPE_SANA2);
return 0;
}
if (!findcmd(&nsdqr, S2_DEVICEQUERYEXT))
{
Printf("Device does not support S2_DEVICEQUERYEXT.\n");
return 0;
}
return 1;
}
const struct {
BYTE *name;
UWORD namelen;
UWORD value;
} media[] = {
/* The order through 100baseT4 matches bits in the BMSR */
{ "10baseT-HD", 10,MII_AN_10BASET_HD },
{ "10baseT-FD", 10,MII_AN_10BASET_FD },
{ "100baseTx-HD", 12,MII_AN_100BASETX_HD },
{ "100baseTx-FD", 12,MII_AN_100BASETX_FD },
{ "100baseT4", 9,MII_AN_100BASET4 },
{ "100baseTx", 9,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
{ "10baseT", 7,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
{ "100bTx", 6,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
{ "10bT", 4,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
};
#define NMEDIA (sizeof(media)/sizeof(media[0]))
void dump_mii_media( USHORT par, BOOL bestonly )
{
LONG i;
par >>= 5; /* get upper bits */
for( i=4 ; i >= 0 ; i-- )
{
if( par & (1<<i) )
{
Printf(" ");
Printf("%s",(ULONG)media[i].name);
if( bestonly )
break;
}
}
if( par & (1<<5) )
Printf(" flow-control");
}
LONG parse_speedduplex( BYTE *parameters )
{
LONG i,res = 0;
BYTE *s;
if( !parameters )
return 0;
s = parameters;
while( *s != 0 )
{
for( i=0 ; i < NMEDIA ; i++ )
if( Strnicmp( media[i].name, s, media[i].namelen ) == 0 )
break;
if( i==NMEDIA )
goto err;
s += media[i].namelen;
res |= media[i].value;
/* skip " " and/or "," */
while( *s != 0 )
{
if( (*s==' ') || (*s==',') )
s++;
else
break;
}
}
return res;
err:
Printf("Invalid media specification %s\n",parameters);
Printf("Valid Arguments:\n");
for( i=0 ; i < NMEDIA ; i++ )
Printf("%s\n",media[i].name);
return -1;
}
/*
note: this code assumes that "mii" has the register contents in natural
byte ordering. Also, the registers themselves shall be consecutive
in memory.
*/
int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
{
USHORT bmcr,bmsr,advert,curlink;
LONG i;
bmcr = mii[MII_BMCR].Content;
bmsr = mii[MII_BMSR].Content;
advert = mii[MII_ANAR].Content;
curlink = mii[MII_ANLPAR].Content;
if( bmcr == 0xffff )
{
Printf("No MII transceiver found\n");
return 0;
}
if( bmcr & MII_BMCR_AN_ENA)
{
if( bmsr & MII_BMSR_AN_COMPLETE)
{
if( advert & curlink )
{
if( curlink & MII_AN_ACK )
Printf("negotiated ");
else Printf("no autonegotiation,");
dump_mii_media( advert & curlink, 1 );
Printf(", ");
}
else
{
Printf("autonegotiation failed, ");
}
}
else
if (bmcr & MII_BMCR_RESTART)
{
Printf("autonegotiation restarted, ");
}
}
else
{
Printf("%s Mbit, %s duplex, ",
(bmcr & MII_BMCR_100MBIT) ? "100" : "10",
(bmcr & MII_BMCR_DUPLEX) ? "full" : "half" );
}
if( bmsr & MII_BMSR_LINK_VALID )
Printf("link ok");
else Printf("no link");
Printf("\n");
if( verbose > 1 )
{
Printf("PHY Registers:");
for( i=0 ; i < length/sizeof( struct S2DevQueryMIIParam ) ; i++ )
{
if(!(i%8))
Printf("\n");
if( mii[i].ID == S2_DEVQUERYEXT_MII_INVALID )
Printf("N/A ");
else
Printf("%04lx ",(LONG)(mii[i].Content));
}
Printf("\n");
}
if( verbose )
{
Printf(" vendor %02lx:%02lx:%02lx, model %ld rev %ld\n",
(LONG)mii[2].Content>>10,
(LONG)(mii[2].Content>>2)&0xff,
(LONG)((mii[2].Content<<6)|(mii[3].Content>>10))&0xff,
(LONG)(mii[3].Content>>4)&0x3f,
(LONG)(mii[3].Content&0x0f)
);
Printf(" basic mode: ");
if( bmcr & MII_BMCR_RESET )
Printf("software reset, ");
if( bmcr & MII_BMCR_LOOPBACK )
Printf("loopback, ");
if( bmcr & MII_BMCR_ISOLATE )
Printf("isolate, ");
if( bmcr & MII_BMCR_COLTEST )
Printf("collision test, ");
if( bmcr & MII_BMCR_AN_ENA )
Printf("autonegotiation enabled\n");
else
Printf("%s Mbit, %s duplex\n",
(bmcr & MII_BMCR_100MBIT) ? "100" : "10",
(bmcr & MII_BMCR_DUPLEX) ? "full" : "half");
Printf(" basic status: ");
if( bmsr & MII_BMSR_AN_COMPLETE )
Printf("autonegotiation complete, ");
else if( bmcr & MII_BMCR_RESTART )
Printf("autonegotiation restarted, ");
if( bmsr & MII_BMSR_REMOTE_FAULT )
Printf(" remote fault, ");
Printf( (bmsr & MII_BMSR_LINK_VALID) ? "link ok" : "no link");
Printf("\n capabilities:");
dump_mii_media( bmsr >> 6, 0 );
Printf("\n advertising: ");
dump_mii_media( advert, 0 );
if( curlink & MII_AN_ABILITY_MASK )
{
Printf("\n link partner:");
dump_mii_media( curlink, 0 );
}
Printf("\n");
}
return 1;
}
/*
Query consecutive set of MII registers from start to end (inclusive)
*/
LONG query_mii( struct prgdata *prg, struct S2DevQueryMIIParam *mii, LONG start, LONG end )
{
struct S2DevQueryMIIParam *miitmp;
struct S2DevQueryExtParam parm_mii;
struct TagItem tags[2];
LONG i;
/* MII specific */
parm_mii.Data = (APTR)mii;
parm_mii.Length = (end-start+1)*sizeof(struct S2DevQueryMIIParam);
parm_mii.Actual = 0;
for( i=start,miitmp=mii ; i <= end ; i++,miitmp++ ) /* MII standard register set: 8 */
{
miitmp->ID = i;
}
tags[i=0].ti_Tag = S2_DevQueryExtGetMII;
tags[i++].ti_Data = (ULONG) &parm_mii;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
return 0;
else
return parm_mii.Actual;
}
LONG write_mii( struct prgdata *prg, struct S2DevQueryMIIParam *mii, LONG num )
{
struct S2DevQueryExtParam parm_mii;
struct TagItem tags[2];
LONG i;
/* MII specific */
parm_mii.Data = (APTR)mii;
parm_mii.Length = (num)*sizeof(struct S2DevQueryMIIParam);
parm_mii.Actual = 0;
tags[i=0].ti_Tag = S2_DevQueryExtSetMII;
tags[i++].ti_Data = (ULONG) &parm_mii;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
return 0;
else
return parm_mii.Actual;
}
/* 8 basic registers, we poll 16 out of curiosity */
#define MII_REGNUM 16
/* two spare registers for write mode */
#define MII_SPARE 2
int main(int argc, char **argv)
{
struct prgdata _prg,*prg=&_prg;
int res = RETURN_FAIL;
char vendorname[128], productname[128];
struct S2DevQueryExtParam parm_productname;
struct S2DevQueryExtParam parm_vendorname;
struct S2DevQueryExtParam parm_mii;
struct S2DevQueryMIIParam mii[MII_REGNUM+MII_SPARE];
struct TagItem tags[3];
int i;
struct RDArgs *rdargs;
BYTE *name;
LONG unit,autoneg,force;
if( !start_prog(prg) )
return res;
if( !(rdargs = ReadArgs( (char*)opt_template,(LONG*)&prg->opts,NULL) ) )
{
Printf("Argument error\n");
end_prog(prg);
return res;
}
if( !prg->opts.devname )
{
name = "enc624j6net.device";
Printf("TODO: auto-detect, now trying default %s\n",name);
/* end_prog(prg);
return res; */
}
else
name = prg->opts.devname;
unit = (prg->opts.unit) ? *prg->opts.unit : 0;
if( prg->opts.vverbose )
prg->opts.verbose = 2;
else
if( prg->opts.verbose )
prg->opts.verbose = 1;
/* parameter check */
if( ( (prg->opts.force) && (prg->opts.renegotiate) ) ||
( (prg->opts.force) && (prg->opts.advertise) )
)
{
Printf("Error: Forced and Autonegotiation parameter mismatch\n");
end_prog(prg);
return RETURN_FAIL;
}
/* convert text to binary mask */
autoneg = parse_speedduplex( prg->opts.advertise );
force = parse_speedduplex( prg->opts.force );
if( (autoneg|force) < 0 )
{
end_prog(prg);
return RETURN_FAIL;
}
if( get_device( prg, name , unit ) )
{
if( probe_device( prg ) )
res = RETURN_OK;
}
if( res != RETURN_OK )
{
end_prog(prg);
return res;
}
/* device open, query extension present, now query it */
{
/* general information */
parm_vendorname.Data = vendorname;
parm_vendorname.Length = sizeof(vendorname);
parm_vendorname.Actual = 0;
parm_productname.Data = productname;
parm_productname.Length = sizeof(productname);
parm_productname.Actual = 0;
#if 1
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
tags[i++].ti_Data = (ULONG) &parm_vendorname;
tags[i ].ti_Tag = S2_DevQueryExtProductName;
tags[i++].ti_Data = (ULONG) &parm_productname;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
DoIO( (struct IORequest *)prg->sana2devio );
/* separate query subroutine in here for MII, though not
absolutely necessary (MII is queried more than once) */
parm_mii.Actual = query_mii( prg, mii, 0, 15 );
if( parm_mii.Actual )
{
/* read BMSR twice */
query_mii( prg, mii+MII_BMSR, MII_BMSR, MII_BMSR );
res = RETURN_OK;
}
else
res = RETURN_WARN;
#else
/* MII specific */
parm_mii.Data = (APTR)mii;
parm_mii.Length = sizeof(mii);
parm_mii.Actual = 0;
for( i=0 ; i < 16 ; i++ ) /* MII standard register set: 8 */
{
mii[i].ID = i; /* mii[i].Content = 0; */
}
mii[16].ID = MII_BMSR; /* read BMSR twice */
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
tags[i++].ti_Data = (ULONG) &parm_vendorname;
tags[i ].ti_Tag = S2_DevQueryExtProductName;
tags[i++].ti_Data = (ULONG) &parm_productname;
tags[i ].ti_Tag = S2_DevQueryExtGetMII;
tags[i++].ti_Data = (ULONG) &parm_mii;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof tags;
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
res = RETURN_WARN;
else res = RETURN_OK;
mii[MII_BMSR].Content = mii[16].Content; /* read BMSR twice */
#endif
}
Printf("Device: %s\n",name);
/* general info */
if( parm_vendorname.Actual != 0 )
{
vendorname[parm_vendorname.Actual-1] = 0;
Printf("Vendor: %s\n",vendorname);
}
if( parm_productname.Actual != 0 )
{
productname[parm_productname.Actual-1] = 0;
Printf("Product: %s\n",productname);
}
/* after query, see what we've got */
if( res == RETURN_OK )
{
/* MII data */
if( parm_mii.Actual == 0 )
{
Printf("Unable to query MII data.\n");
}
else
{
if( !(prg->opts.renegotiate) && !(prg->opts.reset)
&& !(prg->opts.advertise) && !(prg->opts.force)
)
{
Printf("Active Parameters:\n");
dump_mii( mii, parm_mii.Actual, prg->opts.verbose );
}
}
if( prg->opts.reset )
{
Printf("resetting the transceiver...\n");
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = MII_BMCR_RESET;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
if( prg->opts.advertise )
{
mii[MII_REGNUM].ID = MII_ANAR;
mii[MII_REGNUM].Content = autoneg|1;
write_mii( prg, &mii[MII_REGNUM], 1 );
prg->opts.renegotiate = 1;
}
if( prg->opts.renegotiate )
{
Printf("restarting autonegotiation...\n");
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = 0x0000;
write_mii( prg, &mii[MII_REGNUM], 1 );
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = MII_BMCR_AN_ENA|MII_BMCR_RESTART;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
if( prg->opts.force )
{
UWORD bmcr = 0;
if( force & (MII_AN_100BASETX_FD|MII_AN_100BASETX_HD))
bmcr |= MII_BMCR_100MBIT;
if( force & (MII_AN_100BASETX_FD|MII_AN_10BASET_FD))
bmcr |= MII_BMCR_DUPLEX;
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = bmcr;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
}
end_prog(prg);
return res;
}
Driver/baxnet/source/miitool.h
+70
View File
@@ -0,0 +1,70 @@
/*******************************************************************************************/
/** **/
/** miitool.h **/
/** definitions for PHY registers **/
/** **/
/** Copyright (C) 2000 David A. Hinds -- dhinds@pcmcia.sourceforge.org **/
/** **/
/** origin: mii.h in net-tools-1.60 **/
/** **/
/*******************************************************************************************/
#ifndef _INC_MIITOOL_H
#define _INC_MIITOOL_H
/* Basic Mode Control Register */
#define MII_BMCR 0x00
#define MII_BMCR_RESET 0x8000
#define MII_BMCR_LOOPBACK 0x4000
#define MII_BMCR_100MBIT 0x2000
#define MII_BMCR_AN_ENA 0x1000
#define MII_BMCR_ISOLATE 0x0400
#define MII_BMCR_RESTART 0x0200
#define MII_BMCR_DUPLEX 0x0100
#define MII_BMCR_COLTEST 0x0080
/* Basic Mode Status Register */
#define MII_BMSR 0x01
#define MII_BMSR_CAP_MASK 0xf800
#define MII_BMSR_100BASET4 0x8000
#define MII_BMSR_100BASETX_FD 0x4000
#define MII_BMSR_100BASETX_HD 0x2000
#define MII_BMSR_10BASET_FD 0x1000
#define MII_BMSR_10BASET_HD 0x0800
#define MII_BMSR_NO_PREAMBLE 0x0040
#define MII_BMSR_AN_COMPLETE 0x0020
#define MII_BMSR_REMOTE_FAULT 0x0010
#define MII_BMSR_AN_ABLE 0x0008
#define MII_BMSR_LINK_VALID 0x0004
#define MII_BMSR_JABBER 0x0002
#define MII_BMSR_EXT_CAP 0x0001
#define MII_PHY_ID1 0x02
#define MII_PHY_ID2 0x03
/* Auto-Negotiation Advertisement Register */
#define MII_ANAR 0x04
/* Auto-Negotiation Link Partner Ability Register */
#define MII_ANLPAR 0x05
#define MII_AN_NEXT_PAGE 0x8000
#define MII_AN_ACK 0x4000
#define MII_AN_REMOTE_FAULT 0x2000
#define MII_AN_ABILITY_MASK 0x07e0
#define MII_AN_FLOW_CONTROL 0x0400
#define MII_AN_100BASET4 0x0200
#define MII_AN_100BASETX_FD 0x0100
#define MII_AN_100BASETX_HD 0x0080
#define MII_AN_10BASET_FD 0x0040
#define MII_AN_10BASET_HD 0x0020
#define MII_AN_PROT_MASK 0x001f
#define MII_AN_PROT_802_3 0x0001
/* Auto-Negotiation Expansion Register */
#define MII_ANER 0x06
#define MII_ANER_MULT_FAULT 0x0010
#define MII_ANER_LP_NP_ABLE 0x0008
#define MII_ANER_NP_ABLE 0x0004
#define MII_ANER_PAGE_RX 0x0002
#define MII_ANER_LP_AN_ABLE 0x0001
#endif /* _INC_MIITOOL_H */
Driver/baxnet/source/sdnet/hw.c
+9 -6
View File
@@ -36,13 +36,12 @@ extern const BYTE DeviceName[];
#define HW_INTERVALDEF 10000
#define HW_DEFSPI 2
/* these calls might not run within the context of a process and
will be called from varying tasks and without prior init:
hw_Find_Boards()
hw_Find_Boards() - this one just identifies available HW and returns #boards
hw_AllocBoard()
hw_ReleaseBoard()
hw_GetMacAddress()
hw_GetMacAddress() - get default MAC address from board
these calls are in the context of the server task:
hw_Setup() - general init (board allocated already)
@@ -50,7 +49,7 @@ extern const BYTE DeviceName[];
hw_Attach() - make hardware ready for action (online)
hw_Detach() - put hardware into sleep mode (offline)
hw_recv_sigmask() - get signals for hardware (if any)
hw_recv_sigmask() - get signals for hardware (if any, i.e. signal on interrupt)
hw_recv_pending() - check for pending receive frames
hw_recv_frame() - receive one frame
@@ -59,10 +58,14 @@ extern const BYTE DeviceName[];
and apply them (called only when no RX/TX
in progress)
hw_config_init() - set defaults for HW
hw_config_update() - update config of HW
hw_ConfigInit() - set defaults for HW
hw_ConfigUpdate() - update config of HW
hw_change_multicast - re-initialize multicast filter for new address list
hw_get_mac_status() - running parameters (optional), S2_DEVICEQUERYEXT
*/
#ifdef PROTO_V2EXPNET
#define USE_INTERRUPT
Driver/baxnet/source/server.c
+139 -8
View File
@@ -35,9 +35,12 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq );
*/
#define S2QUERYEXT_NOLENGTHCHECK
/* this limits the number of write requests per run, also improves
Roadshow performance when active */
#define ONE_WRITE_REQ
/* tunables: number of one-call read and write requests */
/* this limits the number of processed write requests per run when enabled */
#define ONE_WRITE_REQ 2
/* this limits the number of processed read requests per run when enabled */
#define ONE_READ_REQ 2
/* (avoid external link libraries) this call is not time critical */
@@ -570,6 +573,67 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
}
}
#ifdef S2_DevQueryExtGetMII
tval = GetTagData( S2_DevQueryExtGetMII, 0, tlist );
if( tval )
{
struct S2DevQueryMIIParam *miip;
LONG res;
LONG curidx=0,lastidx = 0;
D(("MII Register Query"));
s2qep = (struct S2DevQueryExtParam *)tval;
len = s2qep->Length; /* in Bytes */
miip = (struct S2DevQueryMIIParam *)s2qep->Data;
while( curidx <= len-sizeof( struct S2DevQueryMIIParam ) )
{
if( (res = hw_read_phy( db, unit, miip->ID )) >= 0 )
{
miip->Content = res;
lastidx = curidx;
}
else
{ /* can't read register ID, invalidate */
miip->ID = S2_DEVQUERYEXT_MII_INVALID;
miip->Content = 0;
}
miip++;
curidx += sizeof( struct S2DevQueryMIIParam );
}
s2qep->Actual = lastidx;
}
#endif
#ifdef S2_DevQueryExtSetMII
tval = GetTagData( S2_DevQueryExtSetMII, 0, tlist );
if( tval )
{
struct S2DevQueryMIIParam *miip;
LONG res;
LONG curidx=0,lastidx = 0;
D(("MII Register Write"));
s2qep = (struct S2DevQueryExtParam *)tval;
len = s2qep->Length; /* in Bytes */
miip = (struct S2DevQueryMIIParam *)s2qep->Data;
while( curidx <= len-sizeof( struct S2DevQueryMIIParam ) )
{
if( miip->ID != S2_DEVQUERYEXT_MII_INVALID )
{
if( (res = hw_write_phy( db, unit, miip->ID, miip->Content )) >= 0 )
lastidx = curidx;
miip++;
curidx += sizeof( struct S2DevQueryMIIParam );
}
}
s2qep->Actual = lastidx;
}
#endif
return 1;
}
@@ -632,13 +696,24 @@ LONG server_writeerror( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, LONG cod
#ifndef EXTERNAL_WRITE_FRAME
/* note: entering here with locked semaphore */
/*
note: entering here with locked semaphore
note(2): HW_DMA_TX is maybe a little misleading in it's actual use here.
This implementation will use that SANA-II capability in the following
way: Obtain a pointer to either the whole frame (RAW) or the Payload
and send either a complete frame or two chunks down to the hardware.
HW_DMA_TX is defined by the Makefile. One of the chunks
is the constant-size header (14 Bytes) and the other is the payload.
*/
static LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
{
LONG ret;/* = SERR_OK;*/
UBYTE *copy_ptr,*frame;
ULONG framesize;
struct db_BufferManagement *dbm;
#ifdef HW_DMA_TX
UBYTE *header_ptr;
#endif
D(("write: type %08lx, size %ld\n",ioreq->ios2_PacketType,
ioreq->ios2_DataLength));
@@ -646,6 +721,9 @@ static LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
frame = db->db_svdat.sv_frame;
framesize = ioreq->ios2_DataLength;
copy_ptr = frame;
#ifdef HW_DMA_TX
header_ptr= NULL;
#endif
/* copy raw frame: simply overwrite ethernet frame part of plip packet */
if( !(ioreq->ios2_Req.io_Flags & SANA2IOF_RAW) )
@@ -653,18 +731,46 @@ static LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
COPYMAC( frame, ioreq->ios2_DstAddr ); /* macro in server.h */
COPYMAC( frame+6, db->db_Units[unit].du_CFGAddr );
*( (USHORT*)(frame+12)) = ioreq->ios2_PacketType;
#ifdef HW_DMA_TX
header_ptr = frame;
copy_ptr += 16; /* aligned behind header with a gap of 2 */
#else
copy_ptr += 14;
framesize += 14;
#endif
}
dbm = (struct db_BufferManagement *)ioreq->ios2_BufferManagement;
/* copy32 is valid ptr, even if the stack offers only regular CopyFromBuffer */
/* #if 0 */
#ifdef HW_DMA_TX
/* hw implementation supports it, now check if we can use DMA copy buffer */
if( dbm->dbm_CopyFromBufferDMA )
{
UBYTE *dma_ptr;
dma_ptr = (UBYTE*)(*dbm->dbm_CopyFromBufferDMA)( ioreq->ios2_Data, NULL, 0 );
if( dma_ptr )
{
/* pass extra header if not raw */
hw_send_frame(db, unit, dma_ptr,framesize, header_ptr );
ret = SERR_OK; /* FIXME: error code */
goto dmasend_done;
}
}
#endif
/* copy32 is a valid ptr, even if the stack offers only regular CopyFromBuffer */
if( (*dbm->dbm_CopyFromBuffer32)(copy_ptr,ioreq->ios2_Data, ioreq->ios2_DataLength) )
{
send:
D(("+hw_send\n"));
ret = hw_send_frame(db, unit, frame, framesize) ? SERR_OK : SERR_ERROR;
#ifdef HW_DMA_TX
ret = hw_send_frame(db, unit, copy_ptr, framesize, header_ptr ) ? SERR_OK:SERR_ERROR;
#else
ret = hw_send_frame(db, unit, frame, framesize ) ? SERR_OK : SERR_ERROR;
#endif
D(("-hw_send\n"));
}
else
@@ -676,6 +782,10 @@ send:
ret = SERR_BUFFER_ERROR;
}
#ifdef HW_DMA_TX
dmasend_done:
#endif
return ret;
}
#endif
@@ -684,17 +794,20 @@ send:
static LONG server_writequeue( DEVBASEP, ULONG unit )
{
LONG code;
#ifdef ONE_WRITE_REQ
LONG t = 0;
#endif
struct IOSana2Req *ioreq,*nextio;
ObtainSemaphore( &db->db_Units[unit].du_Sem );
#if 1 /* #ifdef ONE_WRITE_REQ */
#if 1
/* whole queue per call */
for( ioreq = (struct IOSana2Req *)db->db_Units[unit].du_WriteQueue.lh_Head;
(nextio= (struct IOSana2Req *)ioreq->ios2_Req.io_Message.mn_Node.ln_Succ);
ioreq = nextio )
#else
/* single write per call */
/* single write per call (deprecated in favor of ONE_WRITE_REQ) */
ioreq = (struct IOSana2Req *)db->db_Units[unit].du_WriteQueue.lh_Head;
if( ioreq->ios2_Req.io_Message.mn_Node.ln_Succ )
#endif
@@ -731,8 +844,13 @@ static LONG server_writequeue( DEVBASEP, ULONG unit )
server_writeerror( db, unit, ioreq, code );
}
#ifdef ONE_WRITE_REQ
t++;
if( t >= ONE_WRITE_REQ ) /* this somewhat balances hardware polling overhead vs. IP-stack timing */
{
t = 0;
if( hw_recv_pending(db,unit) )
break;
}
#endif
}
@@ -817,6 +935,9 @@ static LONG server_readqueue( DEVBASEP, ULONG unit )
LONG framesize;
LONG frametype;
LONG dropflag;
#ifdef ONE_READ_REQ
LONG t=0;
#endif
while(1)
{
@@ -895,7 +1016,17 @@ nextframe:
/* TODO: check for error, send S2EVENT_HARDWARE|S2EVENT_ERROR|S2EVENT_RX along with stats db_DevStats.BadData */
goto end;
}
#ifdef ONE_READ_REQ
t++;
if( t>= ONE_READ_REQ )
{
struct IOSana2Req *wr = (struct IOSana2Req *)db->db_Units[unit].du_WriteQueue.lh_Head;
/* t=0; */
if( wr->ios2_Req.io_Message.mn_Node.ln_Succ )
goto end; /* pending writes ? -> leave after ONE_READ_REQ requests */
}
#endif
} /* while(1) */
end:
return SERR_OK;
}
Driver/baxnet/source/smakefile.enc
+4 -2
View File
@@ -30,8 +30,8 @@ ASMOBJECTS = $(SUBDIR)/enc624j6l.o$(TYPE) $(SUBDIR)/intervaltimer.o$(TYPE)
# more than one flavour of the same code base may be build with this setup
# arguments passed down recursively (example):
#DEVICEID=v2expeth.device
#DEFINES1 = -DPROTO_V2EXPNET
#ASMDEFS = -DPROTO_V2EXPNET
DEFINES1 = DEFINE HW_DMA_TX=1
ASMDEFS1 = -DHW_DMA_TX=1
#CPU = 68020
@@ -98,6 +98,8 @@ DEFINES = $(DEFINES) DEFINE DEVICENAME=$(DEVICEID)
ASMDEFS = $(ASMDEFS1)
#-DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
###############################################################################
#
# debug
Driver/baxnet/source/version.h
+2 -2
View File
@@ -9,9 +9,9 @@
#define _INC_VERSION_H
#define DEVICEVERSION 2
#define DEVICEREVISION 0
#define DEVICEREVISION 1
#define DEVICEEXTRA
/* #define DEVICEEXTRA Beta */
#define DEVICEDATE 13.01.2019
#define DEVICEDATE 21.02.2019
#endif
Logic/LAN_IDE/LAN_IDE.gise
+17 -9
View File
@@ -32,6 +32,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="LAN_IDE_CP.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="LAN_IDE_CP.pnx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
@@ -42,9 +43,11 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP_build.xml"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_envsettings.html"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="LAN_IDE_CP_html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="LAN_IDE_CP_pad.csv"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
@@ -65,7 +68,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551390224" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1235887333676579674" xil_pn:start_ts="1551390212">
<transform xil_pn:end_ts="1551994116" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5899415373064323687" xil_pn:start_ts="1551994105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -86,7 +89,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551390232" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551390224">
<transform xil_pn:end_ts="1551994125" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551994116">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
@@ -95,27 +98,33 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1551390285" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551390232">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1551994174" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551994125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.gyd"/>
<outfile xil_pn:name="LAN_IDE_CP.mfd"/>
<outfile xil_pn:name="LAN_IDE_CP.nga"/>
<outfile xil_pn:name="LAN_IDE_CP.pad"/>
<outfile xil_pn:name="LAN_IDE_CP.pnx"/>
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
<outfile xil_pn:name="LAN_IDE_CP.tim"/>
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
<outfile xil_pn:name="LAN_IDE_CP.vm6"/>
<outfile xil_pn:name="LAN_IDE_CP.xml"/>
<outfile xil_pn:name="LAN_IDE_CP_build.xml"/>
<outfile xil_pn:name="LAN_IDE_CP_html"/>
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1551390161" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1551390159">
<transform xil_pn:end_ts="1551994176" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1551994174">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
</transform>
<transform xil_pn:end_ts="1551386236" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1551386235">
<transform xil_pn:end_ts="1551990706" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1551990706">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1550755464" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1550755461">
@@ -123,7 +132,6 @@
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1551017787" xil_pn:in_ck="-8497105071423008236" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1551017787">
Logic/LAN_IDE/LAN_IDE.xise
+2 -2
View File
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Sequential" xil_pn:valueState="non-default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -111,7 +111,7 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE/LAN_IDE_CP-W.vhd
+260 -244
View File
@@ -107,8 +107,10 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
config_rw
wait_cycle_end,
config_rw,
cp_read,
cp_write_wait
);
signal LAN_RST_SM: lan_reset :=nop;
@@ -122,7 +124,7 @@ architecture Behavioral of LAN_IDE_CP is
signal ROM_OE_S: STD_LOGIC;
signal CP_ACCESS: STD_LOGIC;
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
signal LAN_ACCESS: STD_LOGIC;
signal DQ_SWAP: STD_LOGIC;
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
@@ -135,7 +137,6 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
@@ -145,10 +146,19 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal INT6_SIG:STD_LOGIC;
signal INT2_SIG:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal CP_WAIT:STD_LOGIC_VECTOR(3 downto 0);
signal AMIGA_CLK:STD_LOGIC;
signal DS:STD_LOGIC;
@@ -244,41 +254,48 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(--AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
Z3_ADR <= (others => '1');
CP_ACCESS <= '0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
--if((D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(D(15 downto 8) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
--CP base
--if((D(15 downto 8) & A(23 downto 16)) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
if(D(15 downto 8) = CP_BASEADR(15 downto 8) and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(--FCS ='0' or
reset='0')then
if(reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
elsif(falling_edge(AS))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
@@ -287,12 +304,7 @@ begin
AUTOCONFIG_Z2_ACCESS <= '0';
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
@@ -304,186 +316,6 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
if( LAN_INT ='1' --or --no interupt
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
)then
LAN_IRQ_OUT <='1';
elsif(
(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
) then
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
end if;
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
if(LAN_SM_RST ='1' ) then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
end case;
end if;
end process lan_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
@@ -494,7 +326,7 @@ begin
D_Z2_OUT<="1111";
SHUT_UP_Z2 <="111";
IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
CP_BASEADR<=x"FFFF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
@@ -507,7 +339,7 @@ begin
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
else
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
@@ -566,22 +398,20 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
if(AUTO_CONFIG_Z2_DONE(0) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
CP_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
if(AUTO_CONFIG_Z2_DONE(2) = '0')then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(2) <= '0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
@@ -602,10 +432,216 @@ begin
end case;
end if;
end if;
end process autoconfig_proc; --- that's all
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset,FCS )
begin
if(reset = '0' or FCS='1') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
CP_WAIT <="0000";
CP_RD_S <= '1';
CP_WE_S <= '1';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
CP_RD_S <= '1';
CP_WE_S <= '1';
-- delay for clockport
if(CP_ACCESS = '1') then
CP_WAIT <= CP_WAIT+1;
else
CP_WAIT <="0000";
end if;
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
elsif(CP_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(RW='1') then
CP_RD_S <= '0';
LAN_SM <= cp_read;
else
CP_WE_S <= '0';
LAN_SM <= cp_write_wait;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM <= wait_cycle_end;
when cp_read=>
CP_RD_S <= '0';
Z3_DATA(31 downto 0) <= DQ & DQ; -- bus mirroring
if(CP_WAIT(3) = '1') then --wait enough for CP-read
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
else
LAN_SM<=cp_read; -- stay here until cp is ready
end if;
when cp_write_wait=>
CP_WE_S <= '0';
if(CP_WAIT(3) = '1') then --wait enough for CP-write
LAN_READY <='1';
LAN_SM<= wait_cycle_end; --deassert CP_W
else
LAN_SM<=cp_write_wait;
end if;
end case;
end if;
end process lan_rw_gen;
--for the future
CP_WE <= CP_WE_S when FCS='0' else '1';
CP_RD <= CP_RD_S when FCS='0' else '1';
CP_CS <= not CP_ACCESS;
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when FCS='0' and reset = '1' else LAN_WR_RST;
@@ -624,37 +660,35 @@ begin
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
(others => 'Z');
A(7 downto 1) <= (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when reset='0' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D when RW='0' and AS='0' and CP_ACCESS ='1' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and (LAN_ACCESS ='1' or CP_ACCESS='1') else
(others => 'Z');
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
INT2_OUT <= '0' when LAN_INT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
SLAVE <= '0' when FCS='0' and (LAN_ACCESS = '1' or CP_ACCESS = '1') else
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
OVR <= '0' when FCS='0' and (LAN_ACCESS = '1' or CP_ACCESS = '1') else 'Z'; --is Cache inhibit on Z3!
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
@@ -696,25 +730,7 @@ begin
ROM_B <= "00";
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP-Z.vhd
-494
View File
@@ -1,494 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:29 12/13/2016
-- Design Name:
-- Module Name: LAN_IDE_CP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- directory cleanup hint:
-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LAN_IDE_CP is
Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
D : inout STD_LOGIC_VECTOR (15 downto 0);
DQ : inout STD_LOGIC_VECTOR (15 downto 0);
A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
OWN : out STD_LOGIC;
SLAVE : out STD_LOGIC;
CFOUT : out STD_LOGIC;
CFIN : in STD_LOGIC;
C1 : in STD_LOGIC;
C3 : in STD_LOGIC;
MTCR : in STD_LOGIC;
OVR : out STD_LOGIC;
BERR : in STD_LOGIC;
MTACK : out STD_LOGIC;
DS0 : in STD_LOGIC;
DTACK : out STD_LOGIC;
UDS : in STD_LOGIC;
LDS : in STD_LOGIC;
AS : in STD_LOGIC;
RW : in STD_LOGIC;
Z3 : in STD_LOGIC;
DS1 : in STD_LOGIC;
FCS : in STD_LOGIC;
RESET : in STD_LOGIC;
INT_OUT : out STD_LOGIC;
AUTOBOOT_OFF : in STD_LOGIC;
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
ROM_OE : out STD_LOGIC;
IDE_WAIT : in STD_LOGIC;
CLK_EXT : in STD_LOGIC;
IDE_W : out STD_LOGIC;
IDE_R : out STD_LOGIC;
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
LAN_RD : out STD_LOGIC;
LAN_CS : out STD_LOGIC;
LAN_WRH : out STD_LOGIC;
LAN_WRL : out STD_LOGIC;
LAN_INT : in STD_LOGIC;
CP_RD : out STD_LOGIC;
CP_WE : out STD_LOGIC;
CP_CS : out STD_LOGIC;
CP_IRQ : in STD_LOGIC);
end LAN_IDE_CP;
architecture Behavioral of LAN_IDE_CP is
TYPE lan_reset IS (
nop,
wait0,
clr,
clr_commit,
wait1,
set,
set_commit,
done
);
SIGNAL LAN_RST_SM: lan_reset :=nop;
SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
SIGNAL ide: STD_LOGIC;
SIGNAL autoconfig: STD_LOGIC;
SIGNAL lan_adr: STD_LOGIC;
SIGNAL lan_adr_sw: STD_LOGIC;
SIGNAL cp: STD_LOGIC;
signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(1 downto 0);
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal IDE_ENABLE:STD_LOGIC;
signal ROM_OE_S:STD_LOGIC;
signal IDE_R_S:STD_LOGIC;
signal IDE_W_S:STD_LOGIC;
signal DTACK_S:STD_LOGIC;
signal AMIGA_CLK: std_logic;
signal LAN_INT_ENABLE: std_logic;
signal DECODE_RESET: std_logic;
signal LAN_INT_D0: std_logic;
signal DS: std_logic;
signal DS_D: std_logic;
signal LAN_RD_S: std_logic;
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000";
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000";
Function to_std_logic(X: in Boolean) return Std_Logic is
variable ret : std_logic;
begin
if x then ret := '1'; else ret := '0'; end if;
return ret;
end to_std_logic;
begin
AMIGA_CLK <= not (C1 xor C3);
DECODE_RESET <= BERR and reset;
DS <= UDS and LDS;
clock_init: process(CLK_EXT)
begin
if(rising_edge(CLK_EXT))then
if(reset = '0')then
--init the clock!
case LAN_RST_SM is
when nop=>
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=wait0;
when wait0=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=clr;
when clr=>
LAN_CS_RST<='1';
LAN_WR_RST<='1';
LAN_RST_SM<=clr_commit;
when clr_commit=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=wait1;
when wait1=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=set;
when set=>
LAN_CS_RST<='1';
LAN_WR_RST<='1';
LAN_RST_SM<=set_commit;
when set_commit=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=done;
when done=>
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=done;
end case;
else
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=nop;
end if;
end if;
end process clock_init;
ADDRESS_DECODE: process(DECODE_RESET,AS)
begin
if(DECODE_RESET ='0')then
autoconfig <= '0';
ide <= '0';
lan_adr <= '0';
lan_adr_sw <= '0';
cp <= '0';
lancp <= '0';
elsif(falling_edge(AS))then
--default values
autoconfig <= '0';
ide <= '0';
lan_adr <= '0';
lan_adr_sw <= '0';
cp <= '0';
lancp <= '0';
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
autoconfig <= '1';
elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
if(A(14 downto 13)<"11")then
lan_adr_sw <= '1';
end if;
lan_adr <= '1';
lancp <= '1';
elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
cp <= '1';
lancp <= '1';
elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
ide <= '1';
end if;
end if;
end process ADDRESS_DECODE;
--LAN interrupt enable
lan_int_proc: process (AMIGA_CLK,reset)
begin
if(reset ='0') then
LAN_INT_ENABLE <='0';
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif falling_edge(AMIGA_CLK) then
LAN_IRQ_D0 <= LAN_INT;
if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
LAN_IRQ_OUT <='0';
elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then
LAN_IRQ_OUT <='1';
elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
LAN_IRQ_OUT <= D(14); --controll lan irq
end if;
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
LAN_INT_ENABLE <= D(15);
end if;
end if;
end process lan_int_proc;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
if(lan_adr='1' and DS='0' and A(15)='0')then
LAN_RD_S <= RW;
-- swapped LDS/UDS here: ENC624 is little endian
LAN_WRH_S <= not LDS and not RW;
LAN_WRL_S <= not UDS and not RW;
end if;
end if;
end process lan_rw_gen;
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(cp = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S;
end if;
end process cp_rw_gen;
--ide signal generation
ide_rw_gen: process (reset,AMIGA_CLK)
begin
if (reset = '0') then
IDE_ENABLE <= '1';
IDE_R_S <= '1';
IDE_W_S <= '1';
ROM_OE_S <= '1';
elsif falling_edge(AMIGA_CLK) then
--default values
IDE_R_S <= '1';
IDE_W_S <= '1';
ROM_OE_S <= '1';
if(ide='1' and AS='0')then
if(RW='0')then
--the write goes to the hdd!
IDE_ENABLE <= '0'; -- enable IDE on first read
IDE_W_S <= '0';
else
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
ROM_OE_S <= not IDE_ENABLE;
end if;
end if;
end if;
end process ide_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
begin
if reset = '0' then
-- reset active ...
AUTO_CONFIG_DONE_CYCLE <="00";
Dout1<="1111";
--Dout2<="1111";
SHUT_UP <="111";
IDE_BASEADR<=x"FF";
LAN_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
AUTO_CONFIG_DONE <="00";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
DS_D <= DS;
if(AS='1')then
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
elsif(autoconfig= '1' and DS='0') then
case A(6 downto 1) is
when "000000" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
else
Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
when "000010" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1000" ; --ProductID high nibble : 7->1000
else
Dout1 <= "1111" ; --ProductID high nibble : 0->1111
end if;
when "000011" =>
if(AUTO_CONFIG_DONE = 0)then
Dout1 <= "0100" ; --ProductID low nibble: B->0100
elsif(AUTO_CONFIG_DONE = 1)then
Dout1 <= "0011" ; --ProductID low nibble: C->0011
else
Dout1 <= "1001" ; --ProductID low nibble: 6->1001
end if;
when "001000" => Dout1 <= "1111" ; --Ventor ID 0
when "001001" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "0101" ; --Ventor ID 1
else
Dout1 <= "0111" ; --Ventor ID 1
end if;
when "001010" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1110" ; --Ventor ID 2
else
Dout1 <= "1101" ; --Ventor ID 2
end if;
when "001011" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
else
Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC
end if;
when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble
when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble
when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble
when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble
when "010000" => Dout1 <= "1111" ; --Serial byte 2 high nibble
when "010001" => Dout1 <= "1111" ; --Serial byte 2 low nibble
when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble
when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
if(AUTO_CONFIG_DONE = 2)then
Dout1 <= "1110" ; --Rom vector low byte low nibble
else
Dout1 <= "1111" ; --Rom vector low byte low nibble
end if;
when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero
when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero
when "100100" =>
Dout1 <= "1111" ;
if(RW='0' and DS_D='1')then
if(AUTO_CONFIG_DONE = 0)then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(0) <='0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= "01"; --done here
elsif(AUTO_CONFIG_DONE = 1)then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(1) <= '0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part!
elsif(AUTO_CONFIG_DONE = 2)then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(2) <= '0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= "11"; --done here
end if;
end if;
when "100110" =>
Dout1 <= "1111" ;
if(RW='0' and DS_D='1')then
AUTO_CONFIG_DONE_CYCLE <= AUTO_CONFIG_DONE_CYCLE+1; --done here
end if;
when others => Dout1 <= "1111" ;
end case;
end if;
end if;
end process autoconfig_proc; --- that's all
LAN_CS <= lan_adr when reset='1' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
LAN_CFG <= "ZZZZ";
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not cp;
--the lanport is shifted by one adress line but I forgot to adopt the clockport address!
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip
A(14 downto 7);
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(2 downto 1);
--signal assignment
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
(others => 'Z');
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
D when RW='0' and AS='0' and lancp ='1'
else (others => 'Z');
IDE_W <= IDE_W_S when AS='0' else '1';
IDE_R <= IDE_R_S when AS='0' else '1';
IDE_CS(0)<= not(A(12));
IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9);
ROM_B <= "00";
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
-- INT_OUT <= 'Z';
INT_OUT <= '0' when
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
or CP_IRQ = '0'
else 'Z';
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
-- OVR <= 'Z';
OVR <= '0' when ide='1' and AS='0' else 'Z';
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or
-- AUTOCONFIG_IN_PROGRES ='1'
-- else 'Z';
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
-- DTACK <= 'Z';
A <= (others => 'Z');
MTACK <= 'Z';
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.bld
+1 -1
View File
@@ -29,7 +29,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 4418692 kilobytes
Total memory usage is 4418684 kilobytes
Writing NGD file "LAN_IDE_CP.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Logic/LAN_IDE/LAN_IDE_CP.cmd_log
+217
View File
@@ -419,3 +419,220 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE/LAN_IDE_CP.gyd
+71 -69
View File
@@ -20,6 +20,7 @@ DS1 S:PIN78
FCS S:PIN77
LAN_INT S:PIN111
LDS S:PIN82
MTCR S:PIN101
RESET S:PIN143
RW S:PIN83
UDS S:PIN81
@@ -120,82 +121,83 @@ DQ<4> S:PIN124
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 EXP24_ EXP25_ AUTO_CONFIG_Z2_DONE_CYCLE<2> SHUT_UP_Z2<1>
D_5_IOBUFE D_4_IOBUFE EXP26_ IDE_CS_0_OBUF
AUTO_CONFIG_Z2_DONE_CYCLE<1> IDE_CS_1_OBUF LAN_BASEADR<9> IDE_A_0_OBUF$BUF0
LAN_BASEADR<8> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 D_Z2_OUT<0>
PARTITION FB1_1 EXP24_ SHUT_UP_Z2<2> EXP25_ CP_BASEADR<7>
D_5_IOBUFE D_4_IOBUFE CP_BASEADR<6> IDE_CS_0_OBUF
CP_BASEADR<5> IDE_CS_1_OBUF CP_BASEADR<4> IDE_A_0_OBUF$BUF0
CP_BASEADR<1> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 CP_BASEADR<0>
IDE_R_OBUF D_Z2_OUT<2>
PARTITION FB2_1 LAN_SM_FSM_FFd2 A_LAN_4_OBUF A_LAN_7_OBUF
PARTITION FB2_5 A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 DQ_5_IOBUFE/DQ_5_IOBUFE_TRST ROM_B_0_OBUF$BUF5
LAN_RD_S D_6_IOBUFE EXP27_ D_3_IOBUFE
EXP28_ D_7_IOBUFE D_1_IOBUFE LAN_SM_FSM_FFd3
PARTITION FB2_1 DQ<8>_BUFR.MC A_LAN_4_OBUF A_LAN_7_OBUF DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<0> ROM_B_0_OBUF$BUF5
IDE_BASEADR<1> D_6_IOBUFE EXP26_ D_3_IOBUFE
EXP27_ D_7_IOBUFE D_1_IOBUFE EXP28_
D_8_IOBUFE EXP29_
PARTITION FB3_1 $OpTx$BIN_STEP$140 IDE_W_OBUF EXP30_
PARTITION FB3_14 ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF CP_WE_QUIRK
EXP31_
PARTITION FB4_1 IDE_BASEADR<6> D_0_IOBUFE EXP32_ IDE_BASEADR<4>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<3> A_LAN_3_OBUF
IDE_BASEADR<2> IDE_BASEADR<1> IDE_BASEADR<0> A_LAN_2_OBUF
CP_BASEADR<0> A_LAN_5_OBUF EXP33_ D_Z2_OUT<1>
EXP34_ IDE_BASEADR<5>
PARTITION FB5_1 D_8_IOBUFE/D_8_IOBUFE_TRST CP_CS_OBUF SHUT_UP_Z2<2> LAN_BASEADR<10>
ROM_OE_OBUF CP_BASEADR<7> CP_BASEADR<3> CP_BASEADR<2>
EXP35_ D_2_IOBUFE CP_BASEADR<1> D_9_IOBUFE
EXP36_ D_10_IOBUFE D_11_IOBUFE EXP37_
D_12_IOBUFE IDE_BASEADR<7>
PARTITION FB6_1 LAN_D_INIT<8> ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF LAN_IRQ_D0
A_LAN_13_OBUF A_LAN_10_OBUF FCS_SM_P_D0 A_LAN_11_OBUF
LAN_WR_RST A_LAN_8_OBUF LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd2
LAN_RST_SM_FSM_FFd1 A_LAN_9_OBUF LAN_ACCESS EXP38_
LAN_A_INIT<3> LAN_IRQ_OUT
PARTITION FB7_1 Z3_ADR<4> ROM_OE_S D_13_IOBUFE IDE_W_S
D_14_IOBUFE EXP39_ IDE_ENABLE CP_WE_S
CP_RD_S AUTO_CONFIG_Z2_DONE_CYCLE<0> AUTO_CONFIG_Z2_DONE<2> D_15_IOBUFE
IDE_R_S AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0> AUTOCONFIG_Z2_ACCESS
EXP40_ D_Z2_OUT<3>
PARTITION FB8_1 Z3_ADR<2> DQ_12_IOBUFE DQ_14_IOBUFE EXP41_
LAN_WRH_OBUF EXP42_ SHUT_UP_Z2<0> LAN_CS_OBUF
LAN_BASEADR<7> LAN_RD_OBUF LAN_BASEADR<5> LAN_BASEADR<4>
LAN_BASEADR<3> Z3_ADR<3> LAN_BASEADR<2> LAN_BASEADR<1>
LAN_BASEADR<0> LAN_BASEADR<6>
PARTITION FB9_1 Z3_DATA<24> EXP43_ DQ_DATA<6> Z3_DATA<16>
EXP44_ EXP45_ DQ_DATA<5> DQ_DATA<15>
EXP46_ EXP47_ Z3_DATA<0> DQ_DATA<14>
EXP48_ Z3_DATA<1> EXP49_ DQ_DATA<13>
Z3_DATA<2> EXP50_
PARTITION FB3_2 IDE_W_OBUF
PARTITION FB3_10 LAN_A_INIT<3> SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF CP_WE_QUIRK Z3_ADR<9>
ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 Z3_ADR<8> Z3_ADR<7>
LAN_IRQ_OUT
PARTITION FB4_1 IDE_BASEADR<7> D_0_IOBUFE EXP30_ IDE_BASEADR<5>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<4> A_LAN_3_OBUF
IDE_BASEADR<3> IDE_BASEADR<2> CP_BASEADR<3> A_LAN_2_OBUF
CP_BASEADR<2> A_LAN_5_OBUF EXP31_ D_Z2_OUT<1>
EXP32_ IDE_BASEADR<6>
PARTITION FB5_1 EXP33_ CP_CS_OBUF EXP34_ D_8_IOBUFE/D_8_IOBUFE_TRST
ROM_OE_OBUF AUTOCONFIG_Z2_ACCESS
PARTITION FB5_9 EXP35_ D_2_IOBUFE EXP36_ D_9_IOBUFE
EXP37_ D_10_IOBUFE D_11_IOBUFE EXP38_
D_12_IOBUFE IDE_ACCESS/IDE_ACCESS_RSTF__$INT
PARTITION FB6_1 EXP39_ ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF Z3_ADR<6> A_LAN_11_OBUF
Z3_ADR<5> A_LAN_8_OBUF Z3_ADR<13> Z3_ADR<12>
Z3_ADR<11> A_LAN_9_OBUF Z3_ADR<10> INT_VECTOR_CYCLE
EXP40_ IDE_ACCESS
PARTITION FB7_1 Z3_ADR<4> EXP41_ D_13_IOBUFE Z3_ADR<3>
D_14_IOBUFE Z3_ADR_0 EXP42_ LAN_BASEADR<9>
LAN_BASEADR<8> LAN_BASEADR<15> LAN_BASEADR<14> D_15_IOBUFE
EXP43_ Z3_ADR<2> LAN_BASEADR<13> LAN_BASEADR<12>
LAN_BASEADR<11> LAN_BASEADR<10>
PARTITION FB8_1 DQ_DATA<12> DQ_12_IOBUFE DQ_14_IOBUFE EXP44_
LAN_WRH_OBUF EXP45_ LAN_SM_FSM_FFd4 LAN_CS_OBUF
DQ_DATA<6> LAN_RD_OBUF LAN_WRH_S DQ_DATA<14>
EXP46_ DQ_DATA<4> EXP47_ EXP48_
EXP49_ EXP50_
PARTITION FB9_1 LAN_WR_RST LAN_RST_SM_FSM_FFd1 LAN_IRQ_D0 LAN_D_INIT<8>
LAN_D_INIT<1> LAN_CS_RST LAN_A_INIT<6> LAN_RST_SM_FSM_FFd3
LAN_RST_SM_FSM_FFd2 SHUT_UP_Z2<1> Z3_DATA<0> SHUT_UP_Z2<0>
AUTO_CONFIG_Z2_DONE_CYCLE<2> Z3_DATA<1> AUTO_CONFIG_Z2_DONE_CYCLE<1> AUTO_CONFIG_Z2_DONE_CYCLE<0>
Z3_DATA<2> AUTO_CONFIG_Z2_DONE<2>
PARTITION FB10_1 DQ<4>_BUFR.MC DQ_1_IOBUFE DQ_0_IOBUFE EXP51_
DQ_3_IOBUFE DQ_2_IOBUFE EXP52_ DQ_5_IOBUFE
EXP53_ _19_ DQ_7_IOBUFE DQ_6_IOBUFE
EXP54_ _18_ EXP55_ EXP56_
DQ_10_IOBUFE EXP57_
PARTITION FB11_1 LAN_SM_FSM_FFd1 EXP58_ Z3_DATA<3>
PARTITION FB11_5 Z3_DATA<4> EXP59_ LAN_SM_FSM_FFd4 Z3_A_LOW
EXP60_ Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
DQ<8>_BUFR.MC ROM_B_0_OBUF DQ_DATA<8> EXP61_
PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<28>
Z3_DATA<4> Z3_DATA<27> Z3_DATA<22> Z3_DATA<21>
Z3_DATA<20> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
Z3_DATA<19> ROM_B_0_OBUF EXP58_ DQ_DATA<8>
CP_WE_OBUF DQ_DATA<0>
PARTITION FB12_1 CP_BASEADR<4> ROM_B_0_OBUF$BUF4 LAN_BASEADR<14> LAN_BASEADR<13>
DQ_15_IOBUFE LAN_BASEADR<12> LAN_BASEADR<11> DQ_13_IOBUFE
PARTITION FB12_1 EXP59_ ROM_B_0_OBUF$BUF4 LAN_SM_RST EXP60_
DQ_15_IOBUFE LAN_SM_FSM_FFd1 EXP61_ DQ_13_IOBUFE
EXP62_ DQ_11_IOBUFE EXP63_ DQ_9_IOBUFE
EXP64_ EXP65_ EXP66_ LAN_BASEADR<15>
CP_BASEADR<6> CP_BASEADR<5>
PARTITION FB13_1 Z3_ADR<7> CP_RD_OBUF DQ_DATA<1> Z3_ADR<12>
Z3_ADR<11> LAN_WRL_S LAN_D_INIT<1> Z3_DATA<7>
LAN_CS_RST DQ_SWAP LAN_A_INIT<6> LAN_INT_ENABLE
LAN_READY LAN_WRL_OBUF DQ_DATA<9> Z3_ADR<13>
EXP67_ DQ_DATA<7>
PARTITION FB14_1 CP_ACCESS EXP68_ ROM_B_0_OBUF$BUF2
PARTITION FB14_5 FCS_P_D0 Z3_ADR_1 Z3_ADR_0 Z3_ADR<9>
Z3_ADR<8> Z3_ADR<6> CFOUT_OBUF EXP69_
IDE_ACCESS SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR<5>
Z3_ADR<10> EXP70_
PARTITION FB15_1 DQ_DATA<10> Z3_DATA<31> Z3_DATA<30> EXP71_
DQ_DATA<4> Z3_DATA<29> Z3_DATA<23> EXP72_
EXP73_ DQ_DATA<2> DQ_DATA<12> ROM_B_0_OBUF$BUF10
Z3_DATA<22> Z3_DATA<15> Z3_DATA<14> Z3_DATA<21>
Z3_DATA<13> EXP74_
PARTITION FB16_1 LAN_WRH_S Z3_DATA<12> Z3_DATA<11> Z3_DATA<28>
Z3_DATA<27> Z3_DATA<10> Z3_DATA<26> Z3_DATA<9>
Z3_DATA<25> ROM_B_0_OBUF$BUF3 Z3_DATA<8> EXP75_
DQ_DATA<11> Z3_DATA<20> Z3_DATA<19> Z3_DATA<18>
Z3_DATA<17> DQ_DATA<3>
EXP64_ EXP65_ EXP66_ LAN_ACCESS
EXP67_ DQ_SWAP
PARTITION FB13_1 EXP68_ CP_RD_OBUF Z3_DATA<31> Z3_DATA<23>
LAN_INT_ENABLE EXP69_ DQ_DATA<5> Z3_DATA<7>
EXP70_ EXP71_ DQ_DATA<3> DQ_DATA<15>
EXP72_ LAN_WRL_OBUF EXP73_ DQ_DATA<11>
LAN_WRL_S DQ_DATA<13>
PARTITION FB14_1 EXP74_ D_Z2_OUT<3> ROM_B_0_OBUF$BUF2 Z3_ADR_1
ROM_OE_S IDE_W_S IDE_R_S IDE_ENABLE
CP_WE_S CP_RD_S CFOUT_OBUF AUTO_CONFIG_Z2_DONE<1>
AUTO_CONFIG_Z2_DONE<0> SLAVE_OBUF ROM_B_0_OBUF$BUF1 EXP75_
D_Z2_OUT<0> EXP76_
PARTITION FB15_1 EXP77_ EXP78_ EXP79_ LAN_SM_FSM_FFd3
LAN_SM_FSM_FFd2 EXP80_ Z3_A_LOW DQ_DATA<7>
EXP81_ DQ_DATA<9> EXP82_ ROM_B_0_OBUF$BUF10
LAN_RD_S Z3_DATA<15> Z3_DATA<14> LAN_READY
Z3_DATA<13> DQ_DATA<1>
PARTITION FB16_1 EXP83_ Z3_DATA<12> Z3_DATA<11>
PARTITION FB16_5 Z3_DATA<26> Z3_DATA<10> Z3_DATA<25> Z3_DATA<9>
Z3_DATA<24> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<18>
Z3_DATA<17> Z3_DATA<16> EXP84_ DQ_DATA<10>
DQ_DATA<2> EXP85_
Logic/LAN_IDE/LAN_IDE_CP.jed
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Logic/LAN_IDE/LAN_IDE_CP.mfd
+4155 -4356
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Logic/LAN_IDE/LAN_IDE_CP.nga
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngc
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngd
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngr
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.pad
+2 -2
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-28-2019 10:58PM
3- 7-2019 11:51PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
@@ -118,7 +118,7 @@ P97|A<16>|I/O|I/O|BIDIR|||||||||
P98|TIE||I/O||||||||||
P99|GND||GND||||||||||
P100|OVR|O|I/O|OUTPUT|||||||||
P101|TIE||I/O||||||||||
P101|MTCR|I|I/O|INPUT|||||||||
P102|C3|I|I/O|INPUT|||||||||
P103|C1|I|I/O|INPUT|||||||||
P104|CFIN|I|I/O|INPUT|||||||||
Logic/LAN_IDE/LAN_IDE_CP.pnx
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.rpt
+2089 -2290
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Logic/LAN_IDE/LAN_IDE_CP.syr
+93 -90
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@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Compact
FSM Encoding Algorithm : Gray
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -56,7 +56,7 @@ Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -71,7 +71,7 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : OPT
Setting FSM Encoding Algorithm to : Gray
=========================================================================
@@ -110,22 +110,22 @@ INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP>
Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_CYCLE_IN_PROGRESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:647 - Input <BERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_BASEADR<7:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CONFIG_READY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
| States | 13 |
| Transitions | 26 |
| Inputs | 9 |
| Transitions | 19 |
| Inputs | 4 |
| Outputs | 14 |
| Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) |
| Reset | LAN_SM_RST (positive) |
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
@@ -139,7 +139,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -167,32 +167,31 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 183.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 179.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CP_ACCESS>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 295.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 292.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 637.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
Found 1-bit register for signal <FCS_N_D0>.
Found 1-bit register for signal <FCS_P_D0>.
Found 1-bit register for signal <FCS_SM_P_D0>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 264.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 302.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 299.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <INT_VECTOR_CYCLE>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 271.
Found 8-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 263.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
@@ -201,8 +200,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 419.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 423.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 389.
Found 1-bit register for signal <LAN_SM_RST>.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
@@ -213,7 +212,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 32-bit register for signal <Z3_DATA>.
Summary:
inferred 2 Finite State Machine(s).
inferred 77 D-type flip-flop(s).
inferred 59 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
inferred 58 Tristate(s).
@@ -224,18 +223,17 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Registers : 86
1-bit register : 78
# Registers : 71
1-bit register : 62
14-bit register : 2
16-bit register : 2
16-bit register : 3
3-bit register : 1
4-bit register : 1
8-bit register : 2
# Comparators : 6
16-bit comparator equal : 1
2-bit comparator less : 2
4-bit comparator less : 1
8-bit comparator equal : 2
8-bit comparator equal : 3
# Tristates : 28
1-bit tristate buffer : 26
16-bit tristate buffer : 2
@@ -248,37 +246,37 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with compact encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 100
clr | 101
clr_commit | 111
wait1 | 001
set | 011
set_commit | 010
done | 110
wait0 | 001
clr | 011
clr_commit | 010
wait1 | 110
set | 111
set_commit | 101
done | 100
------------------------
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with compact encoding.
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with gray encoding.
-------------------------------
State | Encoding
-------------------------------
nop | 0000
start_read_upper | unreached
wait_read_upper | 1111
end_read_upper | 1100
start_read_lower | 0110
wait_read_lower | 0111
end_read_lower | 0001
start_write_upper | 1011
wait_write_upper | 1110
end_write_upper | 0100
start_write_lower | 0011
wait_write_lower | 1101
wait_cycle_end | 0010
config_rw | 0101
wait_read_upper | 0011
end_read_upper | 0101
start_read_lower | 0100
wait_read_lower | 0010
end_read_lower | 1100
start_write_upper | 0110
wait_write_upper | 1101
end_write_upper | 1111
start_write_lower | 0111
wait_write_lower | 1110
end_write_lower | 1010
config_rw | 0001
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
@@ -308,11 +306,10 @@ Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 76
Flip-Flops : 76
# Registers : 59
Flip-Flops : 59
# Comparators : 3
16-bit comparator equal : 1
8-bit comparator equal : 2
8-bit comparator equal : 3
=========================================================================
@@ -341,35 +338,43 @@ WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <LAN_BASEADR_7> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_6> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_5> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_4> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_3> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_2> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_1> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_0> of sequential type is unconnected in block <LAN_IDE_CP>.
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11>
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=s : D_Z2_OUT_2
implementation constraint: INIT=s : D_Z2_OUT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
=========================================================================
* Partition Report *
@@ -401,42 +406,40 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 1292
# AND2 : 404
# AND3 : 63
# AND4 : 17
# BELS : 1402
# AND2 : 452
# AND3 : 66
# AND4 : 23
# AND5 : 1
# AND6 : 2
# AND7 : 1
# AND8 : 4
# AND8 : 3
# GND : 1
# INV : 480
# OR2 : 250
# OR3 : 34
# OR4 : 1
# XOR2 : 34
# FlipFlops/Latches : 142
# FD : 3
# FDC : 22
# INV : 532
# OR2 : 243
# OR3 : 53
# OR4 : 3
# XOR2 : 25
# FlipFlops/Latches : 134
# FD : 4
# FDC : 21
# FDCE : 7
# FDP : 41
# FDPE : 69
# IO Buffers : 114
# IBUF : 23
# FDPE : 61
# IO Buffers : 115
# IBUF : 24
# IOBUFE : 48
# OBUF : 33
# OBUFE : 10
=========================================================================
Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.75 secs
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.07 secs
-->
Total memory usage is 4534768 kilobytes
Total memory usage is 4534748 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 48 ( 0 filtered)
Number of warnings : 56 ( 0 filtered)
Number of infos : 10 ( 0 filtered)
Logic/LAN_IDE/LAN_IDE_CP.tspec
+510 -502
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.vhd
+35 -78
View File
@@ -107,7 +107,7 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
wait_cycle_end,
end_write_lower,
config_rw
);
@@ -135,6 +135,7 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
@@ -144,12 +145,6 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
@@ -160,6 +155,7 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
signal INT_VECTOR_CYCLE: std_logic;
signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
@@ -249,37 +245,38 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(--AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
INT_VECTOR_CYCLE <='0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
INT_VECTOR_CYCLE <= not MTCR; --is this s special int vector cycle?!?
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
--if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(Z3='1' and (D(15 downto 8) ) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(--FCS ='0' or
reset='0')then
if(reset='0' or FCS='1')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
@@ -292,14 +289,14 @@ begin
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' and LAN_ACCESS = '0')then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' and LAN_ACCESS = '0' )then
IDE_ACCESS <= '1';
else
IDE_ACCESS <= '0';
@@ -337,7 +334,7 @@ begin
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or INT_VECTOR_CYCLE ='1') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
@@ -345,30 +342,10 @@ begin
end if;
end process lan_rst_gen;
fcs_pos_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_P_D0 <='0';
elsif(rising_edge(FCS)) then
FCS_P_D0 <= not FCS_P_D0; --toggle
end if;
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset )
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
if(reset = '0' ) then
if(LAN_SM_RST ='1' ) then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
@@ -377,9 +354,6 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
FCS_SM_P_D0 <='0';
FCS_SM_N_D0 <='0';
LAN_CYCLE_IN_PROGRESS <='0';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -387,13 +361,6 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
FCS_SM_N_D0 <= FCS_N_D0; --store edge state
FCS_SM_P_D0 <= FCS_P_D0; --store edge state
if(LAN_ACCESS = '1' and FCS_SM_N_D0 /= FCS_N_D0) then
LAN_CYCLE_IN_PROGRESS <='1';
elsif(FCS_SM_P_D0 /= FCS_P_D0) then
LAN_CYCLE_IN_PROGRESS <='0';
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -416,7 +383,6 @@ begin
end if;
end if;
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
@@ -435,9 +401,6 @@ begin
LAN_SM <= start_write_lower;
end if;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
@@ -453,7 +416,7 @@ begin
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM <= end_read_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
@@ -475,7 +438,7 @@ begin
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
@@ -493,7 +456,7 @@ begin
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM <= end_write_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
@@ -507,14 +470,10 @@ begin
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_READY <='1';
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
LAN_SM<=end_write_lower; -- stay here until cylce end
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
@@ -522,7 +481,7 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM <= wait_cycle_end;
LAN_SM<=config_rw; -- stay here until cylce end
end case;
end if;
end process lan_rw_gen;
@@ -608,18 +567,16 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with index 0 but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
if(RW='0' and AUTO_CONFIG_Z2_DONE(0)='1')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
@@ -696,7 +653,7 @@ begin
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= 'Z'; --'0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
@@ -745,7 +702,7 @@ begin
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
@@ -756,7 +713,7 @@ begin
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS when AS='0' else '1';
CP_CS <= not CP_ACCESS;
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.vhd.bak
+85 -31
View File
@@ -107,7 +107,7 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
wait_cycle_end,
config_rw
);
@@ -144,6 +144,14 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal INT6_SIG:STD_LOGIC;
signal INT2_SIG:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
@@ -172,6 +180,7 @@ architecture Behavioral of LAN_IDE_CP is
begin
Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
Z3_DS <= UDS & LDS & DS1 & DS0;
AMIGA_CLK <= not (C1 xor C3);
DS <= UDS and LDS;
@@ -242,8 +251,7 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
@@ -252,28 +260,26 @@ begin
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if((D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(FCS ='0' or
reset='0')then
if(reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
@@ -302,13 +308,16 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
--interrupt sampling to avoid ghost interrupts
int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
@@ -325,7 +334,7 @@ begin
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
end process int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
@@ -339,10 +348,30 @@ begin
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
fcs_pos_edge_detect: process(reset, FCS)
begin
if(LAN_SM_RST ='1' ) then
if(reset ='0') then
FCS_P_D0 <='0';
elsif(rising_edge(FCS)) then
FCS_P_D0 <= not FCS_P_D0; --toggle
end if;
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset,FCS )
begin
if(reset = '0' or FCS='1') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
@@ -351,6 +380,9 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
FCS_SM_P_D0 <='0';
FCS_SM_N_D0 <='0';
LAN_CYCLE_IN_PROGRESS <='0';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -358,6 +390,13 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
FCS_SM_N_D0 <= FCS_N_D0; --store edge state
FCS_SM_P_D0 <= FCS_P_D0; --store edge state
if(LAN_ACCESS = '1' and FCS_SM_N_D0 /= FCS_N_D0) then
LAN_CYCLE_IN_PROGRESS <='1';
elsif(FCS_SM_P_D0 /= FCS_P_D0) then
LAN_CYCLE_IN_PROGRESS <='0';
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -380,6 +419,7 @@ begin
end if;
end if;
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
@@ -398,6 +438,9 @@ begin
LAN_SM <= start_write_lower;
end if;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
@@ -413,7 +456,7 @@ begin
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
@@ -435,7 +478,7 @@ begin
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
@@ -453,7 +496,7 @@ begin
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
@@ -467,10 +510,14 @@ begin
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
@@ -478,7 +525,7 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
end case;
end if;
end process lan_rw_gen;
@@ -564,7 +611,7 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with index 0 but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
@@ -645,7 +692,7 @@ begin
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
INT6_OUT <= '0' when INT6_SIG = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
@@ -695,24 +742,31 @@ begin
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
cp_rw_gen: process (AMIGA_CLK,reset)
begin
if falling_edge(AMIGA_CLK) then
--default values
if(reset ='0')then
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
INT6_SIG <= '1';
elsif rising_edge(AMIGA_CLK) then
INT6_SIG <= CP_IRQ;
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
else
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
end if;
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
CP_CS <= not CP_ACCESS when AS='0' else '1';
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.vm6
+11689 -12800
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.xml
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.xst
+2 -2
View File
@@ -8,7 +8,7 @@ run
-p xc9500xl
-top LAN_IDE_CP
-opt_mode Speed
-opt_level 1
-opt_level 2
-iuc NO
-keep_hierarchy Yes
-netlist_hierarchy As_Optimized
@@ -17,7 +17,7 @@ run
-bus_delimiter <>
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Compact
-fsm_extract YES -fsm_encoding Gray
-safe_implementation No
-mux_extract Yes
-resource_sharing YES
Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
+21 -21
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Feb 28 22:57:29 2019">
<application stringID="NgdBuild" timeStamp="Thu Mar 07 23:50:43 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -70,38 +70,38 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="63"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="452"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="21"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="41"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="61"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="480"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="532"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="243"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="63"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="452"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="67"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="480"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="532"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="243"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
Logic/LAN_IDE/LAN_IDE_CP_pad.csv
+2 -2
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-28-2019 10:58PM
3- 7-2019 11:51PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
@@ -118,7 +118,7 @@ P97,A<16>,I/O,I/O,BIDIR,,,,,,,,,
P98,TIE,,I/O,,,,,,,,,,
P99,GND,,GND,,,,,,,,,,
P100,OVR,O,I/O,OUTPUT,,,,,,,,,
P101,TIE,,I/O,,,,,,,,,,
P101,MTCR,I,I/O,INPUT,,,,,,,,,
P102,C3,I,I/O,INPUT,,,,,,,,,
P103,C1,I,I/O,INPUT,,,,,,,,,
P104,CFIN,I,I/O,INPUT,,,,,,,,,
1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 2-28-2019 10:58PM 3- 7-2019 11:51PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
118 P103,C1,I,I/O,INPUT,,,,,,,,,
119 P104,CFIN,I,I/O,INPUT,,,,,,,,,
120 P105,CFOUT,O,I/O,OUTPUT,,,,,,,,,
121 P106,SLAVE,O,I/O,OUTPUT,,,,,,,,,
122 P107,OWN,O,I/O,OUTPUT,,,,,,,,,
123 P108,GND,,GND,,,,,,,,,,
124 P109,VCC,,VCCIO,,,,,,,,,,
Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
+22 -22
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Feb 28 22:57:07 2019">
<application stringID="Xst" timeStamp="Thu Mar 07 23:50:26 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -61,7 +61,7 @@
<item DEFAULT="" label="-p" stringID="XST_P" value="xc9500xl"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="LAN_IDE_CP"/>
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="2"/>
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="YES" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="Yes"/>
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
@@ -71,7 +71,7 @@
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Compact"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Gray"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
@@ -79,10 +79,10 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="86">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="78"/>
<item dataType="int" stringID="XST_REGISTERS" value="71">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="62"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
@@ -97,8 +97,8 @@
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_REGISTERS" value="76">
<item dataType="int" stringID="XST_FLIPFLOPS" value="76"/>
<item dataType="int" stringID="XST_REGISTERS" value="59">
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
</section>
@@ -119,31 +119,31 @@
<item stringID="XST_IOS" value="117"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="1292">
<item dataType="int" stringID="XST_AND2" value="404"/>
<item dataType="int" stringID="XST_AND3" value="63"/>
<item dataType="int" stringID="XST_AND4" value="17"/>
<item dataType="int" stringID="XST_BELS" value="1402">
<item dataType="int" stringID="XST_AND2" value="452"/>
<item dataType="int" stringID="XST_AND3" value="66"/>
<item dataType="int" stringID="XST_AND4" value="23"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="480"/>
<item dataType="int" stringID="XST_OR2" value="250"/>
<item dataType="int" stringID="XST_XOR2" value="34"/>
<item dataType="int" stringID="XST_INV" value="532"/>
<item dataType="int" stringID="XST_OR2" value="243"/>
<item dataType="int" stringID="XST_XOR2" value="25"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="142">
<item dataType="int" stringID="XST_FD" value="3"/>
<item dataType="int" stringID="XST_FDC" value="22"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="134">
<item dataType="int" stringID="XST_FD" value="4"/>
<item dataType="int" stringID="XST_FDC" value="21"/>
<item dataType="int" stringID="XST_FDCE" value="7"/>
<item dataType="int" stringID="XST_FDP" value="41"/>
<item dataType="int" stringID="XST_FDPE" value="69"/>
<item dataType="int" stringID="XST_FDPE" value="61"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="114">
<item dataType="int" stringID="XST_IBUF" value="23"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="115">
<item dataType="int" stringID="XST_IBUF" value="24"/>
<item dataType="int" stringID="XST_OBUF" value="33"/>
</item>
</section>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="48"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="56"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
</section>
</application>
Logic/LAN_IDE/_ngo/netlist.lst
+1 -1
View File
@@ -1,2 +1,2 @@
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551391041
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551999035
OK
Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
-3
View File
@@ -17,9 +17,6 @@
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">IDE_WAIT</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">MTCR</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ&lt;8&gt;</arg> to allow all signals assigned to this function block to be placed.
</msg>
Logic/LAN_IDE/_xmsgs/xst.xmsgs
+27 -3
View File
@@ -29,13 +29,13 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">BERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_SM_RST</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_BASEADR&lt;7:0&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_CYCLE_IN_PROGRESS</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">CONFIG_READY</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="1799" delta="old" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM &lt;<arg fmt="%s" index="2">LAN_SM</arg>&gt;.
@@ -173,6 +173,30 @@
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">LAN_A_INIT_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">LAN_IDE_CP</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">LAN_D_INIT_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;LAN_D_INIT_10&gt; &lt;LAN_D_INIT_11&gt; </arg>
</msg>
Logic/LAN_IDE/area.xds
+2 -2
View File
@@ -7,8 +7,8 @@
<Properties>
<property name="Synthesize - XST:Optimization Goal" value="Speed"/>
<property name="Synthesize - XST:Optimization Effort" value="Normal"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Compact"/>
<property name="Synthesize - XST:Optimization Effort" value="High"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Gray"/>
<property name="Synthesize - XST:Safe Implementation" value="No"/>
<property name="Synthesize - XST:Case Implementation Style" value="None"/>
</Properties>
Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
+2 -2
View File
@@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-02-28T21:24:44</DateModified>
<DateModified>2019-03-07T21:05:55</DateModified>
<ModuleName>LAN_IDE_CP</ModuleName>
<SummaryTimeStamp>2019-02-23T22:34:10</SummaryTimeStamp>
<SummaryTimeStamp>2019-02-28T22:58:23</SummaryTimeStamp>
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\</ImplementationReportsDirectory>
<DateInitialized>2016-12-13T22:08:29</DateInitialized>
Logic/LAN_IDE/log.txt
+4840 -3295
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/webtalk_pn.xml
+3 -2
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Feb 28 22:57:07 2019">
<application name="pn" timeStamp="Thu Mar 07 23:50:25 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -18,7 +18,8 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthFsmEncode" value="Compact" type="process"/>
<property name="PROP_SynthFsmEncode" value="Gray" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd
BIN
View File
Binary file not shown.
Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
+10
View File
@@ -2,3 +2,13 @@ xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/L
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
+73 -73
View File
@@ -57,7 +57,6 @@ CP_CS S:PIN34
CP_RD S:PIN71
CP_WE S:PIN70
DQ<0> S:PIN118
DQ<10> S:PIN129
DQ<11> S:PIN115
DQ<12> S:PIN130
DQ<13> S:PIN113
@@ -65,13 +64,6 @@ DQ<14> S:PIN131
DQ<15> S:PIN112
DQ<1> S:PIN117
DQ<2> S:PIN120
DQ<3> S:PIN119
DQ<4> S:PIN124
DQ<5> S:PIN121
DQ<6> S:PIN126
DQ<7> S:PIN125
DQ<8> S:PIN128
DQ<9> S:PIN116
D<0> S:PIN2
D<10> S:PIN41
D<11> S:PIN43
@@ -113,85 +105,93 @@ INT2_OUT S:PIN32
DTACK S:PIN85
ROM_OE S:PIN35
SLAVE S:PIN106
DQ<8> S:PIN128
DQ<4> S:PIN124
DQ<10> S:PIN129
DQ<7> S:PIN125
DQ<6> S:PIN126
DQ<5> S:PIN121
DQ<3> S:PIN119
DQ<9> S:PIN116
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_2 D_and0000/D_and0000_D2 $OpTx$FX_DC$172 $OpTx$FX_DC$141 D_5_IOBUFE
D_4_IOBUFE $OpTx$FX_DC$127 IDE_CS_0_OBUF LAN_WRL_S
IDE_CS_1_OBUF LAN_WRH_S IDE_A_0_OBUF$BUF0 LAN_RD_S
IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 CP_WE_S IDE_R_OBUF
CP_RD_S
PARTITION FB2_2 A_LAN_4_OBUF A_LAN_7_OBUF
PARTITION FB1_1 ROM_OE_S LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd2 LAN_RST_SM_FSM_FFd1
D_5_IOBUFE D_4_IOBUFE LAN_CS_RST IDE_CS_0_OBUF
IDE_W_S IDE_CS_1_OBUF IDE_ENABLE IDE_A_0_OBUF$BUF0
DS_D IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 CP_WE_S
IDE_R_OBUF DQ<7>_BUFR.MC
PARTITION FB2_1 DQ<10>_BUFR.MC A_LAN_4_OBUF A_LAN_7_OBUF
PARTITION FB2_5 A_LAN_6_OBUF ROM_B_0_OBUF$BUF6
PARTITION FB2_8 ROM_B_0_OBUF$BUF5
PARTITION FB2_10 D_6_IOBUFE
PARTITION FB2_12 D_3_IOBUFE
PARTITION FB2_14 D_7_IOBUFE D_1_IOBUFE $OpTx$FX_SC$167 D_8_IOBUFE
$OpTx$FX_DC$152
PARTITION FB3_2 IDE_W_OBUF
PARTITION FB3_7 DQ_and0001/DQ_and0001_D2 DQ_and0000/DQ_and0000_D2 $OpTx$FX_DC$126 LAN_BASEADR<5>
LAN_BASEADR<4> LAN_BASEADR<3> LAN_BASEADR<1> ROM_B_0_OBUF$BUF8
CP_BASEADR<5> CP_BASEADR<3> CP_BASEADR<1> CP_BASEADR<0>
PARTITION FB4_1 Dout1<1> D_0_IOBUFE
PARTITION FB2_12 D_3_IOBUFE $OpTx$INV$87__$INT D_7_IOBUFE D_1_IOBUFE
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST D_8_IOBUFE EXP30_
PARTITION FB3_1 EXP31_ IDE_W_OBUF EXP32_ EXP33_
EXP34_ BUF_cp EXP35_
PARTITION FB3_10 EXP36_ EXP37_ lancp EXP38_
ROM_B_0_OBUF$BUF8 autoconfig CP_WE_QUIRK EXP39_
ide
PARTITION FB4_2 D_0_IOBUFE
PARTITION FB4_5 A_LAN_1_OBUF A_LAN_0_OBUF
PARTITION FB4_8 A_LAN_3_OBUF
PARTITION FB4_12 A_LAN_2_OBUF
PARTITION FB4_14 A_LAN_5_OBUF $OpTx$FX_DC$195 Dout1<2> EXP22_
EXP23_
PARTITION FB5_2 CP_CS_OBUF
PARTITION FB5_5 ROM_OE_OBUF
PARTITION FB5_10 D_2_IOBUFE $OpTx$FX_DC$154 D_9_IOBUFE lan_adr
D_10_IOBUFE D_11_IOBUFE ide D_12_IOBUFE
lancp
PARTITION FB6_2 LAN_CFG_2_OBUF A_LAN_12_OBUF
PARTITION FB4_14 A_LAN_5_OBUF SHUT_UP<0> LAN_BASEADR<1> IDE_BASEADR<1>
CP_BASEADR<1>
PARTITION FB5_1 EXP40_ CP_CS_OBUF EXP41_ EXP42_
ROM_OE_OBUF
PARTITION FB5_10 D_2_IOBUFE
PARTITION FB5_12 D_9_IOBUFE
PARTITION FB5_14 D_10_IOBUFE D_11_IOBUFE EXP43_ D_12_IOBUFE
EXP44_
PARTITION FB6_1 EXP45_ LAN_CFG_2_OBUF A_LAN_12_OBUF
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF
PARTITION FB6_8 A_LAN_11_OBUF
PARTITION FB6_10 A_LAN_8_OBUF
PARTITION FB6_13 cp_and0000/cp_and0000_D2 A_LAN_9_OBUF A_LAN_9_or0001/A_LAN_9_or0001_D2 $OpTx$FX_DC$137
autoconfig lan_adr_sw
PARTITION FB7_3 D_13_IOBUFE
PARTITION FB7_5 D_14_IOBUFE
PARTITION FB7_8 $OpTx$FX_DC$174 $OpTx$FX_DC$160 ROM_OE_S IDE_W_S
D_15_IOBUFE IDE_R_S IDE_ENABLE D_9_IOBUFE/D_9_IOBUFE_TRST
DS_D AUTO_CONFIG_DONE<1> AUTO_CONFIG_DONE<0>
PARTITION FB8_2 DQ_12_IOBUFE DQ_14_IOBUFE
PARTITION FB8_5 LAN_WRH_OBUF
PARTITION FB8_8 LAN_CS_OBUF
PARTITION FB8_10 LAN_RD_OBUF
PARTITION FB8_14 LAN_IRQ_D0 LAN_INT_ENABLE CP_BASEADR<6> CP_BASEADR<4>
LAN_IRQ_OUT
PARTITION FB9_1 cp_and0001/cp_and0001_D2 EXP24_
PARTITION FB9_17 SHUT_UP<2>/SHUT_UP<2>_CLKF EXP25_
PARTITION FB10_2 DQ_1_IOBUFE DQ_0_IOBUFE
PARTITION FB10_5 DQ_3_IOBUFE DQ_2_IOBUFE
PARTITION FB10_8 DQ_5_IOBUFE
PARTITION FB10_10 DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
PARTITION FB10_14 DQ_8_IOBUFE
PARTITION FB10_16 $OpTx$FX_DC$129 DQ_10_IOBUFE DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
PARTITION FB11_10 CP_WE_QUIRK $OpTx$FX_DC$180 ROM_B_0_OBUF$BUF7 $OpTx$FX_DC$159
ROM_B_0_OBUF $OpTx$FX_DC$153 LAN_BASEADR<2> CP_WE_OBUF
CP_BASEADR<2>
PARTITION FB12_2 ROM_B_0_OBUF$BUF4
PARTITION FB12_5 DQ_15_IOBUFE
PARTITION FB12_8 DQ_13_IOBUFE lancp/lancp_RSTF DQ_11_IOBUFE SHUT_UP<2>
DQ_9_IOBUFE IDE_BASEADR<7> IDE_BASEADR<5> IDE_BASEADR<4>
IDE_BASEADR<3> IDE_BASEADR<2> IDE_BASEADR<1>
PARTITION FB6_10 A_LAN_8_OBUF EXP46_ lan_adr EXP47_
A_LAN_9_OBUF EXP48_ EXP49_ lan_adr_sw
EXP50_
PARTITION FB7_1 Dout1<1> EXP51_ D_13_IOBUFE EXP52_
D_14_IOBUFE EXP53_ EXP54_ EXP55_
Dout1<2> EXP56_ EXP57_ D_15_IOBUFE
EXP58_ EXP59_ Dout1<0> EXP60_
EXP61_ EXP62_
PARTITION FB8_1 EXP63_ DQ_12_IOBUFE DQ_14_IOBUFE EXP64_
LAN_WRH_OBUF DQ<6>_BUFR.MC EXP65_ LAN_CS_OBUF
EXP66_ LAN_RD_OBUF LAN_INT_ENABLE EXP67_
EXP68_ DQ<9>_BUFR.MC DQ<4>_BUFR.MC EXP69_
LAN_RD_S EXP70_
PARTITION FB9_1 EXP71_ $OpTx$FX_DC$144 EXP72_ EXP73_
PARTITION FB9_15 EXP74_ EXP75_ $OpTx$FX_DC$145 EXP76_
PARTITION FB10_1 EXP77_ DQ_1_IOBUFE DQ_0_IOBUFE EXP78_
_24_ DQ_2_IOBUFE EXP79_ _23_
EXP80_ _19_ _21_ _22_
PARTITION FB10_14 _18_ DQ<8>_BUFR.MC EXP81_ _20_
EXP82_
PARTITION FB11_8 SHUT_UP<1> LAN_BASEADR<7> LAN_BASEADR<6> LAN_BASEADR<5>
ROM_B_0_OBUF$BUF7 IDE_BASEADR<7> ROM_B_0_OBUF IDE_BASEADR<6>
CP_BASEADR<7> CP_WE_OBUF CP_BASEADR<6>
PARTITION FB12_1 EXP83_ ROM_B_0_OBUF$BUF4 EXP84_ EXP85_
DQ_15_IOBUFE LAN_WRL_S EXP86_ DQ_13_IOBUFE
LAN_WRH_S DQ_11_IOBUFE EXP87_ _25_
IDE_R_S LAN_IRQ_OUT CP_RD_S DQ<3>_BUFR.MC
EXP88_ DQ<5>_BUFR.MC
PARTITION FB13_2 CP_RD_OBUF
PARTITION FB13_5 SHUT_UP<0> LAN_WR_RST LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd1
LAN_RST_SM_FSM_FFd2 LAN_CS_RST LAN_BASEADR<7> LAN_BASEADR<6>
LAN_BASEADR<0> LAN_WRL_OBUF ROM_B_0_OBUF$BUF0 IDE_BASEADR<6>
IDE_BASEADR<0> CP_BASEADR<7>
PARTITION FB14_1 EXP26_ Dout1<0> ROM_B_0_OBUF$BUF2
PARTITION FB14_9 $OpTx$FX_DC$158 $OpTx$FX_DC$157 CFOUT_OBUF $OpTx$FX_DC$156
AUTO_CONFIG_DONE_CYCLE<0> SLAVE_OBUF ROM_B_0_OBUF$BUF1 AUTO_CONFIG_DONE_CYCLE<1>
EXP27_ Dout1<3>
PARTITION FB15_1 $OpTx$FX_DC$206 EXP28_
PARTITION FB15_12 ROM_B_0_OBUF$BUF9
PARTITION FB15_17 SHUT_UP<1> EXP29_
PARTITION FB13_9 LAN_BASEADR<4> LAN_BASEADR<3> IDE_BASEADR<5> IDE_BASEADR<4>
IDE_BASEADR<3> LAN_WRL_OBUF ROM_B_0_OBUF$BUF0 CP_BASEADR<5>
CP_BASEADR<4> CP_BASEADR<3>
PARTITION FB14_1 AUTO_CONFIG_DONE_CYCLE<0> EXP89_ ROM_B_0_OBUF$BUF2
PARTITION FB14_6 AUTO_CONFIG_DONE<1> AUTO_CONFIG_DONE<0> LAN_BASEADR<2> LAN_BASEADR<0>
IDE_BASEADR<2> CFOUT_OBUF IDE_BASEADR<0> CP_BASEADR<2>
SLAVE_OBUF ROM_B_0_OBUF$BUF1 CP_BASEADR<0> EXP90_
AUTO_CONFIG_DONE_CYCLE<1>
PARTITION FB15_1 Dout1<3> EXP91_
PARTITION FB15_12 ROM_B_0_OBUF$BUF9 lancp/lancp_RSTF__$INT LAN_WR_RST SHUT_UP<2>/SHUT_UP<2>_CLKF
LAN_IRQ_D0 SHUT_UP<2> EXP92_
PARTITION FB16_10 ROM_B_0_OBUF$BUF3
PARTITION FB16_15 EXP30_ EXP31_ cp_and0002/cp_and0002_D2 EXP32_
Logic/LAN_IDE_V2/LAN_IDE_CP.jed
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Logic/LAN_IDE_V2/LAN_IDE_CP.mfd
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Logic/LAN_IDE_V2/LAN_IDE_CP.nga
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Logic/LAN_IDE_V2/LAN_IDE_CP.ngd
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Logic/LAN_IDE_V2/LAN_IDE_CP.pad
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-21-2019 1:44PM
3- 2-2019 7:56PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
Logic/LAN_IDE_V2/LAN_IDE_CP.rpt
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Logic/LAN_IDE_V2/LAN_IDE_CP.syr
+33 -33
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@@ -3,14 +3,14 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: LAN_IDE_CP.prj
@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Compact
FSM Encoding Algorithm : Gray
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -56,7 +56,7 @@ Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -71,26 +71,25 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : OPT
Setting FSM Encoding Algorithm to : Gray
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
Entity <LAN_IDE_CP> compiled.
Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
Architecture behavioral of Entity lan_ide_cp is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -121,7 +120,7 @@ WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected
| Reset type | synchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -206,18 +205,18 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with compact encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 100
clr | 101
clr_commit | 111
wait1 | 001
set | 011
set_commit | 010
done | 110
wait0 | 001
clr | 011
clr_commit | 010
wait1 | 110
set | 111
set_commit | 101
done | 100
------------------------
=========================================================================
@@ -273,19 +272,20 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 964
# AND2 : 222
# AND3 : 78
# AND4 : 12
# AND5 : 5
# BELS : 904
# AND2 : 207
# AND3 : 75
# AND4 : 9
# AND5 : 2
# AND6 : 1
# AND8 : 4
# AND8 : 3
# GND : 1
# INV : 407
# OR2 : 196
# OR3 : 9
# INV : 374
# OR2 : 182
# OR3 : 20
# OR4 : 2
# VCC : 1
# XOR2 : 28
# XOR2 : 27
# FlipFlops/Latches : 60
# FD : 11
# FDC : 6
@@ -300,12 +300,12 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.23 secs
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.51 secs
-->
Total memory usage is 4534756 kilobytes
Total memory usage is 4534796 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 7 ( 0 filtered)
Logic/LAN_IDE_V2/LAN_IDE_CP.tspec
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@@ -1,15 +1,12 @@
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_CS_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_CS_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_CS_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_CS_RST.D:400
Logic/LAN_IDE_V2/LAN_IDE_CP.vm6
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<html>
<head>
<title></title>
</head>
<frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" col="*">
<frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
<frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
<frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
<frame name="content" src="summary.htm">
</frameset>
<frame name="eqns" src="eqns.htm" scrolling="no">
</frameset>
</html>
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<form><span class="pgRef"><table width="90%" align="center"><tr>
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
</tr></table></span></form>
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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
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<meta name=date content="05 1, 2002 4:24:59 PM">
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p.WebHelpNavBar {text-align:right;}
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</head>
<!--(Body)==========================================================-->
<body>
<h1>Text Report</h1>
<p class="whs1">Selecting Text
Report from the left-hand frame will give you a printable text version
of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It
contains sections similar to those of the XML report (a summary section,
errors and warnings, mapped logic, function blocks, function block details,
a text-graphical display of the pinout, and a summary of compiler options),
but it is not easily navigable. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It
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Logic/LAN_IDE_V2/LAN_IDE_CP_html/fit/blank.gif
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<html>
<head>
<script src="XilinxD.js"> </script>
<script src="plugin.js"> </script>
</head>
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
</body>
</html>
Logic/LAN_IDE_V2/LAN_IDE_CP_html/fit/checkNS4.htm
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<html>
<head>
<script src="xilinxD.js"> </script>
<script src="ns4plugin.js"> </script>
</head>
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
</body>
</html>
Logic/LAN_IDE_V2/LAN_IDE_CP_html/fit/defeqns.htm
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<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
<h3 align='center'>Equations</h3>
<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
<tr><td>
</td></tr><tr><td>
********** Mapped Logic **********
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$126 <= (LDS AND UDS);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$127 <= (lan_adr AND lan_adr_sw);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$129 <= (RW AND NOT AS);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$137 <= ((NOT LAN_RST_SM_FSM_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$141 <= (CP_CS AND NOT $OpTx$FX_DC$127);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$152 <= ((D_and0000/D_and0000_D2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (ide AND $OpTx$FX_DC$129 AND $OpTx$FX_DC$141));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$153 <= ((DQ_and0000/DQ_and0000_D2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT AS AND $OpTx$FX_DC$127 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT DQ_and0001/DQ_and0001_D2));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$154 <= ($OpTx$FX_DC$127 AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$156 <= (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND A(3) AND A(6) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DS_D AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$157 <= (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0) AND A(3) AND A(6) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DS_D AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$158 <= (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND A(3) AND A(6) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DS_D AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$159 <= ((NOT DQ_and0000/DQ_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DQ_and0001/DQ_and0001_D2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT AS AND $OpTx$FX_DC$127 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT DQ_and0000/DQ_and0000_D2));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$160 <= (NOT AS AND autoconfig AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$172 <= (NOT RW AND lan_adr AND A(15) AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$174 <= (NOT AS AND RESET);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$180 <= ((NOT RW AND NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND A(3) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A(6) AND autoconfig AND DS_D AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND A(3) AND A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND DS_D AND CFOUT AND NOT $OpTx$FX_DC$126));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$195 <= (NOT A(4) AND A(2) AND A(1));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$206 <= ((SHUT_UP(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(0) AND NOT A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(0) AND A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(1) AND NOT A(17))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(1) AND A(17))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(2) AND A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (SHUT_UP(1).EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(2) AND NOT A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(3) AND NOT A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(3) AND A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(6) AND NOT A(22))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(6) AND A(22))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(4) AND NOT A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(4) AND A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(5) AND NOT A(21))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT IDE_BASEADR(5) AND A(21)));
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_SC$167 <= ((NOT D_and0000/D_and0000_D2 AND NOT $OpTx$FX_DC$129)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ide AND NOT D_and0000/D_and0000_D2 AND $OpTx$FX_DC$141));
</td></tr><tr><td>
FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,NOT RESET,'0',AS);
</td></tr><tr><td>
FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,NOT RESET,'0',AS);
</td></tr><tr><td>
FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,NOT RESET,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTO_CONFIG_DONE_CYCLE_D(0) <= ((NOT AUTO_CONFIG_DONE_CYCLE(0) AND NOT $OpTx$FX_DC$180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(2) AND AUTO_CONFIG_DONE(0) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE_CYCLE(0) AND NOT AUTOBOOT_OFF)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AUTO_CONFIG_DONE_CYCLE(0) AND A(3) AND A(6) AND autoconfig AND DS_D AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE_CYCLE(0) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A(3) AND A(6) AND autoconfig AND DS_D AND NOT AUTOBOOT_OFF AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$126));
</td></tr><tr><td>
FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,NOT RESET,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTO_CONFIG_DONE_CYCLE_D(1) <= ((NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND A(3) AND A(6) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DS_D AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT AUTO_CONFIG_DONE_CYCLE(1) AND NOT $OpTx$FX_DC$180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(2) AND NOT AUTO_CONFIG_DONE_CYCLE(0) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE_CYCLE(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE_CYCLE(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RW AND NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AUTO_CONFIG_DONE_CYCLE(0) AND AUTO_CONFIG_DONE_CYCLE(1) AND A(3) AND A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND DS_D AND NOT $OpTx$FX_DC$126));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(0) <= NOT ((NOT A(1) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(1) <= NOT ((NOT A(2) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(2) <= NOT (((NOT A(2) AND NOT CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(3) AND CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(3) <= ((A(4) AND CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(3) AND NOT CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(4) <= NOT (((NOT A(5) AND CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(4) AND NOT CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(5) <= NOT (((NOT A(5) AND NOT CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(6) AND CP_CS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(6) <= ((NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(7) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(7) <= NOT ((NOT A(8) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(8) <= NOT ((NOT A(9) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(9) <= NOT ((NOT A(10) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(10) <= NOT ((NOT A(11) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(11) <= NOT ((NOT A(12) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(12) <= NOT ((NOT A(13) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN(13) <= NOT ((NOT A(14) AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
A_LAN_9_or0001/A_LAN_9_or0001_D2 <= ((LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd1));
</td></tr><tr><td>
</td></tr><tr><td>
CFOUT <= NOT ((AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0)));
</td></tr><tr><td>
FDCPE_CP_BASEADR0: FDCPE port map (CP_BASEADR(0),CP_BASEADR_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(0) <= ((D(8).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(0) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR1: FDCPE port map (CP_BASEADR(1),CP_BASEADR_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(1) <= ((D(9).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(1) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR2: FDCPE port map (CP_BASEADR(2),CP_BASEADR_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(2) <= ((D(10).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(2) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR3: FDCPE port map (CP_BASEADR(3),CP_BASEADR_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(3) <= ((D(11).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(3) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR4: FDCPE port map (CP_BASEADR(4),CP_BASEADR_D(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(4) <= ((D(12).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(4) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR5: FDCPE port map (CP_BASEADR(5),CP_BASEADR_D(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(5) <= ((D(13).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(5) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR6: FDCPE port map (CP_BASEADR(6),CP_BASEADR_D(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(6) <= ((D(14).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(6) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_BASEADR7: FDCPE port map (CP_BASEADR(7),CP_BASEADR_D(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_BASEADR_D(7) <= ((D(15).PIN AND $OpTx$FX_DC$157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(7) AND NOT $OpTx$FX_DC$157));
</td></tr><tr><td>
FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,NOT AS,'0',NOT lancp/lancp_RSTF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_CS_D <= (cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cp_and0000/cp_and0000_D2 AND NOT cp_and0002/cp_and0002_D2);
</td></tr><tr><td>
</td></tr><tr><td>
CP_RD <= NOT ((NOT AS AND NOT CP_RD_S));
</td></tr><tr><td>
FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_RD_S_D <= (RW AND NOT CP_CS AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
CP_WE <= NOT ((NOT AS AND NOT CP_WE_S AND CP_WE_QUIRK));
</td></tr><tr><td>
FDCPE_CP_WE_QUIRK: FDCPE port map (CP_WE_QUIRK,CP_WE_S,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
</td></tr><tr><td>
FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CP_WE_S_D <= (NOT RW AND NOT CP_CS AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
</td></tr><tr><td>
D_I(0) <= NOT (((NOT DQ(0).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(8).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(0) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(1) <= NOT (((NOT DQ(1).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(9).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(1) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(2) <= NOT (((NOT DQ(2).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(10).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(2) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(3) <= NOT (((NOT DQ(3).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(11).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(3) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(4) <= NOT (((NOT DQ(4).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(12).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(4) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(5) <= NOT (((NOT DQ(5).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(13).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(5) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(6) <= NOT (((NOT DQ(6).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(14).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(6) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(7) <= NOT (((NOT DQ(7).PIN AND NOT $OpTx$FX_SC$167 AND NOT $OpTx$FX_DC$154)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(15).PIN AND NOT $OpTx$FX_SC$167 AND $OpTx$FX_DC$154)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(7) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(8) <= NOT (((NOT DQ(8).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(0).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(8) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(9) <= NOT (((NOT DQ(9).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(1).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(9) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(10) <= NOT (((NOT DQ(10).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(2).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(10) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(11) <= NOT (((NOT DQ(11).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT DQ(3).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(11) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(12) <= ((Dout1(0) AND $OpTx$FX_SC$167)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(12).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(4).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(12) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(13) <= ((Dout1(1) AND $OpTx$FX_SC$167)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(13).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(5).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(13) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(14) <= ((Dout1(2) AND $OpTx$FX_SC$167)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(14).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(6).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(14) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
D_I(15) <= ((Dout1(3) AND $OpTx$FX_SC$167)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(15).PIN AND $OpTx$FX_DC$152)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (DQ(7).PIN AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$129 AND NOT $OpTx$FX_DC$141));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(15) <= NOT D_9_IOBUFE/D_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(0) <= ((D(8).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(0).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(0) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(1) <= ((D(9).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(1).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(1) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(2) <= ((D(10).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(2).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(2) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(3) <= ((D(11).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(3).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(3) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(4) <= ((A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(12).PIN AND $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(4).PIN AND $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(4) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(5) <= ((D(13).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(5).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(5) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(6) <= ((D(14).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(6).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(6) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(7) <= ((D(15).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$159)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(7).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$159));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(7) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(8) <= NOT (((NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT D(8).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT D(0).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$153)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(8) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(9) <= ((NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(9).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(1).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(9) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(10) <= ((NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(10).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(2).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(10) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(11) <= ((NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(11).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(3).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(11) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(12) <= ((D(12).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(4).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(12) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(13) <= ((D(13).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(5).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(13) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(14) <= ((D(14).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(6).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(14) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_I(15) <= ((D(15).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND NOT $OpTx$FX_DC$153)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (D(7).PIN AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137 AND $OpTx$FX_DC$153));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DQ_OE(15) <= NOT DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
</td></tr><tr><td>
</td></tr><tr><td>
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((RW AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (AS AND NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT lancp AND NOT $OpTx$FX_DC$127 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A_LAN_9_or0001/A_LAN_9_or0001_D2 AND $OpTx$FX_DC$137));
</td></tr><tr><td>
</td></tr><tr><td>
DQ_and0000/DQ_and0000_D2 <= (NOT RW AND NOT AS AND NOT LDS AND UDS AND lancp);
</td></tr><tr><td>
</td></tr><tr><td>
DQ_and0001/DQ_and0001_D2 <= (NOT RW AND NOT AS AND LDS AND NOT UDS AND lancp);
</td></tr><tr><td>
FDCPE_DS_D: FDCPE port map (DS_D,$OpTx$FX_DC$126,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0',RESET);
</td></tr><tr><td>
</td></tr><tr><td>
DTACK_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DTACK_OE <= (NOT AS AND ide AND IDE_WAIT);
</td></tr><tr><td>
</td></tr><tr><td>
D_9_IOBUFE/D_9_IOBUFE_TRST <= ((NOT D_and0000/D_and0000_D2 AND NOT $OpTx$FX_DC$129)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT autoconfig AND NOT ide AND NOT D_and0000/D_and0000_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$141));
</td></tr><tr><td>
</td></tr><tr><td>
D_and0000/D_and0000_D2 <= (lan_adr AND NOT lan_adr_sw AND $OpTx$FX_DC$129);
</td></tr><tr><td>
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Dout1_D(0) <= ((NOT A(5) AND A(4) AND NOT A(2) AND NOT AS AND A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND A(1) AND NOT AS AND A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT AS AND NOT A(3) AND A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(2) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT Dout1(0) AND NOT $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(5) AND NOT A(4) AND A(2) AND NOT A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(4) AND A(2) AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(0) AND NOT A(3) AND NOT A(6) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(5) AND NOT A(4) AND A(2) AND A(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND NOT A(6) AND $OpTx$FX_DC$160));
</td></tr><tr><td>
FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Dout1_D(1) <= ((NOT A(5) AND NOT A(4) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(0) AND NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND NOT A(1) AND NOT AS AND A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND A(2) AND NOT A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AUTO_CONFIG_DONE(1) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND A(1) AND NOT AS AND AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(3) AND NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT Dout1(1) AND NOT $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT AS AND NOT A(3) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND A(2) AND NOT AS AND A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126));
</td></tr><tr><td>
FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Dout1_D(2) <= ((A(2) AND A(6) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(1) AND A(3) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(4) AND NOT A(1) AND NOT A(3) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(2) AND NOT A(1) AND NOT A(6) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(1) AND AUTO_CONFIG_DONE(1) AND NOT A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND A(2) AND A(1) AND NOT AS AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (Dout1(2) AND NOT $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(5) AND $OpTx$FX_DC$160 AND NOT $OpTx$FX_DC$195)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(4) AND NOT A(2) AND $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(4) AND A(3) AND $OpTx$FX_DC$160));
</td></tr><tr><td>
FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Dout1_D(3) <= ((NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND A(1) AND NOT AS AND NOT A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_DONE(1) AND NOT A(3) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(6) AND autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT Dout1(3) AND NOT $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT A(3) AND NOT A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$160)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND A(1) AND NOT AS AND NOT A(3) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT AS AND NOT A(3) AND A(6) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; autoconfig AND NOT $OpTx$FX_DC$126));
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
IDE_A(0) <= A(9);
</td></tr><tr><td>
</td></tr><tr><td>
IDE_A(1) <= A(10);
</td></tr><tr><td>
</td></tr><tr><td>
IDE_A(2) <= A(11);
</td></tr><tr><td>
FDCPE_IDE_BASEADR0: FDCPE port map (IDE_BASEADR(0),IDE_BASEADR_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(0) <= ((D(8).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(0) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR1: FDCPE port map (IDE_BASEADR(1),IDE_BASEADR_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(1) <= ((D(9).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(1) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR2: FDCPE port map (IDE_BASEADR(2),IDE_BASEADR_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(2) <= ((D(10).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(2) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR3: FDCPE port map (IDE_BASEADR(3),IDE_BASEADR_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(3) <= ((D(11).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(3) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR4: FDCPE port map (IDE_BASEADR(4),IDE_BASEADR_D(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(4) <= ((D(12).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(4) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR5: FDCPE port map (IDE_BASEADR(5),IDE_BASEADR_D(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(5) <= ((D(13).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(5) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR6: FDCPE port map (IDE_BASEADR(6),IDE_BASEADR_D(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(6) <= ((D(14).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(6) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
FDCPE_IDE_BASEADR7: FDCPE port map (IDE_BASEADR(7),IDE_BASEADR_D(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_D(7) <= ((D(15).PIN AND $OpTx$FX_DC$158)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (IDE_BASEADR(7) AND NOT $OpTx$FX_DC$158));
</td></tr><tr><td>
</td></tr><tr><td>
IDE_CS(0) <= NOT A(12);
</td></tr><tr><td>
</td></tr><tr><td>
IDE_CS(1) <= NOT A(13);
</td></tr><tr><td>
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET,IDE_ENABLE_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_ENABLE_CE <= (NOT RW AND NOT AS AND ide);
</td></tr><tr><td>
</td></tr><tr><td>
IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));
</td></tr><tr><td>
FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_R_S_D <= (ide AND NOT IDE_ENABLE AND $OpTx$FX_DC$129);
</td></tr><tr><td>
</td></tr><tr><td>
IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));
</td></tr><tr><td>
FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_W_S_D <= (NOT RW AND NOT AS AND ide);
</td></tr><tr><td>
</td></tr><tr><td>
INT2_OUT_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;INT2_OUT <= INT2_OUT_I when INT2_OUT_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;INT2_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
</td></tr><tr><td>
</td></tr><tr><td>
INT6_OUT_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;INT6_OUT <= INT6_OUT_I when INT6_OUT_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;INT6_OUT_OE <= NOT CP_IRQ;
</td></tr><tr><td>
FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),LAN_BASEADR_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(0) <= ((D(8).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(0) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),LAN_BASEADR_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(1) <= ((D(9).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(1) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),LAN_BASEADR_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(2) <= ((D(10).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(2) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),LAN_BASEADR_D(3),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(3) <= ((D(11).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(3) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),LAN_BASEADR_D(4),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(4) <= ((D(12).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(4) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),LAN_BASEADR_D(5),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(5) <= ((D(13).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(5) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),LAN_BASEADR_D(6),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(6) <= ((D(14).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(6) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),LAN_BASEADR_D(7),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_BASEADR_D(7) <= ((D(15).PIN AND $OpTx$FX_DC$156)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(7) AND NOT $OpTx$FX_DC$156));
</td></tr><tr><td>
</td></tr><tr><td>
LAN_CFG(1) <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
LAN_CFG(2) <= '1';
</td></tr><tr><td>
</td></tr><tr><td>
LAN_CFG(3) <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
LAN_CFG(4) <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
LAN_CS <= ((RESET AND lan_adr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND LAN_CS_RST));
</td></tr><tr><td>
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_CS_RST_D <= ((NOT RESET AND LAN_RST_SM_FSM_FFd3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT LAN_RST_SM_FSM_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND NOT LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd1));
</td></tr><tr><td>
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,NOT RESET,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$172)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$172));
</td></tr><tr><td>
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
</td></tr><tr><td>
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_INT_ENABLE AND NOT D(14).PIN AND NOT LAN_INT AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $OpTx$FX_DC$172)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$172));
</td></tr><tr><td>
</td></tr><tr><td>
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$174);
</td></tr><tr><td>
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_RD_S_D <= (RW AND lan_adr AND NOT A(15) AND NOT $OpTx$FX_DC$126);
</td></tr><tr><td>
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_RST_SM_FSM_FFd1_D <= ((NOT RESET AND NOT LAN_RST_SM_FSM_FFd3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND NOT LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd1));
</td></tr><tr><td>
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_RST_SM_FSM_FFd2_D <= ((RESET)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd3 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd1));
</td></tr><tr><td>
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_RST_SM_FSM_FFd3_D <= ((NOT RESET AND NOT $OpTx$FX_DC$137)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND NOT LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd3));
</td></tr><tr><td>
</td></tr><tr><td>
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$174)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_WRH_S AND $OpTx$FX_DC$174));
</td></tr><tr><td>
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_WRH_S_D <= (NOT RW AND NOT LDS AND lan_adr AND NOT A(15));
</td></tr><tr><td>
</td></tr><tr><td>
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$174)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_WRL_S AND $OpTx$FX_DC$174));
</td></tr><tr><td>
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_WRL_S_D <= (NOT RW AND NOT UDS AND lan_adr AND NOT A(15));
</td></tr><tr><td>
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LAN_WR_RST_D <= ((NOT RESET AND LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT RESET AND NOT LAN_RST_SM_FSM_FFd2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd1));
</td></tr><tr><td>
</td></tr><tr><td>
MTACK_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;MTACK_OE <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
OVR_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;OVR <= OVR_I when OVR_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;OVR_OE <= (NOT AS AND ide);
</td></tr><tr><td>
</td></tr><tr><td>
OWN_I <= '0';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;OWN <= OWN_I when OWN_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;OWN_OE <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
ROM_B(0) <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
ROM_B(1) <= '0';
</td></tr><tr><td>
</td></tr><tr><td>
ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S AND NOT AUTOBOOT_OFF));
</td></tr><tr><td>
FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ROM_OE_S_D <= (ide AND IDE_ENABLE AND $OpTx$FX_DC$129);
</td></tr><tr><td>
FDCPE_SHUT_UP0: FDCPE port map (SHUT_UP(0),SHUT_UP_D(0),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHUT_UP_D(0) <= (SHUT_UP(0) AND NOT $OpTx$FX_DC$156);
</td></tr><tr><td>
FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHUT_UP_D(1) <= (SHUT_UP(1) AND NOT $OpTx$FX_DC$157);
</td></tr><tr><td>
</td></tr><tr><td>
SHUT_UP(2)/SHUT_UP(2)_CLKF <= C1
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; XOR
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHUT_UP(2)/SHUT_UP(2)_CLKF <= C3;
</td></tr><tr><td>
FDCPE_SHUT_UP2: FDCPE port map (SHUT_UP(2),SHUT_UP_D(2),SHUT_UP(2)/SHUT_UP(2)_CLKF,'0',NOT RESET);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHUT_UP_D(2) <= (SHUT_UP(2) AND NOT $OpTx$FX_DC$158);
</td></tr><tr><td>
</td></tr><tr><td>
SLAVE <= ((AS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT lan_adr AND NOT autoconfig AND NOT ide AND CP_CS));
</td></tr><tr><td>
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,NOT AS,NOT lancp/lancp_RSTF,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;autoconfig_D <= (A(23) AND A(22) AND A(21) AND A(19) AND NOT A(17) AND NOT A(16) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(18) AND NOT A(20) AND NOT CFIN AND CFOUT);
</td></tr><tr><td>
</td></tr><tr><td>
cp_and0000/cp_and0000_D2 <= (A(23) AND A(22) AND A(21) AND A(19) AND NOT A(17) AND NOT A(16) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT A(18) AND NOT A(20) AND NOT CFIN AND CFOUT);
</td></tr><tr><td>
</td></tr><tr><td>
cp_and0001/cp_and0001_D2 <= ((SHUT_UP(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(4) AND NOT A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(5) AND NOT A(21))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(5) AND A(21))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(7) AND NOT A(23))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(7) AND A(23))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (SHUT_UP(2)/SHUT_UP(2)_CLKF.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(2) AND NOT A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(2) AND A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(3) AND NOT A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(3) AND A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(4) AND A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(0) AND NOT A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(0) AND A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (LAN_BASEADR(1) AND NOT A(17))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT LAN_BASEADR(1) AND A(17)));
</td></tr><tr><td>
</td></tr><tr><td>
cp_and0002/cp_and0002_D2 <= ((SHUT_UP(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (EXP30_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(2) AND NOT A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(2) AND A(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(3) AND NOT A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(3) AND A(19))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(4) AND A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(4) AND NOT A(20))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(5) AND NOT A(21))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(5) AND A(21))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(7) AND NOT A(23))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(7) AND A(23))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(0) AND NOT A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(0) AND A(16))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (CP_BASEADR(1) AND NOT A(17))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT CP_BASEADR(1) AND A(17)));
</td></tr><tr><td>
FDCPE_ide: FDCPE port map (ide,ide_D,NOT AS,NOT lancp/lancp_RSTF,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ide_D <= (cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cp_and0000/cp_and0000_D2 AND cp_and0002/cp_and0002_D2 AND NOT $OpTx$FX_DC$206);
</td></tr><tr><td>
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,NOT AS,NOT lancp/lancp_RSTF,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;lan_adr_D <= (NOT cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cp_and0000/cp_and0000_D2);
</td></tr><tr><td>
FDCPE_lan_adr_sw: FDCPE port map (lan_adr_sw,lan_adr_sw_D,NOT AS,NOT lancp/lancp_RSTF,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;lan_adr_sw_D <= ((NOT A(13) AND NOT cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cp_and0000/cp_and0000_D2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A(14) AND NOT cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cp_and0000/cp_and0000_D2));
</td></tr><tr><td>
FDCPE_lancp: FDCPE port map (lancp,lancp_D,NOT AS,NOT lancp/lancp_RSTF,'0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;lancp_D <= ((cp_and0000/cp_and0000_D2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (cp_and0001/cp_and0001_D2 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cp_and0002/cp_and0002_D2 AND $OpTx$FX_DC$206));
</td></tr><tr><td>
</td></tr><tr><td>
lancp/lancp_RSTF <= (RESET AND BERR);
</td></tr><tr><td>
Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP (Q,D,G,CLR,PRE);
</td></tr><tr><td>
</td></tr>
</table>
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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
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<body>
<h1>Equations</h1>
<p><span style="font-size: 10pt; font-family: arial, sans-serif;">The Equations
page provides a list of equations organized by signal name. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can use the pulldown menu in the left-hand frame of the page to select
ABEL, VHDL, or Verilog as your language of display.</span> </p>
<p><img src="xml8.jpg"
x-maintain-ratio=TRUE
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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
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</head>
<!--(Body)==========================================================-->
<body>
<h1>Errors/Warnings</h1>
<p class="whs1">The Errors/Warnings
section of the report lists all of the error, warning, and information
messages generated by the fitter. By default, this section will display
the number of each kind of message you have and the full text of the messages,
but checkboxes at the top of the screen allow you to filter message details
as you choose. </p>
<p class="whs2">Checking all
the boxes will give you a display like this:</p>
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<p class="whs3">Deselecting
the Warning box in this particular example would result in this less detailed
display:</p>
<p><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' width='576' height='226' border='0'>");}
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<dd>
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time for this report data.</dd>
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Logic/LAN_IDE_V2/LAN_IDE_CP_html/fit/failtabledoc.htm
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<body>
<h1>
Failure Table</h1>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
Failure Table section provides a table listing all logic failing to be
placed as well as the cause for failure to fit for each individual Function
Block. </font>The user can use this table to determine primary cause of
failure and try to correct it.</span><!--begin!kadov{{-->
<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span
style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
Failure Table contains the following:&nbsp;</font></span>
<ul type="disc" class="whs1">
<li class="kadov-p" class="kadov-p">
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
signal name&nbsp;</font></span></li>
</ul>
<div class="whs2"><span style="font-weight: bold;
font-family: arial, sans-serif;
font-size: 10pt;"><font size=-1><b>Note:</span><span
style="font-family: arial, sans-serif; font-size: 10pt;"></b>
Clicking on the signal name will open a new window with the equations for
that signal.&nbsp;</font></span></div>
<ul type="disc" class="whs3">
<li class="kadov-p" class="kadov-p">
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
column for each Function Block in device, with reason for failure to fit
for each FB</font></span></li>
<li class="kadov-p" class="kadov-p">
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
legend at the bottom listing all possible reasons for failure</font></span></li>
</ul>
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