Dominick.Vansevenant/Zorro-LAN-IDE
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CP and LAN working! Clockport needed to be stopped if FCS='1'

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This commit is contained in:
MHeinrichs
2019-03-07 23:53:52 +01:00
parent 943507175a
commit 7936ad431b
161 changed files with 45433 additions and 43327 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP.syr
+33 -33
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@@ -3,14 +3,14 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: LAN_IDE_CP.prj
@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Compact
FSM Encoding Algorithm : Gray
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -56,7 +56,7 @@ Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -71,26 +71,25 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : OPT
Setting FSM Encoding Algorithm to : Gray
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
Entity <LAN_IDE_CP> compiled.
Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
Architecture behavioral of Entity lan_ide_cp is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -121,7 +120,7 @@ WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected
| Reset type | synchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -206,18 +205,18 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with compact encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 100
clr | 101
clr_commit | 111
wait1 | 001
set | 011
set_commit | 010
done | 110
wait0 | 001
clr | 011
clr_commit | 010
wait1 | 110
set | 111
set_commit | 101
done | 100
------------------------
=========================================================================
@@ -273,19 +272,20 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 964
# AND2 : 222
# AND3 : 78
# AND4 : 12
# AND5 : 5
# BELS : 904
# AND2 : 207
# AND3 : 75
# AND4 : 9
# AND5 : 2
# AND6 : 1
# AND8 : 4
# AND8 : 3
# GND : 1
# INV : 407
# OR2 : 196
# OR3 : 9
# INV : 374
# OR2 : 182
# OR3 : 20
# OR4 : 2
# VCC : 1
# XOR2 : 28
# XOR2 : 27
# FlipFlops/Latches : 60
# FD : 11
# FDC : 6
@@ -300,12 +300,12 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.23 secs
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.51 secs
-->
Total memory usage is 4534756 kilobytes
Total memory usage is 4534796 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 7 ( 0 filtered)