Dominick.Vansevenant/Zorro-LAN-IDE
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CP and LAN working! Clockport needed to be stopped if FCS='1'

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This commit is contained in:
MHeinrichs
2019-03-07 23:53:52 +01:00
parent 943507175a
commit 7936ad431b
161 changed files with 45433 additions and 43327 deletions
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Logic/LAN_IDE/LAN_IDE_CP.vhd.bak
+101 -47
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@@ -107,7 +107,7 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
wait_cycle_end,
config_rw
);
@@ -144,6 +144,14 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal INT6_SIG:STD_LOGIC;
signal INT2_SIG:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
@@ -172,6 +180,7 @@ architecture Behavioral of LAN_IDE_CP is
begin
Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
Z3_DS <= UDS & LDS & DS1 & DS0;
AMIGA_CLK <= not (C1 xor C3);
DS <= UDS and LDS;
@@ -242,8 +251,7 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
@@ -251,29 +259,27 @@ begin
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
if((D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(FCS ='0' or
reset='0')then
if(reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
@@ -302,13 +308,16 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
--interrupt sampling to avoid ghost interrupts
int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
@@ -325,7 +334,7 @@ begin
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
end process int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
@@ -339,10 +348,30 @@ begin
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
fcs_pos_edge_detect: process(reset, FCS)
begin
if(LAN_SM_RST ='1' ) then
if(reset ='0') then
FCS_P_D0 <='0';
elsif(rising_edge(FCS)) then
FCS_P_D0 <= not FCS_P_D0; --toggle
end if;
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset,FCS )
begin
if(reset = '0' or FCS='1') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
@@ -351,6 +380,9 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
FCS_SM_P_D0 <='0';
FCS_SM_N_D0 <='0';
LAN_CYCLE_IN_PROGRESS <='0';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -358,6 +390,13 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
FCS_SM_N_D0 <= FCS_N_D0; --store edge state
FCS_SM_P_D0 <= FCS_P_D0; --store edge state
if(LAN_ACCESS = '1' and FCS_SM_N_D0 /= FCS_N_D0) then
LAN_CYCLE_IN_PROGRESS <='1';
elsif(FCS_SM_P_D0 /= FCS_P_D0) then
LAN_CYCLE_IN_PROGRESS <='0';
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -380,23 +419,27 @@ begin
end if;
end if;
if(Z3_ADR(15)='1')then
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
LAN_SM <= start_write_lower;
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
@@ -413,7 +456,7 @@ begin
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
@@ -435,7 +478,7 @@ begin
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
@@ -453,7 +496,7 @@ begin
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
@@ -467,10 +510,14 @@ begin
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
@@ -478,7 +525,7 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
end case;
end if;
end process lan_rw_gen;
@@ -564,7 +611,7 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with index 0 but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
@@ -645,7 +692,7 @@ begin
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
INT6_OUT <= '0' when INT6_SIG = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
@@ -695,24 +742,31 @@ begin
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
cp_rw_gen: process (AMIGA_CLK,reset)
begin
if falling_edge(AMIGA_CLK) then
--default values
if(reset ='0')then
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
INT6_SIG <= '1';
elsif rising_edge(AMIGA_CLK) then
INT6_SIG <= CP_IRQ;
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
else
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
CP_CS <= not CP_ACCESS when AS='0' else '1';
end Behavioral;