Dominick.Vansevenant/Zorro-LAN-IDE
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CP and LAN working! Clockport needed to be stopped if FCS='1'

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This commit is contained in:
MHeinrichs
2019-03-07 23:53:52 +01:00
parent 943507175a
commit 7936ad431b
161 changed files with 45433 additions and 43327 deletions
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Logic/LAN_IDE/LAN_IDE.gise
+17 -9
View File
@@ -32,6 +32,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="LAN_IDE_CP.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="LAN_IDE_CP.pnx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
@@ -42,9 +43,11 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP_build.xml"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_envsettings.html"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="LAN_IDE_CP_html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="LAN_IDE_CP_pad.csv"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
@@ -65,7 +68,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551390224" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1235887333676579674" xil_pn:start_ts="1551390212">
<transform xil_pn:end_ts="1551994116" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5899415373064323687" xil_pn:start_ts="1551994105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -86,7 +89,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551390232" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551390224">
<transform xil_pn:end_ts="1551994125" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1551994116">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
@@ -95,27 +98,33 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1551390285" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551390232">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1551994174" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1551994125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.gyd"/>
<outfile xil_pn:name="LAN_IDE_CP.mfd"/>
<outfile xil_pn:name="LAN_IDE_CP.nga"/>
<outfile xil_pn:name="LAN_IDE_CP.pad"/>
<outfile xil_pn:name="LAN_IDE_CP.pnx"/>
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
<outfile xil_pn:name="LAN_IDE_CP.tim"/>
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
<outfile xil_pn:name="LAN_IDE_CP.vm6"/>
<outfile xil_pn:name="LAN_IDE_CP.xml"/>
<outfile xil_pn:name="LAN_IDE_CP_build.xml"/>
<outfile xil_pn:name="LAN_IDE_CP_html"/>
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1551390161" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1551390159">
<transform xil_pn:end_ts="1551994176" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1551994174">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
</transform>
<transform xil_pn:end_ts="1551386236" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1551386235">
<transform xil_pn:end_ts="1551990706" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1551990706">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1550755464" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1550755461">
@@ -123,7 +132,6 @@
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1551017787" xil_pn:in_ck="-8497105071423008236" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1551017787">
Logic/LAN_IDE/LAN_IDE.xise
+2 -2
View File
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Sequential" xil_pn:valueState="non-default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -111,7 +111,7 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE/LAN_IDE_CP-W.vhd
+268 -252
View File
@@ -107,8 +107,10 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
config_rw
wait_cycle_end,
config_rw,
cp_read,
cp_write_wait
);
signal LAN_RST_SM: lan_reset :=nop;
@@ -122,7 +124,7 @@ architecture Behavioral of LAN_IDE_CP is
signal ROM_OE_S: STD_LOGIC;
signal CP_ACCESS: STD_LOGIC;
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
signal LAN_ACCESS: STD_LOGIC;
signal DQ_SWAP: STD_LOGIC;
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
@@ -135,7 +137,6 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
@@ -145,10 +146,19 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal INT6_SIG:STD_LOGIC;
signal INT2_SIG:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal CP_WAIT:STD_LOGIC_VECTOR(3 downto 0);
signal AMIGA_CLK:STD_LOGIC;
signal DS:STD_LOGIC;
@@ -244,41 +254,48 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(--AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
DQ_SWAP <= '0';
Z3_ADR <= (others => '1');
CP_ACCESS <= '0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--if((D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(D(15 downto 8) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
--CP base
--if((D(15 downto 8) & A(23 downto 16)) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
if(D(15 downto 8) = CP_BASEADR(15 downto 8) and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(--FCS ='0' or
reset='0')then
if(reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
elsif(falling_edge(AS))then
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
@@ -287,12 +304,7 @@ begin
AUTOCONFIG_Z2_ACCESS <= '0';
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
@@ -304,187 +316,7 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
if( LAN_INT ='1' --or --no interupt
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
)then
LAN_IRQ_OUT <='1';
elsif(
(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
) then
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
end if;
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
if(LAN_SM_RST ='1' ) then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
end case;
end if;
end process lan_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
begin
@@ -494,7 +326,7 @@ begin
D_Z2_OUT<="1111";
SHUT_UP_Z2 <="111";
IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
CP_BASEADR<=x"FFFF";
AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
@@ -507,7 +339,7 @@ begin
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
else
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
@@ -531,19 +363,19 @@ begin
when "000101" => --er_flags (Z3)
D_Z2_OUT <= "1101" ; -- io device no size extension 64kb subsize
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
when "001001" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0101" ; --Ventor ID 1
else
D_Z2_OUT <= "0111" ; --Ventor ID 1
end if;
end if;
when "001010" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "1110" ; --Ventor ID 2
else
D_Z2_OUT <= "1101" ; --Ventor ID 2
end if;
end if;
when "001011" =>
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
@@ -562,26 +394,24 @@ begin
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
if(AUTO_CONFIG_Z2_DONE(0) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with (0) but it should!
CP_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
end if;
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
if(AUTO_CONFIG_Z2_DONE(2) = '0')then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(2) <= '0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
@@ -599,12 +429,218 @@ begin
end if;
end if;
when others => D_Z2_OUT <= "1111" ;
end case;
end case;
end if;
end if;
end process autoconfig_proc; --- that's all
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset,FCS )
begin
if(reset = '0' or FCS='1') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
CP_WAIT <="0000";
CP_RD_S <= '1';
CP_WE_S <= '1';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
CP_RD_S <= '1';
CP_WE_S <= '1';
-- delay for clockport
if(CP_ACCESS = '1') then
CP_WAIT <= CP_WAIT+1;
else
CP_WAIT <="0000";
end if;
case LAN_SM is
when nop=>
--cycle start!
-- prepare the data for write
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
elsif(CP_ACCESS ='1' and FCS ='0' and Z3_DS < "1111")then
if(RW='1') then
CP_RD_S <= '0';
LAN_SM <= cp_read;
else
CP_WE_S <= '0';
LAN_SM <= cp_write_wait;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
when wait_read_upper=>
LAN_RD_S <= '1';
LAN_SM<=end_read_upper;
when end_read_upper=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(31 downto 16) <= DQ;
else
Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
end if;
when start_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
when wait_read_lower=>
Z3_A_LOW <= '1';
LAN_RD_S <= '1';
LAN_READY <= '1';
LAN_SM<=end_read_lower;
when end_read_lower=>
--fetch data
if(DQ_SWAP='0') then
Z3_DATA(15 downto 0) <= DQ;
else
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
LAN_WRL_S <= not Z3_DS(3);
LAN_SM <= wait_write_upper;
when wait_write_upper=>
LAN_SM<=end_write_upper;
when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
end if;
when start_write_lower=>
Z3_A_LOW <= '1';
-- swapped DS0/DS1 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(0);
LAN_WRL_S <= not Z3_DS(1);
LAN_SM <= wait_write_lower;
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM <= wait_cycle_end;
when cp_read=>
CP_RD_S <= '0';
Z3_DATA(31 downto 0) <= DQ & DQ; -- bus mirroring
if(CP_WAIT(3) = '1') then --wait enough for CP-read
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
else
LAN_SM<=cp_read; -- stay here until cp is ready
end if;
when cp_write_wait=>
CP_WE_S <= '0';
if(CP_WAIT(3) = '1') then --wait enough for CP-write
LAN_READY <='1';
LAN_SM<= wait_cycle_end; --deassert CP_W
else
LAN_SM<=cp_write_wait;
end if;
end case;
end if;
end process lan_rw_gen;
--for the future
CP_WE <= CP_WE_S when FCS='0' else '1';
CP_RD <= CP_RD_S when FCS='0' else '1';
CP_CS <= not CP_ACCESS;
LAN_CS <= LAN_ACCESS when reset='1' and Z3_ADR(15)='0' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
@@ -624,37 +660,35 @@ begin
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and (LAN_ACCESS ='1' or CP_ACCESS = '1') else
(others => 'Z');
A(7 downto 1) <= (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_INIT when reset='0' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D when RW='0' and AS='0' and CP_ACCESS ='1' else
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and (LAN_ACCESS ='1' or CP_ACCESS='1') else
(others => 'Z');
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
INT2_OUT <= '0' when LAN_INT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
SLAVE <= '0' when FCS='0' and (LAN_ACCESS = '1' or CP_ACCESS = '1') else
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
OVR <= '0' when FCS='0' and (LAN_ACCESS = '1' or CP_ACCESS = '1') else 'Z'; --is Cache inhibit on Z3!
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
@@ -696,25 +730,7 @@ begin
ROM_B <= "00";
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP-Z.vhd
-494
View File
@@ -1,494 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:29 12/13/2016
-- Design Name:
-- Module Name: LAN_IDE_CP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- directory cleanup hint:
-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LAN_IDE_CP is
Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
D : inout STD_LOGIC_VECTOR (15 downto 0);
DQ : inout STD_LOGIC_VECTOR (15 downto 0);
A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
OWN : out STD_LOGIC;
SLAVE : out STD_LOGIC;
CFOUT : out STD_LOGIC;
CFIN : in STD_LOGIC;
C1 : in STD_LOGIC;
C3 : in STD_LOGIC;
MTCR : in STD_LOGIC;
OVR : out STD_LOGIC;
BERR : in STD_LOGIC;
MTACK : out STD_LOGIC;
DS0 : in STD_LOGIC;
DTACK : out STD_LOGIC;
UDS : in STD_LOGIC;
LDS : in STD_LOGIC;
AS : in STD_LOGIC;
RW : in STD_LOGIC;
Z3 : in STD_LOGIC;
DS1 : in STD_LOGIC;
FCS : in STD_LOGIC;
RESET : in STD_LOGIC;
INT_OUT : out STD_LOGIC;
AUTOBOOT_OFF : in STD_LOGIC;
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
ROM_OE : out STD_LOGIC;
IDE_WAIT : in STD_LOGIC;
CLK_EXT : in STD_LOGIC;
IDE_W : out STD_LOGIC;
IDE_R : out STD_LOGIC;
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
LAN_RD : out STD_LOGIC;
LAN_CS : out STD_LOGIC;
LAN_WRH : out STD_LOGIC;
LAN_WRL : out STD_LOGIC;
LAN_INT : in STD_LOGIC;
CP_RD : out STD_LOGIC;
CP_WE : out STD_LOGIC;
CP_CS : out STD_LOGIC;
CP_IRQ : in STD_LOGIC);
end LAN_IDE_CP;
architecture Behavioral of LAN_IDE_CP is
TYPE lan_reset IS (
nop,
wait0,
clr,
clr_commit,
wait1,
set,
set_commit,
done
);
SIGNAL LAN_RST_SM: lan_reset :=nop;
SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
SIGNAL ide: STD_LOGIC;
SIGNAL autoconfig: STD_LOGIC;
SIGNAL lan_adr: STD_LOGIC;
SIGNAL lan_adr_sw: STD_LOGIC;
SIGNAL cp: STD_LOGIC;
signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(1 downto 0);
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal IDE_ENABLE:STD_LOGIC;
signal ROM_OE_S:STD_LOGIC;
signal IDE_R_S:STD_LOGIC;
signal IDE_W_S:STD_LOGIC;
signal DTACK_S:STD_LOGIC;
signal AMIGA_CLK: std_logic;
signal LAN_INT_ENABLE: std_logic;
signal DECODE_RESET: std_logic;
signal LAN_INT_D0: std_logic;
signal DS: std_logic;
signal DS_D: std_logic;
signal LAN_RD_S: std_logic;
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic;
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000";
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000";
Function to_std_logic(X: in Boolean) return Std_Logic is
variable ret : std_logic;
begin
if x then ret := '1'; else ret := '0'; end if;
return ret;
end to_std_logic;
begin
AMIGA_CLK <= not (C1 xor C3);
DECODE_RESET <= BERR and reset;
DS <= UDS and LDS;
clock_init: process(CLK_EXT)
begin
if(rising_edge(CLK_EXT))then
if(reset = '0')then
--init the clock!
case LAN_RST_SM is
when nop=>
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=wait0;
when wait0=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=clr;
when clr=>
LAN_CS_RST<='1';
LAN_WR_RST<='1';
LAN_RST_SM<=clr_commit;
when clr_commit=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=wait1;
when wait1=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=set;
when set=>
LAN_CS_RST<='1';
LAN_WR_RST<='1';
LAN_RST_SM<=set_commit;
when set_commit=>
LAN_CS_RST<='1';
LAN_WR_RST<='0';
LAN_RST_SM<=done;
when done=>
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=done;
end case;
else
LAN_CS_RST<='0';
LAN_WR_RST<='0';
LAN_RST_SM<=nop;
end if;
end if;
end process clock_init;
ADDRESS_DECODE: process(DECODE_RESET,AS)
begin
if(DECODE_RESET ='0')then
autoconfig <= '0';
ide <= '0';
lan_adr <= '0';
lan_adr_sw <= '0';
cp <= '0';
lancp <= '0';
elsif(falling_edge(AS))then
--default values
autoconfig <= '0';
ide <= '0';
lan_adr <= '0';
lan_adr_sw <= '0';
cp <= '0';
lancp <= '0';
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
autoconfig <= '1';
elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
if(A(14 downto 13)<"11")then
lan_adr_sw <= '1';
end if;
lan_adr <= '1';
lancp <= '1';
elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
cp <= '1';
lancp <= '1';
elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
ide <= '1';
end if;
end if;
end process ADDRESS_DECODE;
--LAN interrupt enable
lan_int_proc: process (AMIGA_CLK,reset)
begin
if(reset ='0') then
LAN_INT_ENABLE <='0';
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif falling_edge(AMIGA_CLK) then
LAN_IRQ_D0 <= LAN_INT;
if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
LAN_IRQ_OUT <='0';
elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then
LAN_IRQ_OUT <='1';
elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
LAN_IRQ_OUT <= D(14); --controll lan irq
end if;
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
LAN_INT_ENABLE <= D(15);
end if;
end if;
end process lan_int_proc;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
LAN_WRL_S <= '0';
if(lan_adr='1' and DS='0' and A(15)='0')then
LAN_RD_S <= RW;
-- swapped LDS/UDS here: ENC624 is little endian
LAN_WRH_S <= not LDS and not RW;
LAN_WRL_S <= not UDS and not RW;
end if;
end if;
end process lan_rw_gen;
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
begin
if falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(cp = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
CP_WE_QUIRK <= CP_WE_S;
end if;
end process cp_rw_gen;
--ide signal generation
ide_rw_gen: process (reset,AMIGA_CLK)
begin
if (reset = '0') then
IDE_ENABLE <= '1';
IDE_R_S <= '1';
IDE_W_S <= '1';
ROM_OE_S <= '1';
elsif falling_edge(AMIGA_CLK) then
--default values
IDE_R_S <= '1';
IDE_W_S <= '1';
ROM_OE_S <= '1';
if(ide='1' and AS='0')then
if(RW='0')then
--the write goes to the hdd!
IDE_ENABLE <= '0'; -- enable IDE on first read
IDE_W_S <= '0';
else
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
ROM_OE_S <= not IDE_ENABLE;
end if;
end if;
end if;
end process ide_rw_gen;
--autoconfig
autoconfig_proc: process (reset, AMIGA_CLK)
begin
if reset = '0' then
-- reset active ...
AUTO_CONFIG_DONE_CYCLE <="00";
Dout1<="1111";
--Dout2<="1111";
SHUT_UP <="111";
IDE_BASEADR<=x"FF";
LAN_BASEADR<=x"FF";
CP_BASEADR<=x"FF";
AUTO_CONFIG_DONE <="00";
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
DS_D <= DS;
if(AS='1')then
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
elsif(autoconfig= '1' and DS='0') then
case A(6 downto 1) is
when "000000" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
else
Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
end if;
when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
when "000010" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1000" ; --ProductID high nibble : 7->1000
else
Dout1 <= "1111" ; --ProductID high nibble : 0->1111
end if;
when "000011" =>
if(AUTO_CONFIG_DONE = 0)then
Dout1 <= "0100" ; --ProductID low nibble: B->0100
elsif(AUTO_CONFIG_DONE = 1)then
Dout1 <= "0011" ; --ProductID low nibble: C->0011
else
Dout1 <= "1001" ; --ProductID low nibble: 6->1001
end if;
when "001000" => Dout1 <= "1111" ; --Ventor ID 0
when "001001" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "0101" ; --Ventor ID 1
else
Dout1 <= "0111" ; --Ventor ID 1
end if;
when "001010" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "1110" ; --Ventor ID 2
else
Dout1 <= "1101" ; --Ventor ID 2
end if;
when "001011" =>
if(AUTO_CONFIG_DONE < 2)then
Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
else
Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC
end if;
when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble
when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble
when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble
when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble
when "010000" => Dout1 <= "1111" ; --Serial byte 2 high nibble
when "010001" => Dout1 <= "1111" ; --Serial byte 2 low nibble
when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble
when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
if(AUTO_CONFIG_DONE = 2)then
Dout1 <= "1110" ; --Rom vector low byte low nibble
else
Dout1 <= "1111" ; --Rom vector low byte low nibble
end if;
when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero
when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero
when "100100" =>
Dout1 <= "1111" ;
if(RW='0' and DS_D='1')then
if(AUTO_CONFIG_DONE = 0)then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(0) <='0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= "01"; --done here
elsif(AUTO_CONFIG_DONE = 1)then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(1) <= '0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part!
elsif(AUTO_CONFIG_DONE = 2)then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(2) <= '0'; --enable board
AUTO_CONFIG_DONE_CYCLE <= "11"; --done here
end if;
end if;
when "100110" =>
Dout1 <= "1111" ;
if(RW='0' and DS_D='1')then
AUTO_CONFIG_DONE_CYCLE <= AUTO_CONFIG_DONE_CYCLE+1; --done here
end if;
when others => Dout1 <= "1111" ;
end case;
end if;
end if;
end process autoconfig_proc; --- that's all
LAN_CS <= lan_adr when reset='1' else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
LAN_CFG <= "ZZZZ";
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not cp;
--the lanport is shifted by one adress line but I forgot to adopt the clockport address!
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip
A(14 downto 7);
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(2 downto 1);
--signal assignment
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
(others => 'Z');
--defined lancp signal that matches both LAN and CP addresses
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
D when RW='0' and AS='0' and lancp ='1'
else (others => 'Z');
IDE_W <= IDE_W_S when AS='0' else '1';
IDE_R <= IDE_R_S when AS='0' else '1';
IDE_CS(0)<= not(A(12));
IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9);
ROM_B <= "00";
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
-- INT_OUT <= 'Z';
INT_OUT <= '0' when
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
or CP_IRQ = '0'
else 'Z';
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
-- OVR <= 'Z';
OVR <= '0' when ide='1' and AS='0' else 'Z';
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or
-- AUTOCONFIG_IN_PROGRES ='1'
-- else 'Z';
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
-- DTACK <= 'Z';
A <= (others => 'Z');
MTACK <= 'Z';
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.bld
+1 -1
View File
@@ -29,7 +29,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 4418692 kilobytes
Total memory usage is 4418684 kilobytes
Writing NGD file "LAN_IDE_CP.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Logic/LAN_IDE/LAN_IDE_CP.cmd_log
+217
View File
@@ -419,3 +419,220 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE/LAN_IDE_CP.gyd
+71 -69
View File
@@ -20,6 +20,7 @@ DS1 S:PIN78
FCS S:PIN77
LAN_INT S:PIN111
LDS S:PIN82
MTCR S:PIN101
RESET S:PIN143
RW S:PIN83
UDS S:PIN81
@@ -120,82 +121,83 @@ DQ<4> S:PIN124
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 EXP24_ EXP25_ AUTO_CONFIG_Z2_DONE_CYCLE<2> SHUT_UP_Z2<1>
D_5_IOBUFE D_4_IOBUFE EXP26_ IDE_CS_0_OBUF
AUTO_CONFIG_Z2_DONE_CYCLE<1> IDE_CS_1_OBUF LAN_BASEADR<9> IDE_A_0_OBUF$BUF0
LAN_BASEADR<8> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 D_Z2_OUT<0>
PARTITION FB1_1 EXP24_ SHUT_UP_Z2<2> EXP25_ CP_BASEADR<7>
D_5_IOBUFE D_4_IOBUFE CP_BASEADR<6> IDE_CS_0_OBUF
CP_BASEADR<5> IDE_CS_1_OBUF CP_BASEADR<4> IDE_A_0_OBUF$BUF0
CP_BASEADR<1> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 CP_BASEADR<0>
IDE_R_OBUF D_Z2_OUT<2>
PARTITION FB2_1 LAN_SM_FSM_FFd2 A_LAN_4_OBUF A_LAN_7_OBUF
PARTITION FB2_5 A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 DQ_5_IOBUFE/DQ_5_IOBUFE_TRST ROM_B_0_OBUF$BUF5
LAN_RD_S D_6_IOBUFE EXP27_ D_3_IOBUFE
EXP28_ D_7_IOBUFE D_1_IOBUFE LAN_SM_FSM_FFd3
PARTITION FB2_1 DQ<8>_BUFR.MC A_LAN_4_OBUF A_LAN_7_OBUF DQ_8_IOBUFE/DQ_8_IOBUFE_TRST
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<0> ROM_B_0_OBUF$BUF5
IDE_BASEADR<1> D_6_IOBUFE EXP26_ D_3_IOBUFE
EXP27_ D_7_IOBUFE D_1_IOBUFE EXP28_
D_8_IOBUFE EXP29_
PARTITION FB3_1 $OpTx$BIN_STEP$140 IDE_W_OBUF EXP30_
PARTITION FB3_14 ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF CP_WE_QUIRK
EXP31_
PARTITION FB4_1 IDE_BASEADR<6> D_0_IOBUFE EXP32_ IDE_BASEADR<4>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<3> A_LAN_3_OBUF
IDE_BASEADR<2> IDE_BASEADR<1> IDE_BASEADR<0> A_LAN_2_OBUF
CP_BASEADR<0> A_LAN_5_OBUF EXP33_ D_Z2_OUT<1>
EXP34_ IDE_BASEADR<5>
PARTITION FB5_1 D_8_IOBUFE/D_8_IOBUFE_TRST CP_CS_OBUF SHUT_UP_Z2<2> LAN_BASEADR<10>
ROM_OE_OBUF CP_BASEADR<7> CP_BASEADR<3> CP_BASEADR<2>
EXP35_ D_2_IOBUFE CP_BASEADR<1> D_9_IOBUFE
EXP36_ D_10_IOBUFE D_11_IOBUFE EXP37_
D_12_IOBUFE IDE_BASEADR<7>
PARTITION FB6_1 LAN_D_INIT<8> ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF LAN_IRQ_D0
A_LAN_13_OBUF A_LAN_10_OBUF FCS_SM_P_D0 A_LAN_11_OBUF
LAN_WR_RST A_LAN_8_OBUF LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd2
LAN_RST_SM_FSM_FFd1 A_LAN_9_OBUF LAN_ACCESS EXP38_
LAN_A_INIT<3> LAN_IRQ_OUT
PARTITION FB7_1 Z3_ADR<4> ROM_OE_S D_13_IOBUFE IDE_W_S
D_14_IOBUFE EXP39_ IDE_ENABLE CP_WE_S
CP_RD_S AUTO_CONFIG_Z2_DONE_CYCLE<0> AUTO_CONFIG_Z2_DONE<2> D_15_IOBUFE
IDE_R_S AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0> AUTOCONFIG_Z2_ACCESS
EXP40_ D_Z2_OUT<3>
PARTITION FB8_1 Z3_ADR<2> DQ_12_IOBUFE DQ_14_IOBUFE EXP41_
LAN_WRH_OBUF EXP42_ SHUT_UP_Z2<0> LAN_CS_OBUF
LAN_BASEADR<7> LAN_RD_OBUF LAN_BASEADR<5> LAN_BASEADR<4>
LAN_BASEADR<3> Z3_ADR<3> LAN_BASEADR<2> LAN_BASEADR<1>
LAN_BASEADR<0> LAN_BASEADR<6>
PARTITION FB9_1 Z3_DATA<24> EXP43_ DQ_DATA<6> Z3_DATA<16>
EXP44_ EXP45_ DQ_DATA<5> DQ_DATA<15>
EXP46_ EXP47_ Z3_DATA<0> DQ_DATA<14>
EXP48_ Z3_DATA<1> EXP49_ DQ_DATA<13>
Z3_DATA<2> EXP50_
PARTITION FB3_2 IDE_W_OBUF
PARTITION FB3_10 LAN_A_INIT<3> SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF CP_WE_QUIRK Z3_ADR<9>
ROM_B_0_OBUF$BUF9 ROM_B_0_OBUF$BUF0 Z3_ADR<8> Z3_ADR<7>
LAN_IRQ_OUT
PARTITION FB4_1 IDE_BASEADR<7> D_0_IOBUFE EXP30_ IDE_BASEADR<5>
A_LAN_1_OBUF A_LAN_0_OBUF IDE_BASEADR<4> A_LAN_3_OBUF
IDE_BASEADR<3> IDE_BASEADR<2> CP_BASEADR<3> A_LAN_2_OBUF
CP_BASEADR<2> A_LAN_5_OBUF EXP31_ D_Z2_OUT<1>
EXP32_ IDE_BASEADR<6>
PARTITION FB5_1 EXP33_ CP_CS_OBUF EXP34_ D_8_IOBUFE/D_8_IOBUFE_TRST
ROM_OE_OBUF AUTOCONFIG_Z2_ACCESS
PARTITION FB5_9 EXP35_ D_2_IOBUFE EXP36_ D_9_IOBUFE
EXP37_ D_10_IOBUFE D_11_IOBUFE EXP38_
D_12_IOBUFE IDE_ACCESS/IDE_ACCESS_RSTF__$INT
PARTITION FB6_1 EXP39_ ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF Z3_ADR<6> A_LAN_11_OBUF
Z3_ADR<5> A_LAN_8_OBUF Z3_ADR<13> Z3_ADR<12>
Z3_ADR<11> A_LAN_9_OBUF Z3_ADR<10> INT_VECTOR_CYCLE
EXP40_ IDE_ACCESS
PARTITION FB7_1 Z3_ADR<4> EXP41_ D_13_IOBUFE Z3_ADR<3>
D_14_IOBUFE Z3_ADR_0 EXP42_ LAN_BASEADR<9>
LAN_BASEADR<8> LAN_BASEADR<15> LAN_BASEADR<14> D_15_IOBUFE
EXP43_ Z3_ADR<2> LAN_BASEADR<13> LAN_BASEADR<12>
LAN_BASEADR<11> LAN_BASEADR<10>
PARTITION FB8_1 DQ_DATA<12> DQ_12_IOBUFE DQ_14_IOBUFE EXP44_
LAN_WRH_OBUF EXP45_ LAN_SM_FSM_FFd4 LAN_CS_OBUF
DQ_DATA<6> LAN_RD_OBUF LAN_WRH_S DQ_DATA<14>
EXP46_ DQ_DATA<4> EXP47_ EXP48_
EXP49_ EXP50_
PARTITION FB9_1 LAN_WR_RST LAN_RST_SM_FSM_FFd1 LAN_IRQ_D0 LAN_D_INIT<8>
LAN_D_INIT<1> LAN_CS_RST LAN_A_INIT<6> LAN_RST_SM_FSM_FFd3
LAN_RST_SM_FSM_FFd2 SHUT_UP_Z2<1> Z3_DATA<0> SHUT_UP_Z2<0>
AUTO_CONFIG_Z2_DONE_CYCLE<2> Z3_DATA<1> AUTO_CONFIG_Z2_DONE_CYCLE<1> AUTO_CONFIG_Z2_DONE_CYCLE<0>
Z3_DATA<2> AUTO_CONFIG_Z2_DONE<2>
PARTITION FB10_1 DQ<4>_BUFR.MC DQ_1_IOBUFE DQ_0_IOBUFE EXP51_
DQ_3_IOBUFE DQ_2_IOBUFE EXP52_ DQ_5_IOBUFE
EXP53_ _19_ DQ_7_IOBUFE DQ_6_IOBUFE
EXP54_ _18_ EXP55_ EXP56_
DQ_10_IOBUFE EXP57_
PARTITION FB11_1 LAN_SM_FSM_FFd1 EXP58_ Z3_DATA<3>
PARTITION FB11_5 Z3_DATA<4> EXP59_ LAN_SM_FSM_FFd4 Z3_A_LOW
EXP60_ Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
DQ<8>_BUFR.MC ROM_B_0_OBUF DQ_DATA<8> EXP61_
PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<28>
Z3_DATA<4> Z3_DATA<27> Z3_DATA<22> Z3_DATA<21>
Z3_DATA<20> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF8
Z3_DATA<19> ROM_B_0_OBUF EXP58_ DQ_DATA<8>
CP_WE_OBUF DQ_DATA<0>
PARTITION FB12_1 CP_BASEADR<4> ROM_B_0_OBUF$BUF4 LAN_BASEADR<14> LAN_BASEADR<13>
DQ_15_IOBUFE LAN_BASEADR<12> LAN_BASEADR<11> DQ_13_IOBUFE
PARTITION FB12_1 EXP59_ ROM_B_0_OBUF$BUF4 LAN_SM_RST EXP60_
DQ_15_IOBUFE LAN_SM_FSM_FFd1 EXP61_ DQ_13_IOBUFE
EXP62_ DQ_11_IOBUFE EXP63_ DQ_9_IOBUFE
EXP64_ EXP65_ EXP66_ LAN_BASEADR<15>
CP_BASEADR<6> CP_BASEADR<5>
PARTITION FB13_1 Z3_ADR<7> CP_RD_OBUF DQ_DATA<1> Z3_ADR<12>
Z3_ADR<11> LAN_WRL_S LAN_D_INIT<1> Z3_DATA<7>
LAN_CS_RST DQ_SWAP LAN_A_INIT<6> LAN_INT_ENABLE
LAN_READY LAN_WRL_OBUF DQ_DATA<9> Z3_ADR<13>
EXP67_ DQ_DATA<7>
PARTITION FB14_1 CP_ACCESS EXP68_ ROM_B_0_OBUF$BUF2
PARTITION FB14_5 FCS_P_D0 Z3_ADR_1 Z3_ADR_0 Z3_ADR<9>
Z3_ADR<8> Z3_ADR<6> CFOUT_OBUF EXP69_
IDE_ACCESS SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR<5>
Z3_ADR<10> EXP70_
PARTITION FB15_1 DQ_DATA<10> Z3_DATA<31> Z3_DATA<30> EXP71_
DQ_DATA<4> Z3_DATA<29> Z3_DATA<23> EXP72_
EXP73_ DQ_DATA<2> DQ_DATA<12> ROM_B_0_OBUF$BUF10
Z3_DATA<22> Z3_DATA<15> Z3_DATA<14> Z3_DATA<21>
Z3_DATA<13> EXP74_
PARTITION FB16_1 LAN_WRH_S Z3_DATA<12> Z3_DATA<11> Z3_DATA<28>
Z3_DATA<27> Z3_DATA<10> Z3_DATA<26> Z3_DATA<9>
Z3_DATA<25> ROM_B_0_OBUF$BUF3 Z3_DATA<8> EXP75_
DQ_DATA<11> Z3_DATA<20> Z3_DATA<19> Z3_DATA<18>
Z3_DATA<17> DQ_DATA<3>
EXP64_ EXP65_ EXP66_ LAN_ACCESS
EXP67_ DQ_SWAP
PARTITION FB13_1 EXP68_ CP_RD_OBUF Z3_DATA<31> Z3_DATA<23>
LAN_INT_ENABLE EXP69_ DQ_DATA<5> Z3_DATA<7>
EXP70_ EXP71_ DQ_DATA<3> DQ_DATA<15>
EXP72_ LAN_WRL_OBUF EXP73_ DQ_DATA<11>
LAN_WRL_S DQ_DATA<13>
PARTITION FB14_1 EXP74_ D_Z2_OUT<3> ROM_B_0_OBUF$BUF2 Z3_ADR_1
ROM_OE_S IDE_W_S IDE_R_S IDE_ENABLE
CP_WE_S CP_RD_S CFOUT_OBUF AUTO_CONFIG_Z2_DONE<1>
AUTO_CONFIG_Z2_DONE<0> SLAVE_OBUF ROM_B_0_OBUF$BUF1 EXP75_
D_Z2_OUT<0> EXP76_
PARTITION FB15_1 EXP77_ EXP78_ EXP79_ LAN_SM_FSM_FFd3
LAN_SM_FSM_FFd2 EXP80_ Z3_A_LOW DQ_DATA<7>
EXP81_ DQ_DATA<9> EXP82_ ROM_B_0_OBUF$BUF10
LAN_RD_S Z3_DATA<15> Z3_DATA<14> LAN_READY
Z3_DATA<13> DQ_DATA<1>
PARTITION FB16_1 EXP83_ Z3_DATA<12> Z3_DATA<11>
PARTITION FB16_5 Z3_DATA<26> Z3_DATA<10> Z3_DATA<25> Z3_DATA<9>
Z3_DATA<24> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<18>
Z3_DATA<17> Z3_DATA<16> EXP84_ DQ_DATA<10>
DQ_DATA<2> EXP85_
Logic/LAN_IDE/LAN_IDE_CP.jed
+1490 -1490
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Logic/LAN_IDE/LAN_IDE_CP.mfd
+4155 -4356
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Logic/LAN_IDE/LAN_IDE_CP.nga
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngc
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngd
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngr
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.pad
+2 -2
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-28-2019 10:58PM
3- 7-2019 11:51PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
@@ -118,7 +118,7 @@ P97|A<16>|I/O|I/O|BIDIR|||||||||
P98|TIE||I/O||||||||||
P99|GND||GND||||||||||
P100|OVR|O|I/O|OUTPUT|||||||||
P101|TIE||I/O||||||||||
P101|MTCR|I|I/O|INPUT|||||||||
P102|C3|I|I/O|INPUT|||||||||
P103|C1|I|I/O|INPUT|||||||||
P104|CFIN|I|I/O|INPUT|||||||||
Logic/LAN_IDE/LAN_IDE_CP.pnx
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.rpt
+2089 -2290
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Logic/LAN_IDE/LAN_IDE_CP.syr
+93 -90
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@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Compact
FSM Encoding Algorithm : Gray
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
@@ -56,7 +56,7 @@ Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -71,7 +71,7 @@ wysiwyg : NO
=========================================================================
Setting FSM Encoding Algorithm to : OPT
Setting FSM Encoding Algorithm to : Gray
=========================================================================
@@ -110,22 +110,22 @@ INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP>
Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_CYCLE_IN_PROGRESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:647 - Input <BERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <LAN_BASEADR<7:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CONFIG_READY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found finite state machine <FSM_0> for signal <LAN_SM>.
-----------------------------------------------------------------------
| States | 13 |
| Transitions | 26 |
| Inputs | 9 |
| Transitions | 19 |
| Inputs | 4 |
| Outputs | 14 |
| Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) |
| Reset | LAN_SM_RST (positive) |
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
@@ -139,7 +139,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | compact |
| Encoding | gray |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>.
@@ -167,32 +167,31 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit tristate buffer for signal <A<10>>.
Found 1-bit tristate buffer for signal <A<9>>.
Found 1-bit tristate buffer for signal <A<8>>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 183.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 179.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
Found 1-bit register for signal <CP_ACCESS>.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 295.
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 292.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
Found 1-bit register for signal <CP_WE_S>.
Found 4-bit register for signal <D_Z2_OUT>.
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 637.
Found 16-bit register for signal <DQ_DATA>.
Found 1-bit register for signal <DQ_SWAP>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
Found 1-bit register for signal <FCS_N_D0>.
Found 1-bit register for signal <FCS_P_D0>.
Found 1-bit register for signal <FCS_SM_P_D0>.
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 264.
Found 1-bit register for signal <IDE_ACCESS>.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 302.
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 299.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <INT_VECTOR_CYCLE>.
Found 14-bit register for signal <LAN_A_INIT>.
Found 1-bit register for signal <LAN_ACCESS>.
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 271.
Found 8-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 263.
Found 16-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 16-bit register for signal <LAN_D_INIT>.
@@ -201,8 +200,8 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 1-bit register for signal <LAN_IRQ_OUT>.
Found 1-bit register for signal <LAN_RD_S>.
Found 1-bit register for signal <LAN_READY>.
Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 419.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 423.
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 389.
Found 1-bit register for signal <LAN_SM_RST>.
Found 1-bit register for signal <LAN_WR_RST>.
Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>.
@@ -213,7 +212,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
Found 32-bit register for signal <Z3_DATA>.
Summary:
inferred 2 Finite State Machine(s).
inferred 77 D-type flip-flop(s).
inferred 59 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
inferred 58 Tristate(s).
@@ -224,18 +223,17 @@ Unit <LAN_IDE_CP> synthesized.
HDL Synthesis Report
Macro Statistics
# Registers : 86
1-bit register : 78
# Registers : 71
1-bit register : 62
14-bit register : 2
16-bit register : 2
16-bit register : 3
3-bit register : 1
4-bit register : 1
8-bit register : 2
# Comparators : 6
16-bit comparator equal : 1
2-bit comparator less : 2
4-bit comparator less : 1
8-bit comparator equal : 2
8-bit comparator equal : 3
# Tristates : 28
1-bit tristate buffer : 26
16-bit tristate buffer : 2
@@ -248,37 +246,37 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with compact encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
------------------------
State | Encoding
------------------------
nop | 000
wait0 | 100
clr | 101
clr_commit | 111
wait1 | 001
set | 011
set_commit | 010
done | 110
wait0 | 001
clr | 011
clr_commit | 010
wait1 | 110
set | 111
set_commit | 101
done | 100
------------------------
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with compact encoding.
Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:4]> with gray encoding.
-------------------------------
State | Encoding
-------------------------------
nop | 0000
start_read_upper | unreached
wait_read_upper | 1111
end_read_upper | 1100
start_read_lower | 0110
wait_read_lower | 0111
end_read_lower | 0001
start_write_upper | 1011
wait_write_upper | 1110
end_write_upper | 0100
start_write_lower | 0011
wait_write_lower | 1101
wait_cycle_end | 0010
config_rw | 0101
wait_read_upper | 0011
end_read_upper | 0101
start_read_lower | 0100
wait_read_lower | 0010
end_read_lower | 1100
start_write_upper | 0110
wait_write_upper | 1101
end_write_upper | 1111
start_write_lower | 0111
wait_write_lower | 1110
end_write_lower | 1010
config_rw | 0001
-------------------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
@@ -308,11 +306,10 @@ Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 76
Flip-Flops : 76
# Registers : 59
Flip-Flops : 59
# Comparators : 3
16-bit comparator equal : 1
8-bit comparator equal : 2
8-bit comparator equal : 3
=========================================================================
@@ -341,35 +338,43 @@ WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <LAN_BASEADR_7> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_6> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_5> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_4> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_3> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_2> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_1> of sequential type is unconnected in block <LAN_IDE_CP>.
WARNING:Xst:2677 - Node <LAN_BASEADR_0> of sequential type is unconnected in block <LAN_IDE_CP>.
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11>
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=s : D_Z2_OUT_2
implementation constraint: INIT=s : D_Z2_OUT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
implementation constraint: INIT=r : LAN_INT_ENABLE
implementation constraint: INIT=s : SHUT_UP_Z2_1
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
implementation constraint: INIT=s : D_Z2_OUT_0
implementation constraint: INIT=s : D_Z2_OUT_3
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
implementation constraint: INIT=s : LAN_A_INIT_3
implementation constraint: INIT=s : LAN_A_INIT_6
implementation constraint: INIT=r : LAN_D_INIT_1
implementation constraint: INIT=r : LAN_D_INIT_8
implementation constraint: INIT=s : SHUT_UP_Z2_2
implementation constraint: INIT=s : SHUT_UP_Z2_0
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
=========================================================================
* Partition Report *
@@ -401,42 +406,40 @@ Design Statistics
# IOs : 117
Cell Usage :
# BELS : 1292
# AND2 : 404
# AND3 : 63
# AND4 : 17
# BELS : 1402
# AND2 : 452
# AND3 : 66
# AND4 : 23
# AND5 : 1
# AND6 : 2
# AND7 : 1
# AND8 : 4
# AND8 : 3
# GND : 1
# INV : 480
# OR2 : 250
# OR3 : 34
# OR4 : 1
# XOR2 : 34
# FlipFlops/Latches : 142
# FD : 3
# FDC : 22
# INV : 532
# OR2 : 243
# OR3 : 53
# OR4 : 3
# XOR2 : 25
# FlipFlops/Latches : 134
# FD : 4
# FDC : 21
# FDCE : 7
# FDP : 41
# FDPE : 69
# IO Buffers : 114
# IBUF : 23
# FDPE : 61
# IO Buffers : 115
# IBUF : 24
# IOBUFE : 48
# OBUF : 33
# OBUFE : 10
=========================================================================
Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.75 secs
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.07 secs
-->
Total memory usage is 4534768 kilobytes
Total memory usage is 4534748 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 48 ( 0 filtered)
Number of warnings : 56 ( 0 filtered)
Number of infos : 10 ( 0 filtered)
Logic/LAN_IDE/LAN_IDE_CP.tspec
+510 -502
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.vhd
+52 -95
View File
@@ -107,7 +107,7 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
wait_cycle_end,
end_write_lower,
config_rw
);
@@ -135,6 +135,7 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_WRH_S: std_logic;
signal LAN_WRL_S: std_logic;
signal LAN_READY: std_logic;
signal CONFIG_READY: std_logic;
signal LAN_IRQ_D0: std_logic;
signal LAN_IRQ_OUT: std_logic;
signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
@@ -144,12 +145,6 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
@@ -160,6 +155,7 @@ architecture Behavioral of LAN_IDE_CP is
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
signal INT_VECTOR_CYCLE: std_logic;
signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
@@ -249,37 +245,38 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(--AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
INT_VECTOR_CYCLE <='0';
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
INT_VECTOR_CYCLE <= not MTCR; --is this s special int vector cycle?!?
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
--if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(Z3='1' and (D(15 downto 8) ) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(--FCS ='0' or
reset='0')then
if(reset='0' or FCS='1')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
@@ -292,14 +289,14 @@ begin
end if;
--CP base
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' )then
if(A(23 downto 16) = CP_BASEADR and SHUT_UP_Z2(1)='0' and LAN_ACCESS = '0')then
CP_ACCESS <= '1';
else
CP_ACCESS <= '0';
end if;
--IDE base
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' )then
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP_Z2(2)='0' and LAN_ACCESS = '0' )then
IDE_ACCESS <= '1';
else
IDE_ACCESS <= '0';
@@ -337,7 +334,7 @@ begin
lan_rst_gen: process (CLK_EXT)
begin
if falling_edge(CLK_EXT) then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or BERR = '0') then
if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or INT_VECTOR_CYCLE ='1') then
LAN_SM_RST <='1';
else
LAN_SM_RST <='0';
@@ -345,30 +342,10 @@ begin
end if;
end process lan_rst_gen;
fcs_pos_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_P_D0 <='0';
elsif(rising_edge(FCS)) then
FCS_P_D0 <= not FCS_P_D0; --toggle
end if;
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset )
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin
if(reset = '0' ) then
if(LAN_SM_RST ='1' ) then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
@@ -377,9 +354,6 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
FCS_SM_P_D0 <='0';
FCS_SM_N_D0 <='0';
LAN_CYCLE_IN_PROGRESS <='0';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -387,13 +361,6 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
FCS_SM_N_D0 <= FCS_N_D0; --store edge state
FCS_SM_P_D0 <= FCS_P_D0; --store edge state
if(LAN_ACCESS = '1' and FCS_SM_N_D0 /= FCS_N_D0) then
LAN_CYCLE_IN_PROGRESS <='1';
elsif(FCS_SM_P_D0 /= FCS_P_D0) then
LAN_CYCLE_IN_PROGRESS <='0';
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -416,27 +383,23 @@ begin
end if;
end if;
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
LAN_SM <= start_write_lower;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
@@ -453,7 +416,7 @@ begin
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM <= end_read_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
@@ -475,7 +438,7 @@ begin
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM<=end_read_lower; -- stay here until cylce end
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
@@ -493,7 +456,7 @@ begin
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= wait_cycle_end;
LAN_SM <= end_write_upper; -- stay here until cylce end
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
@@ -507,14 +470,10 @@ begin
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_READY <='1';
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
LAN_SM<=end_write_lower; -- stay here until cylce end
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
@@ -522,7 +481,7 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM <= wait_cycle_end;
LAN_SM<=config_rw; -- stay here until cylce end
end case;
end if;
end process lan_rw_gen;
@@ -604,22 +563,20 @@ begin
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
when "010111" =>
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
D_Z2_OUT <= "1110" ; --Rom vector low byte low nibble
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with index 0 but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
end if;
end if;
when "100100" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
if(RW='0' and AUTO_CONFIG_Z2_DONE(0)='1')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(1) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
@@ -696,7 +653,7 @@ begin
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
OVR <= 'Z'; --'0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
DTACK <= '0' when FCS='0' and LAN_READY = '1' else 'Z';
@@ -745,7 +702,7 @@ begin
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
if(CP_ACCESS = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
@@ -756,7 +713,7 @@ begin
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS when AS='0' else '1';
CP_CS <= not CP_ACCESS;
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.vhd.bak
+101 -47
View File
@@ -107,7 +107,7 @@ architecture Behavioral of LAN_IDE_CP is
end_write_upper,
start_write_lower,
wait_write_lower,
end_write_lower,
wait_cycle_end,
config_rw
);
@@ -144,6 +144,14 @@ architecture Behavioral of LAN_IDE_CP is
signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
signal Z3_A_LOW:STD_LOGIC;
signal LAN_SM_RST:STD_LOGIC;
signal FCS_P_D0:STD_LOGIC;
signal FCS_N_D0:STD_LOGIC;
signal FCS_SM_P_D0:STD_LOGIC;
signal FCS_SM_N_D0:STD_LOGIC;
signal LAN_CYCLE_IN_PROGRESS:STD_LOGIC;
signal INT6_SIG:STD_LOGIC;
signal INT2_SIG:STD_LOGIC;
signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic;
@@ -172,6 +180,7 @@ architecture Behavioral of LAN_IDE_CP is
begin
Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
Z3_DS <= UDS & LDS & DS1 & DS0;
AMIGA_CLK <= not (C1 xor C3);
DS <= UDS and LDS;
@@ -242,8 +251,7 @@ begin
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
begin
if(AS ='0' or
reset='0')then
if(reset='0')then
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
Z3_ADR <= (others => '1');
@@ -251,29 +259,27 @@ begin
elsif(falling_edge(FCS))then
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
--lan base
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if(A(14 downto 13)<"11")then
DQ_SWAP <= '1';
else
DQ_SWAP <= '0';
end if;
if((D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
LAN_ACCESS <= '1';
else
LAN_ACCESS <= '0';
DQ_SWAP <= '1';
end if;
end if;
end process ADDRESS_Z3_DECODE;
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
begin
if(FCS ='0' or
reset='0')then
if(reset='0')then
AUTOCONFIG_Z2_ACCESS <= '0';
IDE_ACCESS <= '0';
CP_ACCESS <= '0';
@@ -302,13 +308,16 @@ begin
end if;
end process ADDRESS_Z2_DECODE;
--LAN interrupt controll
lan_int_proc: process (CLK_EXT,reset)
--interrupt sampling to avoid ghost interrupts
int_proc: process (CLK_EXT,reset)
begin
if(reset ='0') then
LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1';
elsif rising_edge(CLK_EXT) then
LAN_IRQ_D0 <= LAN_INT;
--set/deassert the LAN-interrupt bit
@@ -325,7 +334,7 @@ begin
LAN_IRQ_OUT <='0';
end if;
end if;
end process lan_int_proc;
end process int_proc;
--clock this signal to avoid glitches due to short resets
lan_rst_gen: process (CLK_EXT)
@@ -339,10 +348,30 @@ begin
end if;
end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
fcs_pos_edge_detect: process(reset, FCS)
begin
if(LAN_SM_RST ='1' ) then
if(reset ='0') then
FCS_P_D0 <='0';
elsif(rising_edge(FCS)) then
FCS_P_D0 <= not FCS_P_D0; --toggle
end if;
end process;
fcs_neg_edge_detect: process(reset, FCS)
begin
if(reset ='0') then
FCS_N_D0 <='0';
elsif(falling_edge(FCS)) then
FCS_N_D0 <= not FCS_N_D0; --toggle
end if;
end process;
--lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,reset,FCS )
begin
if(reset = '0' or FCS='1') then
LAN_SM <=nop;
LAN_RD_S <= '0';
LAN_WRH_S <= '0';
@@ -351,6 +380,9 @@ begin
LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
FCS_SM_P_D0 <='0';
FCS_SM_N_D0 <='0';
LAN_CYCLE_IN_PROGRESS <='0';
elsif rising_edge(CLK_EXT) then
--default values
LAN_RD_S <= '0';
@@ -358,6 +390,13 @@ begin
LAN_WRL_S <= '0';
Z3_A_LOW <= '0';
LAN_READY <= '0';
FCS_SM_N_D0 <= FCS_N_D0; --store edge state
FCS_SM_P_D0 <= FCS_P_D0; --store edge state
if(LAN_ACCESS = '1' and FCS_SM_N_D0 /= FCS_N_D0) then
LAN_CYCLE_IN_PROGRESS <='1';
elsif(FCS_SM_P_D0 /= FCS_P_D0) then
LAN_CYCLE_IN_PROGRESS <='0';
end if;
case LAN_SM is
when nop=>
--cycle start!
@@ -380,23 +419,27 @@ begin
end if;
end if;
if(Z3_ADR(15)='1')then
if(Z3_DS < "1111" and LAN_ACCESS = '1' and FCS='0')then
if(Z3_ADR(15)='1')then
LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
elsif(RW='1')then --read from MSB
if(Z3_DS(3 downto 2) < "11")then --determine bushalf
LAN_RD_S <= '1';
LAN_SM <= wait_read_upper;
else
LAN_RD_S <= '1';
LAN_SM <= wait_read_lower;
end if;
else
LAN_SM <= start_write_lower;
if(Z3_DS(3 downto 2) < "11")then -- determine bushalf
LAN_SM <= start_write_upper;
else
LAN_SM <= start_write_lower;
end if;
end if;
else
LAN_SM <= nop;
end if;
when start_read_upper=>
LAN_RD_S <= '1';
@@ -413,7 +456,7 @@ begin
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_read_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_read_lower;
@@ -435,7 +478,7 @@ begin
Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
end if;
LAN_READY <='1';
LAN_SM<=end_read_lower; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
when start_write_upper=>
-- swapped DS3/DS2 here: ENC624 is little endian
LAN_WRH_S <= not Z3_DS(2);
@@ -453,7 +496,7 @@ begin
if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
else
Z3_A_LOW <= '1';
LAN_SM <= start_write_lower;
@@ -467,10 +510,14 @@ begin
when wait_write_lower=>
Z3_A_LOW <= '1';
LAN_READY <='1';
LAN_SM<=end_write_lower;
when end_write_lower=>
LAN_SM<=wait_cycle_end;
when wait_cycle_end=>
LAN_READY <='1';
LAN_SM<=end_write_lower; -- stay here until cylce end
if(FCS_SM_P_D0 /= FCS_P_D0 or FCS ='1')then
LAN_SM <= nop;
else
LAN_SM<=wait_cycle_end; -- stay here until cylce end
end if;
when config_rw=>
LAN_READY <='1';
if(Z3_DS(3) ='0' and RW='0')then
@@ -478,7 +525,7 @@ begin
elsif(Z3_DS(1) ='0' and RW='0')then
LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
end if;
LAN_SM<=config_rw; -- stay here until cylce end
LAN_SM <= wait_cycle_end;
end case;
end if;
end process lan_rw_gen;
@@ -564,7 +611,7 @@ begin
when "100010" =>
D_Z2_OUT <= "1111" ;
if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
if(AUTO_CONFIG_Z2_DONE(1) = '0')then --reg (1)?!?! Why? it does not work with index 0 but it should!
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
end if;
end if;
@@ -645,7 +692,7 @@ begin
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
INT6_OUT <= '0' when CP_IRQ = '0' else
INT6_OUT <= '0' when INT6_SIG = '0' else
'Z';
OWN <= 'Z';
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
@@ -695,24 +742,31 @@ begin
--cp signal generation
cp_rw_gen: process (AMIGA_CLK)
cp_rw_gen: process (AMIGA_CLK,reset)
begin
if falling_edge(AMIGA_CLK) then
--default values
if(reset ='0')then
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
INT6_SIG <= '1';
elsif rising_edge(AMIGA_CLK) then
INT6_SIG <= CP_IRQ;
if(CP_ACCESS = '1' and DS='0' and AS='0')then --datastrobe and AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
else
CP_RD_S <= '1';
CP_WE_S <= '1';
CP_WE_QUIRK <= '1';
end if;
CP_WE_QUIRK <= CP_WE_S; --the clockport write must be low exactly one 7MHz cycle!
end if;
end process cp_rw_gen;
--for the future
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when AS='0' else '1';
CP_CS <= not CP_ACCESS;
CP_CS <= not CP_ACCESS when AS='0' else '1';
end Behavioral;
Logic/LAN_IDE/LAN_IDE_CP.vm6
+11689 -12800
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.xml
+1 -1
View File
File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.xst
+2 -2
View File
@@ -8,7 +8,7 @@ run
-p xc9500xl
-top LAN_IDE_CP
-opt_mode Speed
-opt_level 1
-opt_level 2
-iuc NO
-keep_hierarchy Yes
-netlist_hierarchy As_Optimized
@@ -17,7 +17,7 @@ run
-bus_delimiter <>
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Compact
-fsm_extract YES -fsm_encoding Gray
-safe_implementation No
-mux_extract Yes
-resource_sharing YES
Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
+21 -21
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Feb 28 22:57:29 2019">
<application stringID="NgdBuild" timeStamp="Thu Mar 07 23:50:43 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -70,38 +70,38 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="63"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="452"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="21"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="41"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="61"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="480"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="532"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="243"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="63"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="452"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="67"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="480"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="532"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="243"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
Logic/LAN_IDE/LAN_IDE_CP_pad.csv
+2 -2
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2-28-2019 10:58PM
3- 7-2019 11:51PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
@@ -118,7 +118,7 @@ P97,A<16>,I/O,I/O,BIDIR,,,,,,,,,
P98,TIE,,I/O,,,,,,,,,,
P99,GND,,GND,,,,,,,,,,
P100,OVR,O,I/O,OUTPUT,,,,,,,,,
P101,TIE,,I/O,,,,,,,,,,
P101,MTCR,I,I/O,INPUT,,,,,,,,,
P102,C3,I,I/O,INPUT,,,,,,,,,
P103,C1,I,I/O,INPUT,,,,,,,,,
P104,CFIN,I,I/O,INPUT,,,,,,,,,
1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 2-28-2019 10:58PM 3- 7-2019 11:51PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
118 P103,C1,I,I/O,INPUT,,,,,,,,,
119 P104,CFIN,I,I/O,INPUT,,,,,,,,,
120 P105,CFOUT,O,I/O,OUTPUT,,,,,,,,,
121 P106,SLAVE,O,I/O,OUTPUT,,,,,,,,,
122 P107,OWN,O,I/O,OUTPUT,,,,,,,,,
123 P108,GND,,GND,,,,,,,,,,
124 P109,VCC,,VCCIO,,,,,,,,,,
Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
+22 -22
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Feb 28 22:57:07 2019">
<application stringID="Xst" timeStamp="Thu Mar 07 23:50:26 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -61,7 +61,7 @@
<item DEFAULT="" label="-p" stringID="XST_P" value="xc9500xl"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="LAN_IDE_CP"/>
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="2"/>
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="YES" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="Yes"/>
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
@@ -71,7 +71,7 @@
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Compact"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Gray"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
@@ -79,10 +79,10 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="86">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="78"/>
<item dataType="int" stringID="XST_REGISTERS" value="71">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="62"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
@@ -97,8 +97,8 @@
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_REGISTERS" value="76">
<item dataType="int" stringID="XST_FLIPFLOPS" value="76"/>
<item dataType="int" stringID="XST_REGISTERS" value="59">
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
</section>
@@ -119,31 +119,31 @@
<item stringID="XST_IOS" value="117"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="1292">
<item dataType="int" stringID="XST_AND2" value="404"/>
<item dataType="int" stringID="XST_AND3" value="63"/>
<item dataType="int" stringID="XST_AND4" value="17"/>
<item dataType="int" stringID="XST_BELS" value="1402">
<item dataType="int" stringID="XST_AND2" value="452"/>
<item dataType="int" stringID="XST_AND3" value="66"/>
<item dataType="int" stringID="XST_AND4" value="23"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="480"/>
<item dataType="int" stringID="XST_OR2" value="250"/>
<item dataType="int" stringID="XST_XOR2" value="34"/>
<item dataType="int" stringID="XST_INV" value="532"/>
<item dataType="int" stringID="XST_OR2" value="243"/>
<item dataType="int" stringID="XST_XOR2" value="25"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="142">
<item dataType="int" stringID="XST_FD" value="3"/>
<item dataType="int" stringID="XST_FDC" value="22"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="134">
<item dataType="int" stringID="XST_FD" value="4"/>
<item dataType="int" stringID="XST_FDC" value="21"/>
<item dataType="int" stringID="XST_FDCE" value="7"/>
<item dataType="int" stringID="XST_FDP" value="41"/>
<item dataType="int" stringID="XST_FDPE" value="69"/>
<item dataType="int" stringID="XST_FDPE" value="61"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="114">
<item dataType="int" stringID="XST_IBUF" value="23"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="115">
<item dataType="int" stringID="XST_IBUF" value="24"/>
<item dataType="int" stringID="XST_OBUF" value="33"/>
</item>
</section>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="48"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="56"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
</section>
</application>
Logic/LAN_IDE/_ngo/netlist.lst
+1 -1
View File
@@ -1,2 +1,2 @@
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551391041
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1551999035
OK
Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
-3
View File
@@ -17,9 +17,6 @@
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">IDE_WAIT</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">MTCR</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ&lt;8&gt;</arg> to allow all signals assigned to this function block to be placed.
</msg>
Logic/LAN_IDE/_xmsgs/xst.xmsgs
+27 -3
View File
@@ -29,13 +29,13 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">BERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_SM_RST</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_BASEADR&lt;7:0&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">LAN_CYCLE_IN_PROGRESS</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">CONFIG_READY</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="1799" delta="old" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM &lt;<arg fmt="%s" index="2">LAN_SM</arg>&gt;.
@@ -173,6 +173,30 @@
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">LAN_A_INIT_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">LAN_IDE_CP</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">LAN_BASEADR_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">LAN_D_INIT_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LAN_IDE_CP</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;LAN_D_INIT_10&gt; &lt;LAN_D_INIT_11&gt; </arg>
</msg>
Logic/LAN_IDE/area.xds
+2 -2
View File
@@ -7,8 +7,8 @@
<Properties>
<property name="Synthesize - XST:Optimization Goal" value="Speed"/>
<property name="Synthesize - XST:Optimization Effort" value="Normal"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Compact"/>
<property name="Synthesize - XST:Optimization Effort" value="High"/>
<property name="Synthesize - XST:FSM Encoding Algorithm" value="Gray"/>
<property name="Synthesize - XST:Safe Implementation" value="No"/>
<property name="Synthesize - XST:Case Implementation Style" value="None"/>
</Properties>
Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
+2 -2
View File
@@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-02-28T21:24:44</DateModified>
<DateModified>2019-03-07T21:05:55</DateModified>
<ModuleName>LAN_IDE_CP</ModuleName>
<SummaryTimeStamp>2019-02-23T22:34:10</SummaryTimeStamp>
<SummaryTimeStamp>2019-02-28T22:58:23</SummaryTimeStamp>
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\</ImplementationReportsDirectory>
<DateInitialized>2016-12-13T22:08:29</DateInitialized>
Logic/LAN_IDE/log.txt
+4840 -3295
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/webtalk_pn.xml
+3 -2
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Feb 28 22:57:07 2019">
<application name="pn" timeStamp="Thu Mar 07 23:50:25 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -18,7 +18,8 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthFsmEncode" value="Compact" type="process"/>
<property name="PROP_SynthFsmEncode" value="Gray" type="process"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd
BIN
View File
Binary file not shown.