im3
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.14 secs
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Total CPU time to Xst completion: 0.15 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.14 secs
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Total CPU time to Xst completion: 0.16 secs
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--> Reading design: LAN_IDE_CP.prj
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@@ -111,6 +111,7 @@ Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:646 - Signal <LAN_SM_RST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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-----------------------------------------------------------------------
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@@ -119,7 +120,7 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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| Inputs | 4 |
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| Outputs | 14 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | LAN_SM_RST (positive) |
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| Reset | LAN_SM$or0000 (positive) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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@@ -198,7 +199,6 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 387.
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Found 1-bit register for signal <LAN_SM_RST>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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@@ -220,8 +220,8 @@ Unit <LAN_IDE_CP> synthesized.
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HDL Synthesis Report
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Macro Statistics
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# Registers : 85
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1-bit register : 77
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# Registers : 84
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1-bit register : 76
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14-bit register : 2
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16-bit register : 2
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3-bit register : 1
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@@ -343,8 +343,9 @@ INFO:Xst:2261 - The FF/Latch <LAN_A_INIT_3> in Unit <LAN_IDE_CP> is equivalent t
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
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implementation constraint: INIT=r : LAN_INT_ENABLE
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implementation constraint: INIT=s : D_Z2_OUT_3
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@@ -354,7 +355,6 @@ Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=s : D_Z2_OUT_1
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implementation constraint: INIT=s : D_Z2_OUT_0
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=r : LAN_D_INIT_8
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@@ -414,19 +414,19 @@ Cell Usage :
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# BELS : 1090
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# AND2 : 361
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# AND3 : 39
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# AND4 : 15
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# AND4 : 16
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# AND5 : 1
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# AND8 : 4
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# GND : 1
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# INV : 346
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# INV : 345
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# OR2 : 222
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# OR3 : 45
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# OR4 : 6
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# OR5 : 1
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# OR8 : 16
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# XOR2 : 33
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# FlipFlops/Latches : 154
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# FD : 4
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# FlipFlops/Latches : 153
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# FD : 3
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# FDC : 32
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# FDCE : 7
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# FDP : 42
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@@ -440,13 +440,13 @@ Cell Usage :
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Total REAL time to Xst completion: 9.00 secs
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Total CPU time to Xst completion: 9.16 secs
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Total CPU time to Xst completion: 9.25 secs
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-->
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Total memory usage is 4534788 kilobytes
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Total memory usage is 4534804 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 46 ( 0 filtered)
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Number of warnings : 47 ( 0 filtered)
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Number of infos : 11 ( 0 filtered)
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