Fixed an error in the debug-output and switched to "faulty xilinx"-pinout
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@@ -8,6 +8,9 @@
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<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">LAN_IDE_CP.ise</arg>'.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">DQ<5></arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P38</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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@@ -32,5 +35,8 @@
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">Z3</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1239" delta="new" >The global <arg fmt="%s" index="1">clock</arg> designation (BUFG) on signal '<arg fmt="%s" index="2">N37</arg>' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal.
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</msg>
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</messages>
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@@ -8,8 +8,5 @@
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" into library work</arg>
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</msg>
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</messages>
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