Fiexd Clockport-bug for >68040

This commit is contained in:
MHeinrichs
2021-07-30 01:13:50 +02:00
parent fdde3273e8
commit 61a36e326f
24 changed files with 25014 additions and 29714 deletions
+20 -12
View File
@@ -216,16 +216,19 @@ begin
lancp <= '0';
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
autoconfig <= '1';
elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
end if;
if(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
if(A(14 downto 13)<"11")then
lan_adr_sw <= '1';
end if;
lan_adr <= '1';
lancp <= '1';
elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
end if;
if(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
cp <= '1';
lancp <= '1';
elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
end if;
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
ide <= '1';
lancp <= '1';
end if;
@@ -278,20 +281,24 @@ begin
end process lan_rw_gen;
--cp signal generation
cp_rw_gen: process (AMIGA_CLK,AS)
cp_rw_gen: process (AMIGA_CLK,reset)
begin
if (AS = '1') then
if (reset = '0') then
CP_WE_QUIRK <= '1';
CP_WE_S <= '1';
CP_RD_S <= '1';
elsif falling_edge(AMIGA_CLK) then
--default values
CP_RD_S <= '1';
CP_WE_S <= '1';
if(cp = '1' and DS='0')then --datastrobe instead of AS!
CP_RD_S <= not RW;
CP_WE_S <= RW;
end if;
if(cp = '1' and AS='0' and RW ='1')then
CP_RD_S <= '0';
else
CP_RD_S <= '1';
end if;
if(cp = '1' and DS='0' and RW ='0')then --datastrobe instead of AS!!!
CP_WE_S <= '0';
else
CP_WE_S <= '1';
end if;
-- quirk to ensure the WE-Strobe is just one cycle!
CP_WE_QUIRK <= CP_WE_S;
end if;
end process cp_rw_gen;
@@ -489,6 +496,7 @@ begin
--D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
--D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and cp ='1' else
D when RW='0' and AS='0' and lancp ='1'
else (others => 'Z');