Z2-Firmware with working CP and LAN

This commit is contained in:
MHeinrichs
2019-02-21 13:53:40 +01:00
parent 11c25fe78d
commit 5fc99a4460
140 changed files with 49227 additions and 28406 deletions
+2 -1
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Feb 20 23:04:39 2019">
<application name="pn" timeStamp="Thu Feb 21 11:10:33 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@@ -19,6 +19,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthFsmEncode" value="Compact" type="process"/>
<property name="PROP_SynthOpt" value="Area" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>